DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Foreign Priority Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file, as electronically retrieved 10/16/2023. Information Disclosure Statement The information disclosure statement (IDS) submitted on 09/07/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Election/Restrictions Applicant’s election without traverse of Group I (claims 1-10 and 25) in the reply filed on 02/16/2026 is acknowledged. Claims 11-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/16/2026. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-2, 4-5, 8-10 and 25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Schart et al. (PG Pub 2017/0345714; hereinafter Schart ). The applied reference has a common Assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 1 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches a chip package 1000 , comprising: an electrically conductive carrier structure 56 ; a first power chip 44 arranged on the carrier structure (see Fig. 10) , wherein the first power chip comprises a first side (annotated “s1” in Fig. 10 above) with a control contact pad 44 (“G-pad”) and a controlled contact pad 44 (“S/D-pad”) of a first type (e.g. source or drain) , a second side (annotated “s2” in Fig. 10 above) opposite the first side (see Fig. 10) , the second side comprising a controlled contact pad 44 (“S/D-pad”) of a second type (e.g. source or drain) , and a control structure (gate) for controlling a current between the controlled contact pads (see Fig. 10) , wherein the control contact pad is electrically connected to the control structure by a via (annotated “via” in Fig. 10 above) ; a second power chip 42 arranged on the carrier structure (see Fig. 10), wherein the second power chip comprises a first side (annotated “s1” in Fig. 10 above) with a control contact pad 42 (“G-pad”) and a controlled contact pad 42 (“S/D-pad”) of a second type (e.g. source or drain), a second side (annotated “s2” in Fig. 10 above) opposite the first side (see Fig. 10), the second side comprising a controlled contact pad 42 (“S/D-pad”) of a first type (e.g. source or drain) , and a control structure (gate) for controlling a current between the controlled contact pads of the second power chip (see Fig. 10) , wherein the control contact pad is electrically connected to the control structure (see Fig. 10) ; a logic chip 46 with a logic contact pad (annotated “pad” in Fig. 10 above) ; a redistribution layer 10 ; and a mold material 22 at least partially encapsulating the carrier structure, the first power chip, the second power chip, and the logic chip (see Fig. 10) ; wherein the first power chip and the second power chip are arranged with their respective control contact pad facing the redistribution layer (see Fig. 10) , and the logic chip is arranged with the logic contact pad facing the redistribution layer (see Fig. 10) ; and wherein the redistribution layer electrically connects the logic contact pad with the respective control pads of the first power chip and of the second power chip (see Fig. 10) . Regarding claim 2 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches the carrier structure 56 is exposed at first main side (s2)(exposed to the mold 22) of the chip package 1000 , whereas the logic chip 46 is covered by the mold 22 on the first main side (see Fig. 10) . Regarding claim 4 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches a total thickness of a stack of the first power chip 44 and the carrier structure 56 (annotated “t1” in Fig. 10 above) is larger than a thickness of the logic chip (annotated “t2” in Fig. 10 above) (t1 > t2) , and wherein a total thickness of a stack of the second power chip and the carrier structure (annotated “t1” in Fig. 10 above) is larger than a thickness of the logic chip (t1 > t2) (see Fig. 10) . Regarding claim 5 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches the carrier structure 56 comprises an electrically conductive first portion (annotated “portion-1” in Fig. 10 above) contacting the first power chip 44 and an electrically conductive second portion (annotated “portion-2” in Fig. 10 above) contacting the second power chip 42 , and optionally comprises an electrically conductive connecting portion (annotated “connect” in Fig. 10 above) connecting the first portion and the second portion (see Fig. 10) . Regarding claim 8 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches the electrically conductive carrier 56 comprises or consists of copper (para [0070]; “The DCB substrate 56 may include a ceramic core 58 and layers of copper 60 arranged on one or both of the main surfaces of the ceramic core 58. For example, the ceramic material may include at least one of alumina (Al.sub.2O.sub.3), aluminum nitride ( AlN ), beryllium oxide ( BeO ), etc.”)) . Regarding claim 9 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches the currents (between Source and Drain) between the controlled pads of the first power chip 44 and the second power chip 42 , respectively, are vertical currents through the power chip and the chip package (see Fig. 10). Regarding claim 10 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches the first power chip 44 and the second power chip 42 are connected in a half- bridge configuration (see claim 1, Fig. 10 and para [0065]) ) . Regarding claim 25 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches a chip system (see claim limitations below) , comprising: at least one chip package of claim l (see claim 1) ; at least one further component of a group of further components, the group consisting of: a processor; a controller; a cooling structure (para [0037]; heat pipe) ; a power source; wherein the chip system is configured as a converter or a full bridge. The recited “ configured as a converter or a full bridge ” (i.e., function) does not structurally distinguish an apparatus claim from the prior art apparatus see In re Danly , 263 F.2d 844, 838 (CCPA 1959) (apparatus claims must distinguish in terms of structure rather than function). The only structural limitation that appears to be required for the prior art apparatus to be capable of performing the aforementioned function is having the chip package of claim 1 (see claim 1) and a cooling structure, which Schart clearly show s or in other words, the prior art appears to inherently possess the capability of performing the recited functions. "[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer." Atlas Powder Co. v. IRECO Inc ., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus, the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best , 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). See In re Swinehart , 439 F.2d 210 (CCPA 1971) to emphasize that “where the Patent [and Trademark] Office has reason to believe that a functional limitation asserted to be critical for establishing novelty in the claimed subject matter may, in fact be an inherent characteristic of the prior art, it possesses the authority to require the applicant to prove that the subject matter shown to be in the prior art does not possess the characteristic relied on."). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 3 is rejected under 35 U.S.C. 103 as being unpatentable over Schart , as applied to claim 1 above, and further in view of Feil et al. (PG Pub 2019/0267362; hereinafter Feil). Regarding claim 3 , refer to the Examiner’s mark-up of Fig. 10 provided above, Although, Schart teaches the controlled contact pad of the first type and the controlled contact pad of the second type, he does not explicitly teach “ the controlled contact pad of the first type is a source contact pad, and the controlled contact pad of the second type is a drain contact pad. ” In the same field of endeavor, refer to Fig. 2 -provided above, Feil teaches a transistor 31 (para [0084]) comprising: a controlled contact pad 36 of the first type is a source contact pad (see Fig. 2), and the controlled contact pad of the second type 38 is a drain contact pad (para [0084]). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the function of the controlled pad function as a source and drain, as taught by Feil, to transfer current from one pad to another. Claim(s) 6 is rejected under 35 U.S.C. 103 as being unpatentable over Schart , as applied to claim 1 above, and further in view of Kemper et al. (PG Pub 2008/0211091; hereinafter Kemper). Regarding claim 6 , refer to the Examiner’s mark-up of Fig. 10 provided above, Schart teaches the electrically conductive carrier structure 56 has a thickness (see Fig. 10). He does not explicitly teach the thickness “in a range from about 100 µm to about 300 µm.” In the same field of endeavor, refer to Fig. 1b provided above, Kemper teaches a power semiconductor package comprising: an electrically conductive carrier structure 14 has a thickness in a range from about 100 µm to about 300 µm (para [0013]; “a direct copper bonding (DCB) substrate within a copper or primarily copper-containing layer having a material thickness within the range of approximately 0.1 mm to approximately 1.0 mm”). In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the thickness of the carrier structure fall within the range from about 100 µm to about 300 µm, as taught by Kemper, for the purpose of choosing a suitable and well-recognized DCB substrate thickness. Allowable Subject Matter 4 . Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 7 contains allowable subject matter, because the prior art of record, either singularly or in combination, fails to disclose or suggest, in combination with the other elements in claim 7 , the electrically conductive carrier structure comprises an extension overlapping the logic chip, wherein the extension is electrically isolated from the logic chip by the mold material. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christina A Sylvia whose telephone number is (571)272-7474. The examiner can normally be reached on 8am-4pm (M-F). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-2063 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov . Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTINA A SYLVIA/ Examiner, Art Unit 2817 /MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817