DETAILED ACTION
This correspondence is in response to the communications received 12/09/2025. Claims 1, 12, and 15 have been amended. Claims 16-18 have been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of 1-15 and 19-20 in the reply filed on December 9, 2025 is acknowledged.
Claims 16-18 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 12/09/2025. The Examiner would like to thank the Applicant for correcting the mis-categorization of claims 19 and 20 which should be included in invention I, and not invention II as indicated in the Office Action of 10/20/2025. Claims 19 and 20 are therefore drawn to an elected invention, and not withdrawn.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 09/07/2023 and 09/25/2024 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 5 is objected to because of the following informalities: Neither claim 5, nor the claims it depends on, recite "carbonyl sulfide" prior to using the abbreviation "COS". Appropriate correction is required.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a method of forming a semiconductor device (100), the method comprising:
pretreating (S08, see pages 10 and 11, lines 8-31 and 1-12) a semiconductor substrate (105) comprising at least one buried power rail (120) for power transmission, based on a chemical reaction by supplying a pretreatment gas for surface treatment onto a backside of the semiconductor substrate (108);
forming (S10, see page 11, lines 13-25) at least one metal catalyst layer (140) on the backside of the semiconductor substrate so as to be at least partially aligned with the at least one buried power rail (see Fig. 8); and
forming (S20, see pages 12 and 13, lines 28-31 and 1-31) at least one backside via hole (145) by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE) (see Fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. (US 20220020666 A1) in view of Ramaswamy et al. (US 20050217569 A1) in view of Li et al. (US 10,134,634 B2).
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Regarding claim 1, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal disclose a method of forming a semiconductor device (see title), the method comprising:
a semiconductor substrate (“substrate 110”, where “substrate 110 is a semiconductor substrate”, [0024]) comprising at least one buried power rail (“buried power rail 170a”, [0035]) for power transmission (“170a and/or 170b may also be referred to as a supply power rail”, [0045], thus 170a transmits power);
forming at least one backside via hole (“TSV opening 110a”, [0059], as seen in Fig. 18A, 110a is in the backside of the substrate) by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate (“the TSV opening 110a, 110b, and/or 110c is formed with a high aspect ratio greater than about 5 in the substrate 110 by way of example but not limitation. In defining the TSV opening 110a, 110b, and/or 110c, a hard mask layer (not shown) is formed over the substrate 110 followed by forming a patterned photoresist layer (not shown) thereon. … The exposed hard mask layer is then etched, by a wet etch or dry etch process, using the patterned photoresist layer as a masking element to provide an opening”, [0059]) between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE) (Van Dal does not disclose a metal catalyst layer or using MACE, however a secondary reference will be utilized to teach this limitation below).
Van Dal fails to disclose “pretreating a semiconductor substrate based on a chemical reaction by supplying a pretreatment gas for surface treatment onto a backside of the semiconductor substrate;
forming at least one metal catalyst layer on the backside of the semiconductor substrate so as to be at least partially aligned with the at least one buried power rail; and
forming at least one backside via hole by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE).”
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However, in a similar field of endeavor, Figs. 7-9 of Ramaswamy teach pretreating a semiconductor substrate (“all such native oxide 54 from FIG. 7 has been removed in the cleaning gas feeding depicted by FIG. 8”, [0049], where 52 of Ramaswamy is equivalent to 110 of Van Dal, further, “after feeding of the cleaning gas, an elemental silicon comprising material 55 is deposited on semiconductor substrate 52 within deposition chamber 50”, [0052], thus the removal of the native oxide is a pretreatment as it occurs prior to deposition, and the cleaning gas is therefore a pretreatment gas) based on a chemical reaction (the cleaning gas necessarily utilizes a chemical reaction, as the cleaning process does not use mechanical polishing techniques such as grinding) by supplying a pretreatment gas for surface treatment onto a backside of the semiconductor substrate (as seen in Figs. 7-9, the removal of the native oxide occurs on the surface onto which further processing is carried out, thus as 110a of Van Dal is formed in the backside of 110 of Van Dal, the oxide removal process taught by Ramaswamy will also be performed on the backside of 110 of Van Dal).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “pretreating a semiconductor substrate based on a chemical reaction by supplying a pretreatment gas for surface treatment onto a backside of the semiconductor substrate” as taught by Ramaswamy in the system of Van Dal for the purpose of improving film quality and adhesion of subsequent layers by exposing a clean surface of the semiconductor substrate.
Van Dal in combination with Ramaswamy fails to disclose “forming at least one metal catalyst layer on the backside of the semiconductor substrate so as to be at least partially aligned with the at least one buried power rail; and
forming at least one backside via hole by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE).”
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However, in a similar field of endeavor, Fig. 1(a) of Li teaches forming at least one metal catalyst layer on the backside of the semiconductor substrate (“a layer of metal catalyst 114 is applied to be in close contact with the silicon substrate 106”, col. 5, lines 29-30 where 106 of Li is equivalent to 110 of Van Dal, as the MACE process taught by Li is being substituted for the traditional etch process used by Van Dal to form 110a, 114 of Li will be formed on the backside of 110 of Van Dal) so as to be at least partially aligned with the at least one buried power rail (as seen in Fig. 18A of Van Dal, 110a is aligned with 170a, therefore after the substitution of the MACE process of Li into Van Dal, 114 of Li will be aligned with 170a of Van Dal so that the subsequent via hole will expose 170a); and
forming at least one backside via hole by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE) (“an exemplary wet etching technique includes immersing the metal loaded sample or wafer in a solution of H2O2 and HF …whereby holes (h+) are injected into the silicon valence band by the catalytic reduction of H2O2 on metal surface: H2O2→H2O+h+. Therefore, the hole-bearing silicon volume is dissolved by HF and the metal catalyst 114 will move into the etched space to assist further etching”, col 5, lines 51, 59, where “Via one embodiment of MaCE, vertical pores are managed to be etched with a width down to 30 nm and aspect ratio over 100”, col. 6, lines 1-3, thus the MACE technique taught by Li will be used to form 110a of Van Dal where 110a would be formed between the original position of 114 of Li and 170a of Van Dal).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “forming at least one metal catalyst layer on the backside of the semiconductor substrate so as to be at least partially aligned with the at least one buried power rail; and
forming at least one backside via hole by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE)” as taught by Li in the system of Van Dal in combination with Ramaswamy for the purpose of optimizing the cost and speed of forming via holes (“MaCE shows superior performance over currently available DRIE as well as traditional wet etching. Embodiments of MaCE provide a solution for 3D micro- and nanomanufacturing with order-of-magnitudes lower cost and significantly broader range of 3D geometric options”, col. 6, lines 38-42).
Regarding claim 8, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy and Fig. 1(a) of Li disclose the method of claim 1, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal further disclose wherein a diameter or a width of the at least one metal catalyst layer is less than or equal to a width of the at least one buried power rail (“the TSV opening 110a, 110b, and/or 110c may have a circular plan-view profile, with a diameter that is less than the widths of the buried power rails 170a and 170b”, [0061], thus as the size of 110a is determined by the diameter of 114 of Li, 114 of Li must have a diameter less than the width of 170a of Van Dal), and
wherein the at least one metal catalyst layer is vertically aligned with (as seen in Fig. 18A, 110a is vertically aligned with 170a, thus 114 of Li will necessarily be vertically aligned with 170a) and spaced apart from the at least one buried power rail or vertically spaced apart from the at least one buried power rail within the width of the at least one buried power rail when viewed from a cross-section of the semiconductor substrate (prior to the MACE process taught by Li, 114 of Li will be vertically spaced apart from 170a when viewed from a cross-section of 110).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. (US 20220020666 A1) in view of Ramaswamy et al. (US 20050217569 A1) in view of Li et al. (US 10,134,634 B2) in view of Ahmed et al. (US 9,076,651 B1).
Regarding claim 3, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy and Fig. 1(a) of Li disclose the method of claim 1, Figs. 7-9 of Ramaswamy further disclose wherein the pretreatment gas comprises radicals activated in a remote plasma generator to remove a natural oxide layer (“a cleaning gas has been fed to within deposition chamber 50 effective to remove at least some of any native oxide formed on semiconductor substrate 52. In an exemplary preferred embodiment, all such native oxide 54 from FIG. 7 has been removed”, [0049], further, “Plasma may or may not be utilized, and whether remote or generated within the chamber”, [0051], Ramaswamy does not disclose radicals, however, a secondary reference will be utilized to teach this limitation below) on the backside of the semiconductor substrate (as discussed previously, since the subsequent processing steps, such as the formation of 110a of Van Dal, are carried out on the backside of the substrate, one of ordinary skill in the art would recognize that the backside of the substrate would require pretreatment).
Van Dal in combination with Ramaswamy and Li fails to disclose “wherein the pretreatment gas comprises radicals activated in a remote plasma generator”.
However, in a similar field of endeavor, Fig. 3 of Ahmed teaches wherein the pretreatment gas comprises radicals activated in a remote plasma generator (“Plasmas are widely used for a variety of treatment and layer deposition tasks in semiconductor fabrication. These applications include subtractive processes such as … native oxide removal… "Remote" plasma sources are frequently used, where the plasma is located at some distance from the surface to be treated or substrate on which a layer is to be formed. The distance allows some adjusting of the charged particles in the plasma. For example, the density of ions and electrons can be adjusted by distance, the electrons and ions can be removed from the generated plasma using suitable electrode configurations such as a grounded metal showerhead, so that, for example, only atomic radicals and molecule radicals (but not ions) reach the substrate”, col. 6, lines 24-40).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the pretreatment gas comprises radicals activated in a remote plasma generator” as taught by Ahmed in the system of Van Dal, in combination with Ramaswamy and Li for the purpose of minimizing damage to the semiconductor substrate by high energy ions.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. (US 20220020666 A1) in view of Ramaswamy et al. (US 20050217569 A1) in view of Li et al. (US 10,134,634 B2) in view of Reilly et al. (US 9,847,222 B2).
Regarding claim 4, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy and Fig. 1(a) of Li disclose the method of claim 1, Figs. 7-9 of Ramaswamy further disclose wherein the pretreating comprises:
removing a natural oxide layer on the backside of the semiconductor substrate (“a cleaning gas has been fed to within deposition chamber 50 effective to remove at least some of any native oxide formed on semiconductor substrate 52”, [0049], and as discussed previously, since the subsequent processing steps, such as the formation of 110a of Van Dal, are carried out on the backside of the substrate, one of ordinary skill in the art would recognize that the backside of the substrate would require pretreatment).
Van Dal in combination with Ramaswamy and Li fails to disclose “wherein the pretreating comprises:
modifying the backside of the semiconductor substrate to have hydrophilic termination.”
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However, in a similar field of endeavor, Figs. 1 and 6 of Reilly teach wherein the pretreating comprises:
modifying the backside of the semiconductor substrate to have hydrophilic termination (“The surface treatment methods described herein create a hydrophilic surface to allow better wetting of subsequent deposition operations, without creating a thick high [wet etch rate] WER interface layer. In some implementations, the treatment results in a hydroxyl group (—OH) terminated surface, for example, with silicon-containing surfaces, the treatment may result in silanol (Si—OH) terminated surfaces”, col. 8, lines 33-40, where “the treatment may involve exposure to a single plasma chemistry. FIG. 6 shows a process flow of an example of such a treatment. First, a remote plasma is generated from a process gas including one or more reducing compounds … and one or more oxidizing compounds …. Next, the substrate is exposed to the remote plasma (block 603). As described above with respect to FIG. 5, the substrate may be exposed primarily to radical plasma species with relatively few or substantially no ionic species present. In some embodiments, the substrate may be exposed H radicals, oxygen (O) radicals, and/or hydroxyl (OH) radicals”, col. 9, lines 46-63).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement teaches “wherein the pretreating comprises:
modifying the backside of the semiconductor substrate to have hydrophilic termination” as taught by Reilly in the system of Van Dal, in combination with Ramaswamy and Li for the purpose of improving wettability of the substrate without forming thick interfacial layers.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. (US 20220020666 A1) in view of Ramaswamy et al. (US 20050217569 A1) in view of Li et al. (US 10,134,634 B2) in view of Huang et al. (US 20220375751 A1).
Regarding claim 6, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy and Fig. 1(a) of Li disclose the method of claim 1.
Van Dal in combination with Ramaswamy and Li fails to disclose “wherein the pretreating and the forming of the at least one metal catalyst layer are performed in situ in one process chamber or different process chambers of one metal deposition module while maintaining a vacuum atmosphere.”
However, in a similar field of endeavor, Figs. 1 and 4 of Huang teach wherein the pretreating and the forming of the at least one metal catalyst layer are performed in situ in one process chamber or different process chambers of one metal deposition module while maintaining a vacuum atmosphere (“FIG. 4 illustrates an exemplary integrated vacuum processing system 400 that can be used to complete the processing sequence 100 illustrated in FIG. 1, according to certain embodiments. The vacuum processing system 400 has an internal volume which is isolated from ambient environment. As shown in FIG. 4, a plurality of processing chambers 402a, 402b, 402c, 402d are coupled to a first transfer chamber 404. The processing chambers 402a-402d may be used to perform any substrate related processes, such as annealing, chemical vapor deposition, physical vapor deposition, epitaxial process, etching process, thermal oxidation or thermal nitridation process, degassing etc”, [0054], thus the pretreatment process disclosed by Ramaswamy and the forming of the at least one metal catalyst layer disclosed by Li can be performed in different process chambers in a vacuum processing system that maintains a vacuum atmosphere during substrate transfer)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the pretreating and the forming of the at least one metal catalyst layer are performed in situ in one process chamber or different process chambers of one metal deposition module while maintaining a vacuum atmosphere” as taught by Huang in the system of Van Dal in combination with Ramaswamy and Li for the purpose of providing “an improved substrate processing system for cleaning a substrate surface prior to performing an epitaxial deposition process that minimizes substrate handling time and exposure to ambient environment” ([0005]).
Claims 11, 12, 13, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Van Dal et al. (US 20220020666 A1) in view of Ramaswamy et al. (US 20050217569 A1) in view of Li et al. (US 10,134,634 B2) in view of Yim et al (US 9,911,878 B2) in view of Hiblot et al. (US 10,811,315 B2).
Regarding claim 11, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy and Fig. 1(a) of Li disclose the method of claim 1, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal further disclose further comprising:
forming a buried conductive layer (“the TSV 198a and/or 198c are formed in the TSV opening 110a and/or 110c of the substrate 110”, [0063] where “the TSVs 198a, 198b, and/or 198c is formed by using a metallization process as well as the use of metal electroplating techniques to fill high aspect ratio openings to avoid a seam or void defect”, [0064], as metal is known in the art as conductive, 198a is therefore a buried conductive layer) to bury the at least one backside via hole (as seen in Fig. 19, 198a buries 110a).
Van Dal in combination with Ramaswamy and Li fails to disclose “further comprising:
removing the at least one metal catalyst layer descended to a bottom surface of the at least one backside via hole;
forming a liner dielectric layer on at least a side wall of the at least one backside via hole”.
However, in a similar field of endeavor, Figs. 1-3 of Yim teach further comprising:
removing the at least one metal catalyst layer descended to a bottom surface of the at least one backside via hole (“The process comprises (a) performing metal-assisted chemical etching on the substrate, (b) performing a clean, including partial or total removal of the metal used to assist the chemical etch”, col. 1, lines 35-38, the process taught by Yim occurs after the MACE step of Li therefore removing 114 of Li after having descended to a bottom surface of 110a of Van Dal);
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement further comprising:
removing the at least one metal catalyst layer descended to a bottom surface of the at least one backside via hole as taught by Yim in the system of Van Dal, in combination with Ramaswamy and Li for the purpose of controlling the exact composition of the materials in the final device, without compromising on the material chosen for the metal assisted chemical etch process.
Van Dal in combination with Ramaswamy, Li and Yim fails to disclose “further comprising:
forming a liner dielectric layer on at least a side wall of the at least one backside via hole”.
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However, in a similar field of endeavor, Figs. 1A-3B of Hiblot teach further comprising:
forming a liner dielectric layer on at least a side wall of the at least one backside via hole (“A conformal liner 20 is first deposited on the sidewalls and the bottom of the TSV opening 10. This is a dielectric material aimed at isolating the TSV from the surrounding silicon”, col. 5, lines 51-54, where 10 of Hiblot is equivalent to 110a of Van Dal, as seen in Fig. 2C, 20 is on a least a side wall of 10)
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “further comprising:
forming a liner dielectric layer on at least a side wall of the at least one backside via hole” as taught by Hiblot in the system of Van Dal in combination with Ramaswamy, Li and Yim for the purpose of isolating the TSV from the surrounding silicon as discussed above.
Regarding claim 12, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy, Fig. 1(a) of Li, Figs. 1-3 of Yim, and Figs. 1A-3B of Hiblot disclose the method of claim 11, Figs. 1A-3B of Hiblot further disclose further comprising exposing the at least one buried power rail by removing at least a portion of the liner dielectric layer on the at least one buried power rail exposed by the at least one backside via hole after the at least one metal catalyst layer is removed (“At the bottom of the opening [10], the liner [20] is subsequently removed (FIG. 2D)”, col. 5, lines 57-58, after the substitution of 20 into the process disclosed by Van Dal, this would result in exposing 170a of Van Dal as 114 of Li has been removed as taught by Yim).
Regarding claim 13, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy, Fig. 1(a) of Li, Figs. 1-3 of Yim, and Figs. 1A-3B of Hiblot disclose the method of claim 11, Figs. 1A-3B of Hiblot further disclose wherein the forming of the liner dielectric layer comprises:
forming the liner dielectric layer on an inner surface of the at least one backside via hole (as seen in Fig. 2C, 20 is on an inner surface of 10); and
partially removing the liner dielectric layer on the bottom surface of the at least one backside via hole (“At the bottom of the opening [10], the liner [20] is subsequently removed (FIG. 2D)”, col. 5, lines 57-58) to leave the liner dielectric layer on the side wall of the at least one backside via hole (as seen in Fig. 2D, a portion of 20 is left on the sidewall of 10 after removing a portion of 20 on the bottom surface of 10).
Regarding claim 14, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy, Fig. 1(a) of Li, Figs. 1-3 of Yim, and Figs. 1A-3B of Hiblot disclose the method of claim 13, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal further disclose further comprising forming a diffusion barrier layer on the inner surface of the at least one backside via hole from which the liner dielectric layer is partially removed, so as to be connected to the at least one buried power rail (“a barrier layer (not shown) is used between the insulation layer and the TSV metal. The barrier layer may line the TSV opening 110a, 110b, and/or 110c. The barrier layer functions as a diffusion barrier to prevent metal diffusion”, [0064], as the barrier layer lines 110a, it is on the inner surface of 110a upon which 20 of Hiblot is removed, and will be connected to 170a),
wherein the buried conductive layer is formed in the at least one backside via hole so as to be connected to the diffusion barrier layer (as the barrier layer is formed to prevent diffusion of metal atoms, it must be connected to 198a to effectively stop atomic migration).
Regarding claim 15, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal in combination with Figs. 7-9 of Ramaswamy, Fig. 1(a) of Li, Figs. 1-3 of Yim, and Figs. 1A-3B of Hiblot disclose the method of claim 11.
Van Dal in combination with Ramaswamy, Li, Yim, and Hiblot do not directly disclose “wherein the at least one buried power rail, the at least one metal catalyst layer, and the buried conductive layer comprise the same metal.”
However, Figs. 1A, 1B, 2-13, 14A, 15-17, 18A, 19, 20A, and 20B of Van Dal teach wherein the at least one buried power rail and the buried conductive layer comprise the same metal (“trenches 160a and 160b are filled with a conductive material 170. In some embodiments, the conductive material 170 may include metal, such as tungsten (W), ruthenium (Ru), aluminum (Al), copper (Cu), or other suitable conductive material”, [0033], where “an etching process is performed to thin down the conductive material 170, such that a top surface of the conductive material 170 is lowered to a level below a top surface of the isolation dielectric 160, and thus buried power rails 170a and 170b are formed”, [0035], further “a conductive layer is plated on the wafer W1 by the plating process to fill the TSV opening 110a, 110b, and/or 110c. … the conductive layer may comprise various materials, such as tungsten, ruthenium, aluminum, gold, silver, and the like”, [0065], where “the excess portions of the conductive layer… are removed … The remaining portions of the conductive layer and the barrier layer in the TSV opening 110a, 110b, and/or 110c forms the TSV 198a, 198b, and/or 198c”, [0066], thus while Van Dal does not disclose 170a being formed from gold, Van Dal states that 170a could be made from other suitable materials and as gold is included in the list of possible materials of 198a along with tungsten, ruthenium, and aluminum which are listed as possible materials for both 170a and 198a, one of ordinary skill in the art would recognize gold as a suitable material from which both 170a and 198a could be formed).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the at least one buried power rail and the buried conductive layer comprise the same metal” as taught by Van Dal in the system of Van Dal in combination with Ramaswamy, Li, Yim, and Hiblot for the purpose of simplifying manufacturing by minimizing the number of necessary materials.
Fig. 1(a) of Li further discloses wherein the at least one buried power rail, the at least one metal catalyst layer, and the buried conductive layer comprise the same metal (“a layer of metal catalyst 114 is applied to be in close contact with the silicon substrate 106. In order to ensure uniform etching across the whole wafer (e.g., 4 inch wafer), the thickness of the noble metal catalysts on the whole wafer should be uniform, e.g., having variation below 1 nm. In one embodiment, gold (Au) catalyst can be deposited through electron-beam evaporation (EBE) for uniform MaCE”, col. 5, lines 29-36, thus 170a and 198a of Van Dal and 114 of Li are all formed of gold and therefore comprise the same metal).
Allowable Subject Matter
Claims 2, 5, 7, 9, and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the method of forming a semiconductor device as recited in the claims of the instant application.
Regarding claim 2, the prior art of Van Dal et al. (US 20220020666 A1) in combination with Ramaswamy et al. (US 20050217569 A1) and Li et al. (US 10,134,634 B2) discloses a method of forming a semiconductor device but fails to disclose the specific claims of the instant application regarding the use of carbonyl sulfide (COS) in a non-plasma, thermal treatment e.g. “wherein the pretreatment gas comprises carbonyl sulfide (COS) gas for removing a natural oxide layer on the backside of the semiconductor substrate, and
wherein the pretreating uses non-plasma thermal activation to prevent plasma damage to the semiconductor substrate”.
Regarding claim 5, the prior art of Van Dal et al. (US 20220020666 A1) in combination with Ramaswamy et al. (US 20050217569 A1), Li et al. (US 10,134,634 B2), and Reilly et al. (US 9,847,222 B2) discloses a method of forming a semiconductor device but fails to disclose the specific claims of the instant application e.g. “wherein the removing of the natural oxide layer is performed by providing COS gas”.
Regarding claim 7, the prior art of Van Dal et al. (US 20220020666 A1) in combination with Ramaswamy et al. (US 20050217569 A1) and Li et al. (US 10,134,634 B2) discloses a method of forming a semiconductor device but fails to disclose the specific claims of the instant application regarding the arrangement and geometry of the liner insulating layer with respect to the at least one buried power rail and the at least one metal catalyst layer e.g. “wherein at least a top surface and side walls of the at least one buried power rail are surrounded by a liner insulating layer when viewed from the backside of the semiconductor substrate, and
wherein, in the forming of the at least one backside via hole, the etching of the semiconductor substrate is stopped when the at least one metal catalyst layer is at least partially in contact with the liner insulating layer”.
Regarding claim 9, the prior art of Van Dal et al. (US 20220020666 A1) in combination with Ramaswamy et al. (US 20050217569 A1) and Li et al. (US 10,134,634 B2) discloses a method of forming a semiconductor device but fails to disclose the specific claims of the instant application regarding the geometry of the passivation insulating layer with respect to the at least one buried power rail and the at least one metal catalyst layer e.g. “a passivation insulating layer having an opening at least partially aligned with the at least one buried power rail,
wherein the at least one metal catalyst layer is formed in the opening of the passivation insulating layer.”
Claim 10 is allowable by virtue of its dependence on claim 9.
Claims 19 and 20 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the method of forming a semiconductor device as recited in the claims of the instant application.
Regarding claim 19, the prior art of Van Dal et al. (US 20220020666 A1) in combination with Ramaswamy et al. (US 20050217569 A1) and Li et al. (US 10,134,634 B2) discloses a method of forming a semiconductor device but fails to disclose the specific claims of the instant application regarding the interaction of the semiconductor substrate, the liner insulating layer and the at least one buried power rail during the metal assisted chemical etch process e.g. “forming at least one backside via hole by supplying an etchant to the semiconductor substrate to anisotropically etch the semiconductor substrate between the at least one metal catalyst layer and the at least one buried power rail while the at least one metal catalyst layer is descending into the semiconductor substrate by using metal assisted chemical etching (MACE) and to stop the etching of the semiconductor substrate when a liner insulating layer on the at least one buried power rail is at least partially exposed”.
Claim 20 is allowable by virtue of its dependence on claim 19.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893