DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 09/07/23 was/were received by the Examiner before the issuance/mailing date of the first office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) has/have been considered (except for anything in foreign language non-accompanied by an English translation) by the Examiner.
Claim Objections
Claim 10 is objected to because of the following informalities: claim 10 recites “an high bandwidth memory”. This is incorrect and should rather be “a high bandwidth memory”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8 and 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 8, 17 and 18 each recites “the seed metal layer comprises seed metal forming the metal TIM”. This is found undescriptive of the invention because as written, it means that the seed metal (350) is an integral part of the metal TIM (370) while this is not the case. [0030] of the PGPub of this application recites “The seed metal layer 350 may be used in an electroplating process for forming a metal TIM 370”, so the seed metal layer is used for forming the metal TIM that is what needs to be expressed in the claims. So, the Examiner has assumed “for forming”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 7-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Touzelbaev et al. (US 2009/0057877).
a. Re claim 1, Touzelbaev et al. disclose a semiconductor package comprising: a first substrate 110 (see figs. 1-3 and related text; see [0025] and remaining of disclosure for more details); a first chip structure 125 ([0026]) on the first substrate, the first chip structure comprising (i.e. being) at least one chip; a heat dissipation member 180 (see [0032]-0035]) on the first chip structure, the heat dissipation member comprising: a heat dissipation plate 210 comprising a first (bottom) surface facing the first chip structure and a second (top) surface opposite to the first surface; and a seed metal layer 220&230&240 on the second surface of the heat dissipation plate; and a metal thermal interfacial material (TIM) 190 (when it is indium as disclosed in [0032]-[0033]) on the seed metal layer.
b. Re claim 7, the seed metal layer comprises: a first layer 220 on the second surface of the heat dissipation plate, the first layer comprising titanium ([0035]); a second layer 230 on the first layer, the second layer comprising nickel ([0035]); and a third layer 240 on the second layer, the third layer comprising gold ([0035]).
c. Re claim 8 and in view of the 112 1st rejection above, the seed metal layer comprises (i.e. is) seed metal for forming the metal TIM (the Examiner notes that since metal layer 240 supports the TIM 190, it can be reasonably assumed that layer 240 is for forming TIM 190 thereon; in the alternative, the Examiner notes that a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. See, e.g., In re Pearson, 181 USPQ 641 (CCPA); In re Minks, 169 USPQ 120 (Bd Appeals); In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963). See MPEP §2114. The recitation of “for forming” does not distinguish the present invention over the prior art of Touzelbaev et al. who teach the structure as claimed).
d. Re claim 9, a thermal conductivity of the metal TIM is within a range of 50 W/mK to 100 W/mK (the thermal conductivity of indium is conventionally known to be 82-86 W/mK).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Touzelbaev et al. (US 2009/0057877).
a. Re claim 2, Touzelbaev et al. all the limitations of claim 1 as stated above including that the first chip structure comprises a plurality of chips (memory devices disclosed in [0026]), except explicitly that the plurality of chips are in a vertical direction. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the plurality of chips vertically stacked and electrically connected via through-substrate vias, and this as a non-inventive step of providing a plurality of chips according to one of the two known configurations (the other configuration being disposing the plurality of chips side-by-side) for providing a plurality of chips on a wiring substrate and that achieves faster signal transmission between chips through through-substrate vias (see MPEP 2143.E and 2144.I&II).
b. Re claim 3, Touzelbaev et al. all the limitations of claim 2 as stated above except explicitly that the first chip structure comprises a high bandwidth memory (HBM) package. However, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided the first chip structure comprises a high bandwidth memory (HBM) package in an application requiring such a first structure to be a HBM package that would benefit from the advantageous thermal performance disclosed by Touzelbaev et al. (see MPEP 2144.I&II).
c. Re claim 4, Touzelbaev et al. all the limitations of claim 2 as stated above except explicitly that a thickness of a top-layer semiconductor chip, disposed uppermost, of the plurality of chips disposed in the first chip structure is within a range of 50μm to 100μm. However, it is conventionally known to provide a chip to a thickness down to 50 microns to achieve a thin and light weight chip. As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided each chip of the plurality of chips, thus also a top-layer semiconductor chip, disposed uppermost, of the plurality of chips disposed in the first chip structure, to have a thickness of 50μm in order to obtain a thinner and lighter first chip structure, thus also a thinner and lighter package 100 (see MPEP 2144.I&II).
Claim(s) 11-14 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2017/0162542) in view of Touzelbaev et al. (US 2009/0057877).
a. Re claim 11, Chen et al. disclose a semiconductor package comprising: a first substrate 18 (see figs. 1A-H and related text; see [0016] and remaining of disclosure for more details); a first chip structure 12 (left; [0015]) and a second chip structure 10 (or 12 on the right; [0015]) in a first horizontal direction on the first substrate; and a metal thermal interfacial material (TIM) 58 (indium or silver solder; [0020]) on the [first and second chip structures]. But Chen et al. do not appear to explicitly disclose a heat dissipation member on the first chip structure and the second chip structure, the heat dissipation member comprising: a heat dissipation plate that comprises a first surface facing the first chip structure and the second chip structure and a second surface opposite to the first surface; and a seed metal layer on the second surface of the heat dissipation plate.
However, Touzelbaev et al. disclose providing a heat dissipation member 180 (see figs. 1-3 and related text) on a chip structure 125, the heat dissipation member comprising: a heat dissipation plate 210 ([0035]) that comprises a first (bottom) surface facing the chip structure and a second (top) surface opposite to the first surface, and a seed metal layer 220&230&240 on the second surface of the heat dissipation plate, wherein a lid 170 is bonded via an indium solder 190 to chip structure (see [0032]-[0033]), and this in order to provide for a low thermal resistance pathway between a lid 120 and the chip structure while securing enhanced bonding and preventing diffusion of metal into the chip structure (see [0032]).
As such, it would have been obvious to one skilled in the art before the effective filing date of the invention to have provided a heat dissipation member on the first chip structure and the second chip structure, the heat dissipation member comprising: a heat dissipation plate that comprises a first (bottom) surface facing the first chip structure and the second chip structure and a second (top) surface opposite to the first surface; and a seed metal layer on the second surface of the heat dissipation plate, and this in order to provide for a low thermal resistance pathway between the lid 66 and the first and second chip structures while securing enhanced bonding and preventing diffusion of metal into the first and second chip structures. The modification would have resulted in the metal thermal interfacial material (TIM) being on the seed metal layer.
b. Re claim 12, one (chip structure 10 or chip structure 12 on the right) of the first chip structure and the second chip structure comprises a logic chip (a system-on-chip is implicitly a logic chip for chip structure 10, or the logic chip would be the logic chip 12a of the chip structure 12 on the right; see [0015]), and wherein the other (chip structure 12 on the left) of the first chip structure and the second chip structure comprises a high bandwidth memory (HBM) package comprising a plurality of memory chips in a vertical direction (see [0015]).
c. Re claim 13, the semiconductor package of claim 11, further comprises a package substrate 52 ([0018]) on a lower surface of the first substrate, wherein the first substrate comprises (i.e. is) an interposer substrate electrically connecting the first chip structure, the second chip structure, and the package substrate with one another (explicit on figs. 1A-C and related text).
d. Re claim 14, each of the first surface and the second surface of the heat dissipation plate is a substantially flat surface (the top surfaces of the first and second chip structures are flat, so each of the first surface and the second surface of the heat dissipation plate would be a substantially flat surface).
e. Re claims 16 and 17, see respectively claims 7 and 8 rejections above.
Allowable Subject Matter
Claims 5-6, 10 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 would be allowable assuming Applicants adopt the assumption made by the Examiner above for the problematic limitation.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Su et al. (US 2021/0280493), Sur et al. (US 6,724,078) and Chen et al. (US 2023/0026141) disclose structures similar to the claimed information.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PENIEL M GUMEDZOE whose telephone number is (571)270-3041. The examiner can normally be reached M-F: 9:00AM - 5:30PM.
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/PENIEL M GUMEDZOE/Primary Examiner, Art Unit 2899