DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-22 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/08/2026.
Claims 1-16 are still pending.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-2, 4-5, 8, and 10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5-9 of copending Application No. 18/371,531 (US20250107161A1-Mendez31). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 5-9 of copending Application No. 18/371,531 teach each limitation of claims 1-2, 4-5, 8, and 10. See below table.
Claims 12-13 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 15 of copending Application No. 18/371,531 in view of Mendez et al. ("Quantum Transport Simulations for Si- P δ-layer Tunnel Junctions", PPT presentation at 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (2021)-NPLMendez21PPT). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1 and 15 of copending Application No. 18/371,531 in view of NPLMendez21PPT, teach each limitation of claims 12-13. See below table.
Application 18/243,453 Mamaluy et al. (US20250089287A1-Mamaluy53)
Application 18/371,531 (US20250107161A1-Mendez31)
Claim 1
A charge-sensing semiconductor device, comprising:
a substrate body;
a source formed along a first sidewall of the substrate body;
a drain formed along a second sidewall of the substrate body;
first and second delta layers disposed on the substrate body and separated by a gap,
wherein the first delta layer is in contact with the source and
the second delta layer is in contact with the drain; and
a cap disposed over the first and second delta layers.
Claim 1
A semiconductor device having first and second conductivity regimes, comprising:
a substrate body;
a source formed along a first sidewall of the substrate body;
a drain formed along a second sidewall of the substrate body;
first and second delta layers disposed on the substrate body and separated by a gap,
wherein the first delta layer is in contact with the source and
the second delta layer is in contact with the drain; and
a cap disposed over the first and second delta layers,
wherein the semiconductor device has the first conductivity regime responsive to a first voltage between the drain and the source and has the second conductivity regime responsive to a second voltage between the drain and the source.
The claim under examination is directed to a charge-sensing semiconductor device with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers. The conflicting claim is directed to a semiconductor device having first and second conductivity regimes with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers.
The charge-sensing semiconductor device with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers is anticipated by the semiconductor device having first and second conductivity regimes with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of anticipation has been established.
Claim 2
he charge-sensing semiconductor device of claim 1,
wherein the first and second delta layers are embedded between the substrate body and the cap.
Claim 5
The semiconductor device of claim 1,
wherein the first and second delta layers are embedded between the substrate body and the cap.
The claim under examination is directed to a charge-sensing semiconductor device wherein the first and second delta layers are embedded between the substrate body and the cap; and the conflicting claim is directed to a semiconductor device having first and second conductivity regimes wherein the first and second delta layers are embedded between the substrate body and the cap.
The charge-sensing semiconductor device wherein the first and second delta layers are embedded between the substrate body and the cap, is anticipated by the semiconductor device having first and second conductivity regimes wherein the first and second delta layers are embedded between the substrate body and the cap.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of anticipation has been established.
Claim 4
The charge-sensing semiconductor device of claim 1,
wherein the first and second delta layers are formed by thin layers of phosphorus.
Claim 6
The semiconductor device of claim 1,
wherein the first and second delta layers are formed by thin layers of phosphorus.
The claim under examination is directed to a charge-sensing semiconductor device wherein the first and second delta layers are formed by thin layers of phosphorus; and the conflicting claim is directed to a semiconductor device having first and second conductivity regimes wherein the first and second delta layers are formed by thin layers of phosphorus.
The charge-sensing semiconductor device wherein the first and second delta layers are formed by thin layers of phosphorus, is anticipated by the semiconductor device having first and second conductivity regimes wherein the first and second delta layers are formed by thin layers of phosphorus.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of anticipation has been established.
Claim 5
The charge-sensing semiconductor device of claim 1,
wherein the substrate body and the cap are formed of a semiconductor material.
Claim 7
The semiconductor device of claim 1,
wherein the substrate body and the cap are formed of a semiconductor material.
The claim under examination is directed to a charge-sensing semiconductor device wherein the substrate body and the cap are formed of a semiconductor material.; and the conflicting claim is directed to a semiconductor device having first and second conductivity regimes wherein the substrate body and the cap are formed of a semiconductor material.
The charge-sensing semiconductor device wherein the substrate body and the cap are formed of a semiconductor material, is anticipated by the semiconductor device having first and second conductivity regimes wherein the substrate body and the cap are formed of a semiconductor material.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of anticipation has been established.
Claim 8
The charge-sensing semiconductor device of claim 1,
wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap.
Claim 8
The semiconductor device of claim 1,
wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap.
The claim under examination is directed to a charge-sensing semiconductor device wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap; and the conflicting claim is directed to a semiconductor device having first and second conductivity regimes wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap.
The charge-sensing semiconductor device wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap, is anticipated by the semiconductor device having first and second conductivity regimes wherein the first delta layer extends from the source into a region between the substrate body and the cap, and wherein the second delta layer extends from the drain into another region between the substrate body and the cap.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of anticipation has been established.
Claim 10
The charge-sensing semiconductor device of claim 1,
wherein the gap separating the two delta layers is between 4 nano-meters and 20 nano-meters.
Claim 9
The semiconductor device of claim 1,
wherein the gap separating the two delta layers is between 2 nano-meters and 12 nano-meters.
The claim under examination is directed to a charge-sensing semiconductor device wherein the gap separating the two delta layers is between 4 nano-meters and 20 nano-meters; and the conflicting claim is directed to a semiconductor device having first and second conductivity regimes wherein the gap separating the two delta layers is between 4 nano-meters and 20 nano-meters.
The charge-sensing semiconductor device wherein the gap separating the two delta layers is between 4 nano-meters and 20 nano-meters, is anticipated by the semiconductor device having first and second conductivity regimes wherein the gap separating the two delta layers is between 4 nano-meters and 20 nano-meters.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of anticipation has been established.
Claim 12
A charge-sensing semiconductor device, comprising:
a substrate body;
a source formed along a first sidewall of the substrate body;
a drain formed along a second sidewall of the substrate body;
first and second delta layers disposed on the substrate body and separated by a gap,
wherein the first delta layer is in contact with the source and
the second delta layer is in contact with the drain; and
a cap disposed over the first and second delta layers,
wherein the first and second delta layers are embedded between the substrate body and the cap, and
wherein the gap separating the first and second delta layers has a controlled width to enable tunable charge sensing capability.
Claim 1
A semiconductor device having first and second conductivity regimes, comprising:
a substrate body;
a source formed along a first sidewall of the substrate body;
a drain formed along a second sidewall of the substrate body;
first and second delta layers disposed on the substrate body and separated by a gap,
wherein the first delta layer is in contact with the source and
the second delta layer is in contact with the drain; and
a cap disposed over the first and second delta layers,
wherein the semiconductor device has the first conductivity regime responsive to a first voltage between the drain and the source and has the second conductivity regime responsive to a second voltage between the drain and the source.
Claim 5
The semiconductor device of claim 1,
wherein the first and second delta layers are embedded between the substrate body and the cap.
The claim under examination is directed to a charge-sensing semiconductor device with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers, wherein the first and second delta layers are embedded between the substrate body and the cap. The conflicting claims are directed to a semiconductor device having first and second conductivity regimes with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers, wherein the first and second delta layers are embedded between the substrate body and the cap.
The charge-sensing semiconductor device with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers, wherein the first and second delta layers are embedded between the substrate body and the cap, is anticipated by the semiconductor device having first and second conductivity regimes with a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers, wherein the first and second delta layers are embedded between the substrate body and the cap.
Mendez31 fails to disclose a charge-sensing semiconductor device
wherein the gap separating the first and second delta layers has a controlled width to enable tunable charge sensing capability.
NPLMendez21PPT teaches a charge-sensing semiconductor device
wherein the gap separating the first and second delta layers has a controlled width to enable tunable charge sensing capability (low-energy electron contribution on the current is depressed with the tunnel gap width Lgap, so the gap width between the two delta layers tunes the charge sensing capability-Slide 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge-sensing semiconductor device of Mendez21 as taught by NPLMendez21PPT for the purpose of controlling a donor-molecule electron spin qubit in silicon (NPLMendez21PPT: Slide 2).
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of obviousness has been established.
Claim 13
The charge-sensing semiconductor device of claim 12,
wherein the first and second delta layers are formed by thin layers of phosphorus.
Claim 15
The semiconductor device of claim 10,
wherein the first and second delta layers are formed by thin layers of phosphorus.
The claim under examination is directed to a charge-sensing semiconductor device wherein the first and second delta layers are formed by thin layers of phosphorus; and the conflicting claim is directed to a semiconductor device having first and second conductivity regimes wherein the first and second delta layers are formed by thin layers of phosphorus.
The charge-sensing semiconductor device wherein the first and second delta layers are formed by thin layers of phosphorus, is anticipated by the semiconductor device having first and second conductivity regimes wherein the first and second delta layers are formed by thin layers of phosphorus.
MPEP 2112.01 states “Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
The claim under examination is directed to a charge-sensing semiconductor device while the conflicting claim is directed to a semiconductor device having first and second conductivity regimes. Both preambles are substantially identical in composition, as noted above, and a prima facie case of obviousness has been established.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 and 8-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mendez et al. ("Quantum Transport Simulations for Si- P δ-layer Tunnel Junctions", PPT presentation at 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (2021)-NPLMendez21PPT).
Regarding claim 1, NPLMendez21PPT discloses a charge-sensing semiconductor device (Examiner's annotated Slide 3), comprising:
a substrate body (Substrate body p-type Si Substrate-Examiner's annotated Slide 3);
a source formed along a first sidewall of the substrate body (Source formed along a first sidewall of the substrate body-Examiner's annotated Slide 3);
a drain formed along a second sidewall of the substrate body(Drain formed along a second sidewall of the substrate body-Examiner's annotated Slide 3);
first and second delta layers disposed on the substrate body and separated by a gap (First and second delta layers disposed on the substrate body, separated by a gap, and embedded between the substrate body and the cap-Examiner's annotated Slide 3),
wherein the first delta layer is in contact with the source (First delta layer disposed on the substrate body, separated from second delta-layer by a gap, and in contact with the source-Examiner's annotated Slide 3) and
the second delta layer is in contact with the drain (Second delta layer disposed on the substrate body, separated from first delta-layer by a gap, and in contact with the drain-Examiner's annotated Slide 3); and
a cap disposed over the first and second delta layers (Cap disposed over first and second delta layers-Examiner's annotated Slide 3).
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Regarding claim 2, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the first and second delta layers are embedded between the substrate body and the cap (First and second delta layers disposed on the substrate body, separated by a gap, and embedded between the substrate body and the cap-Examiner's annotated Slide 3).
Regarding claim 3, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the gap is embedded between the substrate body and the cap (Gap embedded between the substrate body and the cap-Examiner's annotated Slide 3).
Regarding claim 4, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the first and second delta layers are formed by thin layers of phosphorus (First and second delta layers are mono-layers of Phosphorus (P), so thin layers of Phosphorus-Examiner's annotated Slide 3).
Regarding claim 5, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the substrate body and the cap are formed of a semiconductor material (Silicon (Si) Gap and Silicon (Si) cap-Examiner's annotated Slide 3).
Regarding claim 6, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the substrate body and the cap are formed of silicon doped with a dopant (p-doped Silicon (Si) cap and p-type Silicon (Si) substrate body so formed of silicon doped with a dopant-Examiner's annotated Slide 3).
Regarding claim 8, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the first delta layer extends from the source into a region between the substrate body and the cap (First delta layer extending from the source into a region between the substrate body and the cap-Examiner's annotated Slide 3), and
wherein the second delta layer extends from the drain into another region between the substrate body and the cap (Second delta layer extending from the drain into a region between the substrate body and the cap-Examiner's annotated Slide 3).
Regarding claim 9, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the gap separating the two delta layers has a controlled width to enable tunable charge sensing capability (low-energy electron contribution on the current is depressed with the tunnel gap width Lgap, so the gap width between the two delta layers tunes the charge sensing capability-Slide 9).
Regarding claim 10, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the gap separating the two delta layers is between 4 nano-meters and 20 nano-meters (the gap width is 6nm so between 4nm and 20 nm-Slide 9).
Regarding claim 11, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the thickness of the delta layers is between 0.2 and 5 nm (Thickness of the delta layers can be 0.2nm, or 1.0nm, or 5.0nm so between 0.2 and 5nm-Slide 10).
Regarding claim 12, NPLMendez21PPT discloses a charge-sensing semiconductor device (Examiner's annotated Slide 3), comprising:
a substrate body (Substrate body p-type Si Substrate-Examiner's annotated Slide 3);
a source formed along a first sidewall of the substrate body (Source formed along a first sidewall of the substrate body-Examiner's annotated Slide 3);
a drain formed along a second sidewall of the substrate body(Drain formed along a second sidewall of the substrate body-Examiner's annotated Slide 3);
first and second delta layers disposed on the substrate body and separated by a gap (First and second delta layers disposed on the substrate body, separated by a gap, and embedded between the substrate body and the cap-Examiner's annotated Slide 3),
wherein the first delta layer is in contact with the source (First delta layer disposed on the substrate body, separated from second delta-layer by a gap, and in contact with the source-Examiner's annotated Slide 3) and
the second delta layer is in contact with the drain (Second delta layer disposed on the substrate body, separated from first delta-layer by a gap, and in contact with the drain-Examiner's annotated Slide 3); and
a cap disposed over the first and second delta layers (Cap disposed over first and second delta layers-Examiner's annotated Slide 3),
wherein the first and second delta layers are embedded between the substrate body and the cap (First and second delta layers disposed on the substrate body, separated by a gap, and embedded between the substrate body and the cap-Examiner's annotated Slide 3), and
wherein the gap separating the first and second delta layers has a controlled width to enable tunable charge sensing capability (low-energy electron contribution on the current is depressed with the tunnel gap width Lgap, so the gap width between the two delta layers tunes the charge sensing capability-Slide 9).
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Regarding claim 13, NPLMendez21PPT discloses all the elements of claim 12, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the first and second delta layers are formed by thin layers of phosphorus (First and second delta layers are mono-layers of Phosphorus (P), so thin layers of Phosphorus-Examiner's annotated Slide 3).
Regarding claim 14, NPLMendez21PPT discloses all the elements of claim 12, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the substrate body and the cap are formed of a semiconductor material (Silicon (Si) Gap and Silicon (Si) cap-Examiner's annotated Slide 3).
Regarding claim 15, NPLMendez21PPT discloses all the elements of claim 12, as noted above.
NPLMendez21PPT further discloses a charge-sensing semiconductor device
wherein the substrate body and the cap are formed of silicon doped with a dopant (p-doped Silicon (Si) cap and p-type Silicon (Si) substrate body so formed of silicon doped with a dopant-Examiner's annotated Slide 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mendez et al. ("Quantum Transport Simulations for Si- P δ-layer Tunnel Junctions", PPT presentation at 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) (2021)-NPLMendez21PPT) in view of Mamaluy et al. ("Revealing quantum effects in highly conductive δ-layer systems. Commun Phys 4, 205 (2021)-NPLMamaluy21).
Regarding claim 7, NPLMendez21PPT discloses all the elements of claim 1, as noted above.
NPLMendez21PPT does not disclose a charge-sensing semiconductor device
wherein the source and the drain are formed of a semiconductor material doped with a dopant.
NPLMamaluy21 teaches a charge-sensing semiconductor device
wherein the source and the drain are formed of a semiconductor material doped with a dopant (Source and drain having the same property as the channel, the channel being doped Silicon so doped semiconductor-[Results and Discussion] L1-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge-sensing semiconductor device of NPLMendez21PPT as taught by NPLMamaluy21 for the purpose of selectively filtering charge carriers based on their kinetic energy (NPLMamaluy21:[Conclusion] L11-13).
Regarding claim 16, NPLMendez21PPT discloses all the elements of claim 12, as noted above.
NPLMendez21PPT does not disclose a charge-sensing semiconductor device
wherein the source and the drain are formed of a semiconductor material doped with a dopant.
NPLMamaluy21 teaches a charge-sensing semiconductor device
wherein the source and the drain are formed of a semiconductor material doped with a dopant (Source and drain having the same property as the channel, the channel being doped Silicon so doped semiconductor-[Results and Discussion] L1-8).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the charge-sensing semiconductor device of NPLMendez21PPT as taught by NPLMamaluy21 for the purpose of selectively filtering charge carriers based on their kinetic energy (NPLMamaluy21:[Conclusion] L11-13).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Mendez et al. ("Quantum Transport Simulations for Si:P δ-layer Tunnel Junctions," 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, pp. 210-214-NPLMendez21Paper) discloses a charge-sensing semiconductor device comprising: a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers (Fig 2).
Gao et al. ("Modeling and Assessment of Atomic Precision Advanced Manufacturing (APAM) Enabled Vertical Tunneling Field Effect Transistor," 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2021, pp. 102-106-NPLGao21) discloses a charge-sensing semiconductor device (vertical tunneling TFET-Abstract) enables by APAM (Abstract).
Mendez et al. ("Conductivity and size quantization effects in semiconductor delta-layer systems.", Sci Rep 12, 16397 (2022)-NPLMendez22) discloses a charge-sensing semiconductor device comprising: a substrate body; a source formed along a first sidewall of the substrate body; a drain formed along a second sidewall of the substrate body; first and second delta layers disposed on the substrate body and separated by a gap, wherein the first delta layer is in contact with the source and the second delta layer is in contact with the drain; and a cap disposed over the first and second delta layers (Fig 1).
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 02/04/2026/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812