DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species II (claims 1-10) in the reply filed on 5/1/26 is acknowledged. However, based on claims 1-10, it appears the applicant intended Species I as this species (i.e. FIG. 1-4) shows (see, for example, paragraph [0022] of the specification) the drain region Da on a first surface (i.e. lower surface of the semiconductor chip 10 as shown in FIG. 4), and a source region Sa and gate region Ga on a second surface (i.e. upper surface of the semiconductor chip 10). On the other hand, Species II (i.e. FIG. 5-7) shows (see, for example, paragraph [0046], and [0049]) the drain region Da on the second surface, and the source region Sa and gate region Ga on a first surface. However, in lines 10-14 of claim 1, the applicant states limitations (i.e. first coating films 27 provided on an exposed major surface and side surfaces of the drain electrode 21, an exposed major surface of the source electrode 22, and an exposed major surface of the gate electrode 23; and second coating films 28 provided on an upper or lower surface and side surfaces of the mold layers 26) that are only disclosed in Species II (i.e. FIG. 5-7). It appears the limitations in claim 1 combine structural features that are disclosed in two separate species (i.e. Species I, and II). For the sake of compact prosecution, the Examiner will examine the claims as best ascertained by the Examiner even though the limitations in claims 1-10 are spread between multiple species. Examiner requests clarification to which Species (i.e. either FIG. 3 of Species I or FIG. 6 of Species II) the applicant elects.
Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as
being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/1/26.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “Sa” has been used to designate both source region and gate region. See paragraph [0029] and [0032]. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the (1) “a drain electrode provided in the drain region” (claim 1), (2) “a source electrode provided in the source region” (claim 1), (3) “a gate electrode provided in the gate region” (clam 1), (4) mold layers provided on … the gate electrode (claim 1) and (5) (a)“a semiconductor chip having a drain region on a first surface, and a source region and a gate region on a second surface facing the first surface;” … and (b) “first coating films provided on an exposed major surface and side surfaces of the drain electrode, an exposed major surface of the source electrode, and an exposed major surface of the gate electrode; and second coating films provided on an upper or lower surface and side surfaces of the mold layers.” (claim 1) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding (1), (2), and (3), the figures do not show the electrodes being “in” their
respective regions as disclosed in claim 1.
Regarding (4), FIG. 6, for example, shows the mold layer 26 next to the gate electrode
23, but not on the gate electrode 23.
Regarding (5), none of the drawings show both features in the same figure as (a) is shown
in FIG. 4 of Species I and (b) is shown in FIG. 7 of Species II, but none the figures show (a) and (b) in the same drawing and/or described in the same Species. This Drawing Objection is related to the 112 rejection above.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 thru 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As stated in the Election/Restrictions and Drawings paragraph above, claim 1 contains
limitations that are described in two separate species I, and II. Lines 2-3 of claim 1 are shown exclusively in FIG. 4 of Species I, and lines 9-13 of claim 1 are shown exclusively in FIG. 7 of Species II. Claim 1 is combining limitations from two separate species, which is not supported by the disclosure and not featured in the applicant’s drawings. Appropriate clarification and/or correction are required.
In line 4 of claim 1, the applicant states “a drain electrode provided in the drain region”;
however, it appears (see, for example, FIG. 4) that the drain electrode 11 is below the drain region Da. Appropriate clarification and/or correction are required.
In line 5 of claim 1, the applicant states “a source electrode provided in the source
region”; however, it appears (see, for example, FIG. 4) that the source electrode 12 is above the source region Sa. Appropriate clarification and/or correction are required.
In line 6 of claim 1, the applicant states “a gate electrode provided in the gate
region”; however, it appears (see, for example, FIG. 4) that the gate electrode 13 is above the gate region Ga. Appropriate clarification and/or correction are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In view of the 112 rejection above, claim(s) 1 thru 3, and 8 thru 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inutsuka et al. US 2023/0223310 A1 in view of Son et al. US 2010/0148328 A1 in view of Featherby et al. US 6,368,899 B1. Inutsuka discloses (see, for example, FIG. 3) a semiconductor device 20 comprising a semiconductor chip 41, drain electrode 41D, source electrode 41S, gate electrode 41P, mold layers 30, first coating films 46/45. The first coating films 46 is directly on an exposed major surface and side surfaces of the drain electrode 41D, and the first coating film 45 is on an exposed major surface of the source electrode 41S. The first coating films 45 is also on exposed major surface of the gate electrode 41P. In paragraph [0062], Inutsuka discloses the pad 41P is a pad for the gate electrode, and, therefore, a structure of the gate electrode. Inutsuka does not clearly disclose the drain electrode provided in the drain region, a source electrode provided in the source region, gate electrode provided in the gate region; however, it was well known in the art to have these electrodes in their respective regions for improving electrical contact between the electrode and its respective region for better speed, less resistance, better scalability. Son discloses (see, for example, FIG. 3, and paragraph [0018]) a semiconductor device comprising a drain electrode 125, source electrode 126, and gate electrode 124 that are in the semiconductor die 120. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the drain electrode provided in the drain region, a source electrode provided in the source region, gate electrode provided in the gate region in order to improve electrical contact between the electrode and its respective region for better speed, less resistance, better scalability. Further, regarding the limitations “drain region, source region, and gate region”, these regions are inherent in the semiconductor chip 41 as the drain electrode, source electrode, and gate electrodes are named because these electrodes are connected to these regions in a semiconductor chip.
Inutsuka in view of Son does not disclose a second coating films provided on an upper or lower surface and side surfaces of the mold layers. However, Featherby discloses (see, for example, FIG. 8) a semiconductor device comprising a mold layer 12, and second coating films 300/400. In column 11, lines 1-10, Featherby discloses the second coating films 300/400 provide a hermetic barrier than protects the semiconductor device from contaminants. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a second coating films provided on an upper or lower surface and side surfaces of the mold layers in order to protect the semiconductor device from contaminants.
Regarding claims 2-3, Inutsuka in view of Son in view of Featherby does not clearly disclose each of the drain electrode, the source electrode, and the gate electrode contains Cu and has a thickness of 50 um or greater or 150 um or greater and 300 um or less. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filming date, to have each of the drain electrode, the source electrode, and the gate electrode contains Cu and has a thickness of 50 um or greater or 150 um or greater and 300 um or less in order to have a material of minimal electrode resistance and parasitic capacitance, and since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 8, Featherby discloses (see, for example, column 12, lines 17-18) the
coating film 400 being an organic material, but does not specifically state the material being benzotriazole (BTA). It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the material being benzotriazole (BTA) in order to have a material that protects the semiconductor device from contamination, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 9, Featherby discloses the coating film may include metal oxides, but does not specifically disclose the first coating film includes one of a film containing Sn, a film containing Ni and Au, or a film containing Ni, Pd, and Au. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the first coating film includes one of a film containing Sn, a film containing Ni and Au, or a film containing Ni, Pd, and Au in order to have a material that protects the semiconductor device from contamination, and since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Regarding claim 10, see, for example, FIG. 3 wherein Inutsuka discloses the semiconductor device has a stacked structure in which the drain electrode 41D, the semiconductor chip 41, and the source electrode 41S are stacked in this order. Inutsuka in view of Son in view of Featherby does not clearly disclose a thickness of the stacking structure being 500 um or less. However, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filming date, to have a thickness of the stacking structure being 500 um or less in order to have a semiconductor device with strong mechanical support and manages thermal stress well, and since it has been held that discovering the optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 4 thru 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Inutsuka et al. US 2023/0112210 A1 in view of Son et al. US 2010/0148328 A1 in view of Featherby et al. US 6,368,899 B1 as applied to claims 1-3, and 8-10 above, and further in view of Park et al US 2023/0268204 A1. Inustsuka in view of Son in view of Featherby does not disclose a first electrode layer provided between the drain region of the semiconductor chip and the drain electrode, wherein the first electrode layer includes one of a stacked structure of Al, Ni, and Au, a stacked structure of Al, Ni, Pd, and Au, a stacked structure of Al and Cu, or a single-layer structure of Cu. However, Park discloses (see, for example, paragraph [0076]) a semiconductor device wherein the drain electrode may include multiple layers (i.e. first electrode layer) of copper (i.e. single-layer structure of Cu). It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a first electrode layer provided between the drain region of the semiconductor chip and the drain electrode, wherein the first electrode layer includes one of a stacked structure of Al, Ni, and Au, a stacked structure of Al, Ni, Pd, and Au, a stacked structure of Al and Cu, or a single-layer structure of Cu in order to improve structural durability, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 5, Inutsuka in view of Son in view of Featherby does not disclose a first conductive layer provided between the first electrode layer and the drain electrode, wherein the first conductive layer contains one of Ag, Cu, CuSn, AgSn, AuSn, or PbSn. However, Park discloses (see, for example, paragraph [0067]) the drain electrode may include multiple layers (i.e. first conductive layer) of copper (i.e. single-layer structure of Cu) that may include a first electrode layer and first conductive layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a first conductive layer provided between the first electrode layer and the drain electrode, wherein the first conductive layer contains one of Ag, Cu, CuSn, AgSn, AuSn, or PbSn in order to improve structural durability, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 6, Inutsuka in view of Son in view of Featherby does not disclose a second electrode layer provided between the source region of the semiconductor chip and the source electrode; and a third electrode layer provided between the gate region of the semiconductor chip and the gate electrode, wherein each of the second electrode layer and the third electrode layer includes one of a stacked structure of Al, Ni, and Au, a stacked structure of Al, Ni, Pd, and Au, a stacked structure of Al and Cu, or a single-layer structure of Cu. However, Park discloses (see, for example, paragraph [0076] and [0074]) the source electrode and gate electrode may include multiple layers of copper wherein such layers include a second electrode layer, and third electrode layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a second electrode layer provided between the source region of the semiconductor chip and the source electrode; and a third electrode layer provided between the gate region of the semiconductor chip and the gate electrode, wherein each of the second electrode layer and the third electrode layer includes one of a stacked structure of Al, Ni, and Au, a stacked structure of Al, Ni, Pd, and Au, a stacked structure of Al and Cu, or a single-layer structure of Cu in order to improve structural durability, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Regarding claim 7, Inustsuka in view of Son in view of Featherby does not disclose a second conductive layer provided between the source region of the semiconductor chip and the source electrode; and a third conductive layer provided between the gate region of the semiconductor chip and the gate electrode, wherein each of the second electrode layer and the third electrode layer includes one of a stacked structure of Al, Ni, and Au, a stacked structure of Al, Ni, Pd, and Au, a stacked structure of Al and Cu, or a single-layer structure of Cu. However, Park discloses (see, for example, paragraph [0076] and [0074]) the source electrode and gate electrode may include multiple layers of copper wherein such layers include a second conductive layer, and third conductive layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a second conductive layer provided between the source region of the semiconductor chip and the source electrode; and a third conductive layer provided between the gate region of the semiconductor chip and the gate electrode, wherein each of the second electrode layer and the third electrode layer includes one of a stacked structure of Al, Ni, and Au, a stacked structure of Al, Ni, Pd, and Au, a stacked structure of Al and Cu, or a single-layer structure of Cu in order to improve structural durability, and since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
INFORMATION ON HOW TO CONTACT THE USPTO
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JOSHUA BENITEZ can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
Eugene Lee
May 9, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
Prosecution Insights