Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6, 7 and 12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kinyua et al. (8,305,246), hereafter called KINYUA.
Regarding claims 1 and 7, KINYUA (Fig. 1) discloses an audio amplifier comprising: a digital input node configured to receive a digital audio input signal (InPCM); a signal processing chain (140, 150, 160 and 170) coupled to the digital input node, wherein the signal processing chain comprises a switching converter circuit (180) driven by a pulse-width-modulated (PWM) signal (172) and configured to provide an analog audio output signal (speaker 198) based on the digital audio input signal; a sensing circuit branch (R and C) in the feedback path coupled to sense the analog audio output signal and configured to provide an analog feedback signal indicative of the sensed analog audio output signal (198); wherein the signal processing chain comprises: a digital-to-analog (DAC) converter circuit (140 and also column 3, lines 1-18) configured to apply digital-to-analog conversion to the digital audio input signal to produce an analog replica of the digital input signal; a superposition node (Nrc and Nd0 – Ndn, of Fig. 3) coupled to the sensing circuit branch to receive the analog feedback signal and coupled to the DAC converter circuit to receive the analog replica of the digital input signal, wherein the superposition node is configured to produce an analog error signal indicative of a difference between the analog replica of the digital input signal and the analog feedback signal, see column 5, lines 17-20; an analog-to-digital converter (ADC) circuit (150) coupled to the superposition node to receive the analog error signal therefrom and configured to apply analog-to-digital conversion to the analog error signal to produce a digital error signal; a digital filter circuit (160) coupled to the ADC circuit to receive the digital error signal and configured to apply digital filtering to the digital error signal to produce a filtered digital error signal (162) as a result; and a pulse-width-modulation generator circuit (170) coupled to the digital filter circuit to receive the filtered digital error signal, wherein the pulse-width-modulation generator circuit is configured to drive said switching converter circuit (180) with the PWM signal produced based on the filtered digital error signal.
Regarding claims 6 and 12, wherein output signal is coupled to speaker (198).
Allowable Subject Matter
Claims 2-5 and 8-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 2-4, 8-10, prior art(s) does not disclose the analog output signal comprises an output voltage signal; the analog feedback signal indicative of the sensed analog voltage signal comprises a feedback current signal obtained as a ratio of the sensed analog voltage signal and a feedback resistive element; the DAC circuit is configured to apply digital-to-analog conversion to the digital input signal to convert the digital input signal to an input current signal; the analog error signal indicative of the difference between the input current signal and the feedback signal comprises an error current signal; and the ADC circuit is configured to apply transresistance analog-to-digital conversion to the error current signal to producing the digital error signal.
Regarding claims 5 and 11, prior art(s) does not disclose a feedforward circuit coupled to the input node to receive the digital audio input signal, wherein the feedforward circuit is configured to apply phase and magnitude correction to the digital input signal to produce a compensating digital signal; and an adder circuit coupled to the digital filter circuit to receive the filtered digital error signal, wherein the adder circuit is configured to add the compensating digital signal to the filtered digital error signal to provide the resulting sum signal to the PWM generator circuit; wherein the PWM generator circuit is configured to drive said switching converter circuit with the PWM signal produced based on the sum of the filtered digital error signal and the compensating digital signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843