DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt of Applicants’ specification amendments received on 13 and 14 September 2023.
Claim Objections
Claims 4, 11, and 18 are objected to because of the following informalities:
Claim 4, line 2, recites “through dielectric layer,” which should read “through the dielectric layer” for proper grammar and/or composition.
Claim 11, line 2, recites “through dielectric layer,” which should read “through the dielectric layer” for proper grammar and/or composition.
Claim 18, line 2, recites “through dielectric layer,” which should read “through the dielectric layer” for proper grammar and/or composition.
Claim 18, line 2, recites “to defines a gap,” which should read “to define a gap” for proper grammar and/or composition.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 9, 13, and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6, line 1, recites “the upper surface,” which is indefinite because it is unclear whether and/or how this upper surface differs from the second surface recited in base claim 1. For the purpose of compact prosecution and to better comport with base claim 1, the claim will be interpreted to recite “the second surface.”
Claim 9, line 2, recites “the S/D terminal,” which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution and to better comport with base claim 8, the claim will be interpreted to recite “the one S/D terminal.”
Claim 13, line 1, recites “the upper surface,” which is indefinite because it is unclear whether and/or how this upper surface differs from the second surface recited in base claim 8. For the purpose of compact prosecution and to better comport with base claim 8, the claim will be interpreted to recite “the second surface.”
Claim 19, lines 1 and 2, recites “the upper surface,” which is indefinite because it is unclear whether and/or how this upper surface differs from the second surface recited in base claim 15. For the purpose of compact prosecution and to better comport with base claim 15, the claim will be interpreted to recite “the second surface.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Zhao et al. (US20230095367A1).
Regarding claim 1, Zhao teaches in Fig. 1A (see annotated copy, below) a structure comprising:
a dielectric layer (120 and/or 122) over a substrate (102, 104, 106) and horizontally between a gate terminal (113) and a source/drain (S/D) terminal (124), wherein the dielectric layer (120 and/or 122) has a first surface (bottom surface) proximal to the substrate (102, 104, 106) and a second surface (top surface) opposite the first surface (bottom surface), wherein the dielectric layer (120 and/or 122) has a plurality of recesses in the second surface (top surface), and wherein at least some of the plurality of recesses have different depths {[0019, 0024]}; and
a conductive field plate (140) including a metal (e.g., Ti) layer on the second surface (top surface) and within the plurality of recesses, wherein the conductive field plate (140) is electrically isolated (e.g., by 120, 122, and/or 150) from the gate terminal (113) and the S/D terminal (124) {[0040]}.
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Regarding claim 2, Zhao teaches the structure of claim 1, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 1) wherein the depths of the recesses decrease between (e.g., between 142 and 130) the gate terminal (113) and the S/D terminal (124).
Regarding claim 3, Zhao teaches the structure of claim 1, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 1) wherein the metal layer (e.g., Ti) is on sidewalls of at least one of the plurality of recesses.
Regarding claim 4, Zhao teaches the structure of claim 1, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 1) wherein at least one of the plurality of recesses extends completely through [the] dielectric layer (120 and/or 122) and defines a gap (gap in which 142 is disposed) therein.
Regarding claim 5, Zhao teaches the structure of claim 1, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 1) wherein at least two of the plurality of recesses have distinct lengths {e.g., L1 and L2 in the annotated copy of Zhao’s Fig. 1A}.
Regarding claim 6, as interpreted in view of the indefiniteness rejection, Zhao teaches the structure of claim 1, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 1) wherein the second surface (top surface) of the dielectric layer (120 and/or 122) includes at least two segments having distinct lengths between respective pairs of the plurality of recesses {e.g., segments L3 and L4 have different lengths in the annotated copy of Zhao’s Fig. 1A}.
Regarding claim 7, Zhao teaches the structure of claim 1, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 1) wherein the substrate (102, 104, 106) includes a III-V semiconductor material and is within a high electron mobility transistor (HEMT) {[0020-0022]}.
Regarding claim 8, Zhao teaches in Fig. 1A (see annotated copy, below) a structure comprising:
a pair of source/drain (S/D) terminals (124, 126) over a substrate (102, 104, 106), the substrate (102, 104, 106) including a III-V semiconductor material {[0020, 0021, 0030]};
a gate terminal (113) over the substrate (102, 104, 106) and horizontally between the pair of S/D terminals (124, 126) {[0019]};
a dielectric layer (120 and/or 122) over the substrate (102, 104, 106) and horizontally between the gate terminal (113) and one (124) of the pair of S/D terminals (124, 126), wherein the dielectric layer (120 and/or 122) has a first surface (bottom surface) proximal to the substrate (102, 104, 106) and a second surface (top surface) opposite the first surface (bottom surface), wherein the dielectric layer (120 and/or 122) has a plurality of recesses in the second surface (top surface), and wherein at least some of the plurality of recesses have different depths {[0019, 0024]}; and
a conductive field plate (140) including a metal (e.g., Ti) layer on the second surface (top surface) and within the plurality of recesses, wherein the conductive field plate (140) is electrically isolated (e.g., by 120, 122, and/or 150) from the gate terminal (113) and the pair of S/D terminals (124, 126) {[0040]}.
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Regarding claim 9, as interpreted in view of the indefiniteness rejection, Zhao teaches the structure of claim 8, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 8) wherein the depths of the recesses decrease between (e.g., between 142 and 130) the gate terminal (113) and the one S/D terminal (124).
Regarding claim 10, Zhao teaches the structure of claim 8, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 8) wherein the metal (e.g., Ti) layer is on sidewalls of at least one of the plurality of recesses.
Regarding claim 11, Zhao teaches the structure of claim 8, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 8) wherein at least one of the plurality of recesses extends completely through [the] dielectric layer (120 and/or 122) and defines a gap (gap in which 142 is disposed) therein.
Regarding claim 12, Zhao teaches the structure of claim 8, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 8) wherein at least two of the plurality of recesses have distinct lengths {e.g., L1 and L2 in the annotated copy of Zhao’s Fig. 1A}.
Regarding claim 13, as interpreted in view of the indefiniteness rejection, Zhao teaches the structure of claim 8, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 8) wherein the second surface (top surface) of the dielectric layer (120 and/or 122) includes at least two segments having distinct lengths between respective pairs of the plurality of recesses {e.g., segments L3 and L4 have different lengths in the annotated copy of Zhao’s Fig. 1A}.
Regarding claim 14, Zhao teaches the structure of claim 8, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 8) wherein the substrate (102, 104, 106), the gate terminal (113), and the pair of S/D terminals (124, 126) define portions of a high electron mobility transistor (HEMT) {[0022]}.
Regarding claim 15, Zhao teaches in Fig. 1A (see annotated copy, below) a method comprising:
forming a dielectric layer (120 and/or 122) over a substrate (102, 104, 106) and horizontally between a gate terminal (113) and a source/drain (S/D) terminal (124), wherein the dielectric layer (120 and/or 122) has a first surface (bottom surface) proximal to the substrate (102, 104, 106) and a second surface (top surface) opposite the first surface (bottom surface), wherein the dielectric layer (120 and/or 122) has a plurality of recesses in the second surface (top surface), and wherein at least some of the plurality of recesses have different depths {[0019, 0024]}; and
forming a conductive field plate (140) including a metal (e.g., Ti) layer on the second surface (top surface) and within the plurality of recesses, wherein the conductive field plate (140) is electrically isolated from the gate terminal (113) and the S/D terminal (124) {[0040]}.
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Regarding claim 16, Zhao teaches the method of claim 15, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 15) further comprising forming at least two of the plurality of recesses to having decreasing depths between (e.g., between 142 and 130) the gate terminal (113) and the S/D terminal (124).
Regarding claim 17, Zhao teaches the method of claim 15, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 15) further comprising forming the metal (e.g., Ti) layer on sidewalls of at least one of the plurality of recesses.
Regarding claim 18, Zhao teaches the method of claim 15, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 15) wherein forming the dielectric layer (120 and/or 122) includes forming at least one of the plurality of recesses completely through [the] dielectric layer (120 and/or 122) to define[] a gap (gap in which 142 is disposed) within the dielectric layer (120 and/or 122).
Regarding claim 19, as interpreted in view of the indefiniteness rejection, Zhao teaches the method of claim 15, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 15) wherein forming the dielectric layer (120 and/or 122) includes forming the second surface (top surface) to include at least two segments having distinct lengths between respective pairs of the plurality of recesses {e.g., segments L3 and L4 have different lengths in the annotated copy of Zhao’s Fig. 1A}.
Regarding claim 20, Zhao teaches the method of claim 15, and Zhao further teaches in Fig. 1A (see annotated copy with respect to claim 15) further comprising forming a high electron mobility transistor (HEMT) by forming the S/D terminal (124), the gate terminal (113), and an additional S/D terminal (126) on the substrate (102, 104, 106), wherein the substrate (102, 104, 106) includes a III-V semiconductor material {[0020-0022]}.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Zhang et al. (US20210384303A1) teaches a semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.
Conclusion
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/D.W.W./ Examiner, Art Unit 2891
/MATTHEW C LANDAU/ Supervisory Patent Examiner, Art Unit 2891