DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 09/08/2023.
Currently claims 1-9 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/08/2023 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 7 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 1, the instant claim recites “the third transparent electrode" (claim 1, line 18). There is insufficient antecedent basis for this limitation in the claim. The “third transparent electrode” was not defined earlier. It is unclear whether the first “third transparent conductive layer” (claim 1, line 15) is being recalled or a new “third transparent electrode” is being introduced, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the claim will be interpreted as “the third transparent conductive layer”.
Regarding claim 7, the instant claim recites limitation in view of claim 5 where claim 7 recites, “the first substrate" (claim 7, line 2). There is insufficient antecedent basis for this limitation in the claim. The “first substrate” was not defined earlier. It is unclear whether the first “substrate” (claim 5, line 2) is being recalled or a new “first substrate” is being introduced, rendering the claim indefinite. Clarification and/or correction are/is required. For the purpose of examination, the claim will be interpreted as “the substrate”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by US 2022/0308378 A1 (Ozeki).
Regarding claim 1, Ozeki discloses, a display device (10; display device; Fig. 2; [0037] – [0045]) comprising a plurality of pixels (310) arranged in a matrix on a substrate (300; array substrate; Fig. 2; [0037]) along a first direction (D1) and a second direction (D2) intersecting the first direction (D1),
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each of the plurality of pixels (310) comprises: a transistor (Tr1; Fig. 4; [0046]);
a first transparent conductive layer (ZTCO; connecting electrode; Fig. 4; [0046]) arranged over the transistor (Tr1) and electrically connected to the transistor (Tr1) ;
a first insulating layer (IL4; Fig. 4; [0052]) arranged over the first transparent conductive layer (ZTCO);
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a second transparent conductive layer (PTCO; pixel electrode; Fig. 4; [0052]) arranged in the first insulating layer (IL4) and electrically connected to the first transparent conductive layer (ZTCO) via an opening (as annotated on Fig. 4) extending over the plurality of pixels (310) arranged in line in the first direction (D1);
a filling member (IL5; Fig. 4; [0053]) arranged over the second transparent conductive layer (PTCO) to fill the interior of the opening;
a third transparent conductive layer (CTCO; common electrode; Fig. 4; [0053]) arranged on the first insulating layer (IL4) and the filling member (IL5) (Fig. 4; [0053]);
a metal layer (CMTL; common auxiliary electrode; Fig. 4; [0053]) in contact with the third transparent electrode (CTCO).
Regarding claim 2, Ozeki discloses, the display device according to claim 1, wherein the transistor (TR1) has an oxide semiconductor layer (OS1), a gate wiring (GL1) opposite the oxide semiconductor layer (OS1), and a gate insulating layer (GI1) between the oxide semiconductor layer (OS1) and the gate wiring (GL1), and the gate wiring (GL1) extends along the first direction (D1) overlapping on the opening (Figs. 4 and 5; [0047] – [0049]).
Regarding claim 3, Ozeki discloses, the display device according to claim 1, wherein the filling member (IL5) has a protruding portion (on both sides of the opening) protruding above a top surface of the second transparent conductive layer (PTCO) arranged above the first insulating layer (IL4).
Claims 5-8 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by US 2022/0308378 A1 (Ozeki).
Regarding claim 5, Ozeki discloses, a display device (10; display device; Fig. 2; [0037] – [0045]) comprising a plurality of pixels (310) arranged in a matrix on a substrate (300; array substrate; Fig. 2; [0037]) along a first direction (D1) and a second direction (D2) intersecting the first direction (D1),
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each of the plurality of pixels (310) comprises: a transistor (Tr1; Fig. 4; [0046]);
a first transparent conductive layer (ZTCO; connecting electrode; Fig. 4; [0046]) arranged over the transistor (Tr1) and electrically connected to the transistor (Tr1) ;
a first insulating layer (IL4; Fig. 4; [0052]) arranged over the first transparent conductive layer (ZTCO);
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a second transparent conductive layer (PTCO; pixel electrode; Fig. 4; [0052]) arranged in the first insulating layer (IL4) and electrically connected to the first transparent conductive layer (ZTCO) via an opening (as annotated on Fig. 4) extending over the plurality of pixels (310) arranged in line in the first direction (D1);
a second insulating layer (IL5; Fig. 4; [0053]) arranged over the second transparent conductive layer (PTCO);
a third transparent conductive layer (CTCO; common electrode; Fig. 4; [0053]) arranged over the second insulating layer (IL5);
a filling member (SP) arranged over the third transparent conductive layer (CTCO) to fill the interior of the opening (as annotated on Fig. 4); and
a metal layer (CMTL; common auxiliary electrode; Fig. 4; [0053]) in contact with the third transparent conductive layer (CTCO) and the filling member (SP through intervening layer CTCO).
Regarding claim 6, Ozeki discloses, the display device according to claim 5, wherein the transistor (TR1) has an oxide semiconductor layer (OS1), a gate wiring (GL1) opposite the oxide semiconductor layer (OS1), and a gate insulating layer (GI1) between the oxide semiconductor layer (OS1) and the gate wiring (GL1), and the gate wiring (GL1) extending along the first direction (D1) overlapping on the opening (Figs. 4 and 5; [0047] – [0049]).
Regarding claim 7, Ozeki discloses, the display device according to claim 6, further comprising: a light-shielding layer (LS1/LS2; Fig. 4; [0055]) between the first substrate (300) and the oxide semiconductor layer (OS1), wherein the light-shielding layer (LS1/LS2) extends along the first direction (D1) so as to overlap the opening (as annotated on Fig. 4).
Regarding claim 8, Ozeki discloses, the display device according to claim 5, wherein the filling member (SP) has a protrusion portion protruding above a top surface of the second transparent conductive layer (PTCO) arranged above the first insulating layer (IL4).
Allowable Subject Matter
Claims 4 and 9 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims.
Regarding claim 4, the closest prior art, US 2022/0308378 A1 (Ozeki), in combination with, fails to disclose, “the display device according to claim 3, wherein the third transparent conductive layer and the metal layer are arranged on the protruding portion”, in combination with the additionally claimed features, as are claimed by the Applicant.
Regarding claim 9, the closest prior art, US 2022/0308378 A1 (Ozeki), in combination with, fails to disclose, “the display device according to claim 8, wherein the metal layer is arranged above the protruding portion”, in combination with the additionally claimed features, as are claimed by the Applicant.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 11,774,819 B2 (Miyamoto) - An active matrix substrate is disclosed including, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.
US 2019/0346711 A1 (Yeh) - A thin film transistor and touch signal lines are disposed on a substrate. A first insulating layer, a first transparent conductive layer and a second insulating layer are disposed on the thin film transistor and the touch signal lines in sequence, wherein the first transparent conductive layer includes pixel electrodes. First connecting holes and second connecting holes are situated in the first insulating layer and the second insulating layer, each first connecting hole exposes a portion of the pixel electrode and a portion of the drain, and each second connecting hole exposes a portion of the touch signal line. A second transparent conductive layer is disposed on the second insulating layer, and includes touch electrodes and connecting electrodes electrically insulated from each other and respectively extending into the first connecting holes and the second connecting holes.
US 2019/0056620 A1 (Akiyoshi) - A liquid crystal display device is disclosed comprising: scanning lines extending in a first direction, video signal lines extending in a second direction, a pixel electrode formed in an area surrounded by the scanning lines and the video signal lines; a transistor connected to the pixel electrode, a first insulating film formed on a source electrode of the transistor, a common electrode formed on the first insulating film, a second insulating film on the common electrode, the pixel electrode is formed on the second insulating film; wherein a first through hole is formed in the first insulating film, the pixel electrode connects with the source electrode via the first through hole, a common metal wiring made of metal is formed overlapping with a part of the common electrode, black resin exists in the first through hole, the black resin is formed overlapping with the video signal line in a plan view.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
11/04/2025