Prosecution Insights
Last updated: July 17, 2026
Application No. 18/244,326

LAYOUT METHOD, NON-TRANSITORY COMPUTER-READABLE MEDIUM, AND ASSOCIATED INTEGRATED CIRCUIT

Non-Final OA §101§112
Filed
Sep 11, 2023
Priority
Mar 01, 2023 — TW 112107302
Examiner
DOAN, NGHIA M
Art Unit
Tech Center
Assignee
Faraday Technology Corporation
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
887 granted / 1019 resolved
+27.0% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
20 currently pending
Career history
1032
Total Applications
across all art units

Statute-Specific Performance

§101
6.8%
-33.2% vs TC avg
§103
50.2%
+10.2% vs TC avg
§102
30.9%
-9.1% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1019 resolved cases

Office Action

§101 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is response to Application 18/244326 filed on 09/11/2023. Claims 1-20 are pending the office action. Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. TW112107302, filed on 03/01/2023. Information Disclosure Statement The information disclosure statement filed 11/13/2023 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 19 is rejected under 35 U.S.C. 101 because the claimed invention is not supported by either a specific and substantial asserted utility or a well-established utility. The claim recited “A computer-readable medium” is generally considered a composition of matter if it is a tangible, physical substrate (e.g., a disk, tape, or memory chip) that can store data. However, if the medium is without a processor and is merely a passive storage device, it may not meet the “machine” category because it lacks the functional integration of parts that define a machine. Also notice that the Application’s specification does not describe/include such as a computer system, processor, CPU, or any other means that is integrated with the passive storage medium which may not qualify as a machine. The claim 19 also does not fall in other categories: composition of matter or manufacture because there is no tangible or physical objection, nor as process category because the method (data) contained in the passive storage medium may not execute. Claim 19 is also rejected under 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph. Specifically, because the claimed invention is not supported by either a specific and substantial asserted utility or a well-established utility for the reasons set forth above, one skilled in the art clearly would not know how to use the claimed invention. Allowable Subject Matter Claims 1-18 and 20 are allowed. The following is an examiner’s statement of reasons for allowance: the prior art of record does not teach the limitation of claims 1 and 20, a layout method used with an integrated circuit comprising Q circuit blocks, wherein the layout method comprises steps of: placing K gate-controlled elements and (K-1) buffers on an edge of a qth circuit block among the Q circuit blocks, wherein each of the K gate-controlled elements comprises a first terminal, a second terminal, and a control terminal, and each of the (K-1) buffers comprises an input terminal and an output terminal; connecting the first terminals of the K gate-controlled elements to a supply voltage terminal; connecting the second terminals of the K gate-controlled elements to the qth circuit block; selecting, among the K gate-controlled elements, (K-1) gate-controlled elements comprising an SEL[1]-th gate-controlled element as (K-1) source nodes, wherein the control terminal of the SEL[1]-th gate-controlled element receives a qth enabling signal corresponding to the qth circuit block; selecting, among the K gate-controlled elements, another (K-1) gate-controlled elements other than the SEL[1]-th gate-controlled element as (K-1) destination nodes; and routing the (K-1) buffers as (K-1) delayed gating lines connected between the (K-1) source nodes and the (K-1) destination nodes, respectively, wherein Q, q, K, and SEL[1] are positive integers, SEL[1] is smaller than K, and q is smaller than or equivalent to Q. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NGHIA M DOAN whose telephone number is (571)272-5973. The examiner can normally be reached Mon - Fri 7:00 AM - 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. NGHIA M. DOAN Primary Examiner Art Unit 2851 /NGHIA M DOAN/ Primary Examiner, Art Unit 2851
Read full office action

Prosecution Timeline

Sep 11, 2023
Application Filed
Jun 15, 2026
Non-Final Rejection mailed — §101, §112 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+17.2%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1019 resolved cases by this examiner. Grant probability derived from career allowance rate.

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