Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Elections/Restrictions
Applicant’s election without traverse of Species A (Claims 1, 8, 10-20 and 23) in the reply filed on 03/10/2026 is acknowledged. However, claims 8, 12 and 18-19 in applicant’s election correspond to a non-elected species.
Specifically, claim 8, lines 5-6: “based on a lower surface of the substrate, an upper surface of the transparent layer is positioned under an upper surface of the first mask layer” is drawn to at least Figures 34-45 of the non-elected species whereas elected Figures 1-12 do not illustrate such feature. For instance, Figures 5-10 require the upper surface of the transparent layer to be coplanar with upper surface of the mask.
Claim 12, line 3: “forming a protective film covering the transparent layer” is drawn to at least Figures 26 or 29 of the non-elected species whereas elected Figures 1-12 do not illustrate such feature. For instance, Figure 12 requires the transparent layer to be removed before the deposition of the protective film.
Claim 18, line 2 and 5: “a lower surface of the transparent layer is in contact with the first mask layer…a second portion under the transparent layer” is drawn to at least Figures 21-32 of the non-elected species whereas elected Figures 1-12 do not illustrate such feature. For instance, Figures 5-10 do not include a lower portion of the first mask under the transparent layer.
Claim 19 requires all limitation of claim 18.
Therefore, claims 8, 12 and 18-19 are withdrawn from consideration for being drawn to the non-elected species.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) based upon an application filed in KOREA on 10/11/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/11/2023is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5-7, 10-11, 13, 15-17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20150079791A1; Park et al.; (hereinafter “Park”).
Regarding Claim 1, Park teaches a method for manufacturing a semiconductor device ([0008]), comprising:
forming a step key (#104, Figure 2B) on a substrate (#100);
forming a mold layer (#121) on the step key covering the step key (#104);
forming a first mask layer (#116) on the mold layer (#121),
forming a transparent layer (#120) in the first mask layer (#116) overlapping the step key (#104);
forming a second mask layer (#122, Figure 3B) on the first mask layer (#116) and the transparent layer (#120);
etching the mold layer (#121, Figure 4B-5B) using the second mask layer (#122),
wherein the first mask layer (#116) includes a metal material ([0045]).
Regarding Claim 5, Park teaches the method for manufacturing a semiconductor device as described in claim 1, wherein Park further teaches forming the transparent layer (#120, Figure 2B) includes:
forming a key-hole (#118) extending through the first mask layer (#116) and overlapping with the step key (#104), and
forming the transparent layer (#120, Figure 3B) in the key-hole (#104).
Regarding Claim 6, Park teaches the method for manufacturing a semiconductor device as described in claim 5, wherein Park further teaches a first width of the key-hole (#118, Figure 2B) is greater than a second width of the step key (#104).
Regarding Claim 7, Park teaches the method for manufacturing a semiconductor device as described in claim 5, wherein Park further teaches:
forming the transparent layer (#120, Figure 3B) in the key-hole (#104) includes forming the transparent layer using chemical vapor deposition, physical vapor deposition, or atomic layer deposition ([0044]), and
an upper surface of the transparent layer (#120) and an upper surface of the first mask layer (#116) are coplanar with each other ([0050]).
Regarding Claim 10, Park teaches the method for manufacturing a semiconductor device as described in claim 1, wherein Park further teaches the mold layer (#121, Figure 2B) includes:
a flat surface area non-overlapping with the step key (#121 comprises such as flat top surface non-overlapping key #104); and
a curved surface area (#118b) overlapping with the step key (#104).
Regarding Claim 11, Park teaches the method for manufacturing a semiconductor device as described in claim 1, wherein Park further teaches the mold layer (#121) includes:
a first mold layer including silicon nitride (#106, [0044]); and
a second mold layer including silicon oxide (#108/#112, [0044]).
Regarding Claim 13, Park teaches the method for manufacturing a semiconductor device as described in claim 1, wherein Park further teaches a light transmittance of the transparent layer is greater than a light transmittance of the first mask layer ([0049], patterns #120 has higher optical transmittance than mask #116).
Regarding Claim 15, Park teaches a method for manufacturing a semiconductor device ([0008]), comprising:
forming a substrate (#100, Figure 2B) including a chip area (#CR) and an out-of-chip area (#PR);
forming a step key (#104) on the out-of-chip area (#PR) of the substrate;
forming a mold layer (#121) on the substrate (#100) covering the step key (#104);
forming a first mask layer (#116) on the mold layer (#121),
forming a key-hole (#118) in the first mask layer (#116) overlapping the step key (#104);
forming a transparent layer (#120, Figure 3B) in the key-hole (#118);
forming a second mask layer (#122) on the first mask layer (#116) and the transparent layer (#120) while aligning the second mask layer using the step key ([0055]);
etching the mold layer (#121, Figure 4B-5B) using the second mask layer (#122) to form a pattern hole (#132); and
filling the pattern hole with a pattern material (Figure 7B-8B) to form a pillar structure (#140).
Regarding Claim 16, Park teaches the method for manufacturing a semiconductor device as described in claim 15, wherein Park further teaches the first mask layer includes a metal material ([0045], mask #116 comprises metal).
Regarding Claim 17, Park teaches the method for manufacturing a semiconductor device as described in claim 15, wherein Park further teaches the key-hole (#118, Figure 3B) extends through the first mask layer (#116), and a lower surface of the transparent layer (#120) is in contact with the mold layer (#114/#121).
Regarding Claim 20, Park teaches the method for manufacturing a semiconductor device as described in claim 15, wherein Park further teaches:
forming the pattern hole (#132, Figures 4B-5B) includes etching the first mask layer (#116) and the mold layer (#121),
forming the pillar structure includes removing the second mask layer (#122, Figures 4B-5B) and forming the pillar structure (#136/#140, Figures 7B-8B) in the pattern hole (#132), and
based on a lower surface of the substrate (#100), an upper surface of the pillar structure is positioned at a higher vertical level than a vertical level of a lower surface of the first mask layer (Figure 7B, upper surface of conductive layer #136 is at a higher level than mask #128, Figure 6B).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of US20100309470A1; Liu et al.; (hereinafter “Liu”).
Regarding Claim 14, Park teaches the method for manufacturing a semiconductor device as described in claim 1.
Park does not explicitly teach the transparent layer includes hafnium oxide, titanium oxide, tantalum oxide, silicon oxide, or silicon nitride.
However, Liu teaches a semiconductor device ([0004]), comprising a transparent layer (Figure 3, stripe #18 material formed in layer #21) includes hafnium oxide, titanium oxide, tantalum oxide, silicon oxide, or silicon nitride (#18 comprises silicon nitride).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Park with the teaching of Liu, as it would be a simple substitution of one known element (layer material of Park) for another (layer material of Liu) in comparable structures to obtain predictable results. See MPEP 2143(I)(B).
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Park in view of US20210098260A1; Yoon et al.; (hereinafter “Yoon”).
Regarding Claim 23, Park teaches a method for manufacturing a semiconductor device ([0008]), comprising:
forming a substrate (#100, Figure 2B) including a chip area (#CR) and an out-of-chip area (#PR);
forming a bit line on the substrate and in the chip area extending across the substrate ([0040], bit lines form in cell region of the substrate);
forming a buried contact connected to the chip area of the substrate ([0040], contact plugs form in cell region of the substrate);
forming a step key (#104) on the substrate (#100) and in the out-of-chip area (#PR);
forming a mold layer (#121) on the chip area (#CR) and the out-of-chip area (#PR) covering the step key (#104);
forming a first mask layer (#116) on the mold layer (#121), wherein the first mask layer includes a metal material ([0045], mask #116 comprises metal);
forming a key-hole (#118) in the first mask layer (#116) overlapping the step key (#104);
forming a transparent layer (#120, Figure 3B) in the key-hole (#118);
forming a second mask layer (#122) on the first mask layer (#116) and the transparent layer (#120) while aligning the second mask layer using the step key ([0055]);
etching the mold layer (#121, Figures 4B-5B) in the chip area (#CR) using the second mask layer (#122) to form a pattern hole (#132);
forming a lower electrode (#140, Figures 7B-8B) filling the pattern hole (#132); and
forming a dielectric film (#148, Figure 11B) and an upper electrode (#150) on the lower electrode (#140),
wherein:
a light transmittance of the transparent layer is greater than a light transmittance of the first mask layer ([0049], optical transmittance of pattern #120 is higher than mask #116), and
a first vertical level of an upper surface of the lower electrode extends farther in a vertical direction relative to a bottom surface of the substrate than a second vertical level of an upper surface of the mold layer (Figure 8B, upper surface of electrode #140 is higher than an upper surface of layer #112/#108).
Park does not explicitly teach forming the buried contact between the bit lines; forming a landing pad on the buried contact.
However, Yoon teaches a method for manufacturing a semiconductor device ([0005]), comprising forming a buried contact (#256, Figure 9E, conductive plugs) between bit lines (#BL, bit lines); forming a landing pad (#LP, landing pads) on the buried contact (#256).
It would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to modify the invention disclosed by Park with the teaching of Yoon by known methods to yield predictable results (implementation of buried contacts and landing pads in lower structure of cell region of the substrate, see also [0039-0040] of Park). See MPEP 2143(I)(A).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US202120061732A1 – Figure 6-17
US20070018341A1 – Figures 2A-E
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/TIEN TRAN/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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