DETAILED ACTION Election /Restrictions Applicant’s election without traverse of claims 1-15 in the reply filed on 02/19/2026 is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/02/2024, 09/11/2023 were filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim objection Claim 13 should be amended to include “second” to the third line, so it will be read as: …- and the second input/output pads. --- Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claim s 1- 3 , 7 , 9 -1 4 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Jeon et al., U.S. Pub. No. 2016/0117110. Regarding claim 1 , Jeon discloses a nonvolatile memory package comprising (See Figure 2) : f irst nonvolatile memory devices configured to be stacked (NVM0-NVM3, Fig. 2), second nonvolatile memory devices configured to be stacked (NVM4-NVM7, Fig. 2), and an interface chip connected to an external device through a bonding channel (Fig. 2, 11) , connected to one of the first nonvolatile memory devices through a first bonding channel, and connected to one of the second nonvolatile memory devices through a second bonding channel (see below) , wherein the interface chip 110 includes: input/output pads 111 connected to the bonding channel 110 , first input/output pads 113 connected to the first bonding channel 121 , and second input/output pads 114 connected to the second bonding channel 122 , wherein the first input/output pads and the second input/output pads are alternately arranged by channel for cross-channel shielding ( first I/O pads arranged by channel 113 and the second I/O arrange by channel 114, Fig. 2). Regarding claim 2, Jeon discloses wherein the first input/output pads 113 and second input/output pads 114 are arranged in a single row or in a zigzag pattern (Figs. 2-3). Regarding claim 3, Jeon discloses wherein each of the first nonvolatile memory devices (NVM0-NVM3) includes first signal pads connected to each other 1 21 , first ground pads connected to each other, and first power pads connected to each other, and wherein each of the second nonvolatile memory devices includes second signal pads connected to each other 1 22 , second ground pads connected to each other, and second power pads connected to each other (Figs . 5, 7-8; [0063], [0069]-[0070] ). Regarding claim 7, Jeon discloses wherein the input/output pads are arranged in a row (Fig. 2). Regarding claim 9, Jeon discloses wherein the first bonding channel is connected to a lowermost or topmost nonvolatile memory device among the first nonvolatile memory devices (Fig. 2). Regarding claim 10, Jeon discloses wherein the second bonding channel is connected to a lowermost or topmost nonvolatile memory device among the second nonvolatile memory devices (Fig. 2). Regarding claim 11 , Jeon discloses a nonvolatile memory package comprising (See Figure 2): A nonvolatile memory package 100 (Figs. 1-2) and a controller 200 (Fig. 1) connected to the nonvolatile memory package through a channel and configured to control the nonvolatile memory package 100, wherein the nonvolatile memory package includes: first nonvolatile memory devices configured to be stacked (NVM0-NVM3, Fig. 2), second nonvolatile memory devices configured to be stacked (NVM4-NVM7, Fig. 2), and an interface chip connected to the first internal channel 121 and the second internal channel 122, wherein the interface chip 110 includes: input/output pads 111 connected to the bonding channel 110, first input/output pads 113 connected to the first bonding channel 121, and second input/output pads 114 connected to the second bonding channel 122, wherein the first input/output pads and the second input/output pads are alternately arranged by channel for cross-channel shielding (first I/O pads arranged by channel 113 and the second I/O arrange by channel 114, Fig. 2). Regarding claim 12, Jeon discloses wherein the first I/O and the second I/O pads are arranged in a second row and wherein each of the first nonvolatile memory devices and the second nonvolatile memory devices are configured to be stacked (Fig. 2). Regarding claim 13, it is inherent that wherein during a read operation or a write operation, the I/O pads are electrically connected to one of the first I/O pads and the second I/O pads. Regarding claim 14, it is inherent that the first and second memory devices include power pads connected to each other or ground pads connected to each other in order to keep voltage stable across the chip, increase yield, reduce ground bounce and noise, keep signals accurate , and improve reliability, and it is inherent that wherein the power pads and the ground pads are connected to the controller 200 through bonding pads in order connect to outside/external device . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 4 - 6 , 8 , 15 are rejected under 35 U.S.C. 103 as being unpatentable over Jeon et al., U.S. Pub. No. 2016/0117110. Regarding claim s 4 -5 , Jeon fails to disclose wherein one of the first ground pads and the first power pads is alternately arranged between the first signal pads, and wherein one of the second ground pads and the second power pads is alternately arranged between the second signal pads, and wherein first ground pad connects to second ground pad and first power pad connects to second power pad . Jeon is silent as to any specific positional relationship between ground pads, power pads, and signal pads, and thus does not teach the claimed alternating configuration. The particular arrangement of ground pads and power pads whether alternating or not, would have been obvious to one having ordinary skill in the art as a matter of design choice. It is well known that pad layouts may be modified based on routine considerations and manufacturing preferences. In the absence of claimed alternating arrangement, the limitations of claims do not distinguish over the prior art. Rather, it constitutes a predictable variation within the level of ordinary skill in the art and is therefore unpatentable under 35 U.S.C 103. Regarding claim 6, Jeon discloses wherein the first ground pad and the first power pad are connected to bonding pads connected to the external device (Figs. 2-3). Regarding claim 8, Jeon is silent as to whether when one bonding channel is activated the other is inactivated. The reference does not expressly disclose or describe any such mutually exclusive activation scheme. However, the it would have been obvious to one having ordinary skill in the art at the time the invention was made that it is well known in the art that selectively activating one channel while deactivating the other represents a conventional control strategy used to prevent signal interference, reduce power consumption, and simplify circuit operation. Implementing such mutual exclusivity would have been a predictable variation and within the routine skill of a person having ordinary skill in the art and does not render the claims patentable under 35 U.S.C 103. Regarding claim 15, Jeon fails to disclose wherein the first nonvolatile memory devices and the second nonvolatile memory devices are alternately arranged horizontally with a predetermined distance therebetween. However, alternating arrangement of the first and second nonvolatile memory devices could have been a routine layout choice that would have been obvious to one having ordinary skill in the art at the time of the invention. It is well known that alternating arrangement is commonly used and routine layout in order to achieve balanced power distribution, improve routing and thermal uniformity, thus, it’s obvious and unpatentable. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT THAO P LE whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1785 . The examiner can normally be reached on Monday-Friday 9AM-6PM FILLIN "Work schedule?" \* MERGEFORMAT . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272- 2266 . The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). /THAO P LE/ Primary Examiner, Art Unit 2818