DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Species I (FIG. 1), encompassing claims 1-3 and 9-10, in the reply filed on 1/23/2026 is acknowledged.
Claims 4-8 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/23/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 9-10 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 reciting “one or a plurality of first via wirings …; and one or a plurality of second via wirings …; wherein a first inductance between the one of the pair of first source electrodes and the metal layer via the one or plurality of first via wirings is larger than a second inductance between the one of the pair of second source electrodes and the metal layer via the one or plurality of second via wirings” lacks adequate written description. Applicant’s specification describes a combination of plural first via wirings 28a and plural second via wirings 28b as shown in FIGs. 1 and 9-13, and a combination of one first via wiring 28a and plural second via wirings 28b as shown in FIG. 14. However, there is no disclosure to a combination of one first via wiring and one second via wiring, nor disclosure to a combination of plural first via wirings and one second via wiring. Furthermore, there is no disclosure of the claimed inductance values for these undisclosed combinations. Therefore, Applicant’s disclosure fails to provide written description for the entirety of claimed invention.
Claim 9 reciting “wherein when the one or plurality of first via wirings is a single first via wiring, the first inductance is a self-inductance of the single first via wiring, when the one or plurality of first via wirings is a plurality of first via wirings, the first inductance is a sum of an inductance obtained by combining self-inductances of the plurality of first via wirings and a mutual inductance between the plurality of first via wirings, when the one or plurality of second via wirings is a single second via wiring, the second inductance is a self-inductance of the single second via wiring, and when the one or plurality of second via wirings is a plurality of second via wirings, the second inductance is a sum of an inductance obtained by combining self-inductances of the plurality of second via wirings and a mutual inductance between the plurality of second via wirings” lacks adequate written description. Applicant’s disclosures does not specifically describe an embodiment having a single second via wiring. Nor does the disclosure provide description for the inductance of a single second via wiring as compared to one or more of the first via wirings or the first source electrodes or the metal layer.
Other claims are rejected for depending on a rejected claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 9-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “a first inductance between the one of the pair of first source electrodes and the metal layer via the one or plurality of first via wirings is larger than a second inductance between the one of the pair of second source electrodes and the metal layer via the one or plurality of second via wirings” renders the claim indefinite. It is unclear what constitutes an inductance “between the one of the pair of first/second source electrodes and the metal layer via the one or plurality of first/second via wirings”. Is the inductance referring to the total inductance associated with the first/second source electrode, the metal layer, and the first/second via wirings? Or is the inductance associated with the first/second via wirings only? Or is the inductance measured for some other parts or combination of the first/second source electrode, the metal layer, and the first/second via wirings? Applicant’s invention, as best understood, is aimed at ensuring the inductance is equal among the source electrodes. It is unclear what the claimed first/second inductance is intended to be measurement of and how do the difference of inductance achieved the disclosed uniformity across the device. Furthermore, the correspondence between “the one or plurality of first via wirings” and “the one or plurality of second via wirings” is indefinite. More specifically, Applicant’s specification describes a combination of plural first via wirings 28a and plural second via wirings 28b as shown in FIGs. 1 and 9-13, and a combination of one first via wiring 28a and plural second via wirings 28b as shown in FIG. 14. However, there is no disclosure to a combination of one first via wiring and one second via wiring, nor disclosure to a combination of plural first via wirings and one second via wiring. There is a lack of specificity on how the inductance characteristic remain true for these undisclosed combinations encompassed by the claim.
Claim 1 reciting “the pair of first source electrodes being closest to ends of the plurality of source electrodes” and “the pair of second source electrodes being second closest to the ends of the plurality of source electrodes” render the claim indefinite. It is unclear what constitutes “ends of the plurality of source electrodes”. Does “end” refer to an ending face, an ending one of the source electrode or some arbitrary demarcation? If the “end” is referring to the last outermost one of the source electrode, what constitutes a source electrode that is “closest”? In this case, is the closest source electrode the same as the last source electrode or is it referring to the next closest source electrode? Furthermore, are the pair of the source electrodes closest to the same end? Or are the pair of source electrodes closest to respective different ends?
Claim 9 reciting “wherein when the one or plurality of first via wirings is a single first via wiring, the first inductance is a self-inductance of the single first via wiring, when the one or plurality of first via wirings is a plurality of first via wirings, the first inductance is a sum of an inductance obtained by combining self-inductances of the plurality of first via wirings and a mutual inductance between the plurality of first via wirings, when the one or plurality of second via wirings is a single second via wiring, the second inductance is a self-inductance of the single second via wiring, and when the one or plurality of second via wirings is a plurality of second via wirings, the second inductance is a sum of an inductance obtained by combining self-inductances of the plurality of second via wirings and a mutual inductance between the plurality of second via wirings” renders the claim indefinite.
In the instance “when the one or plurality of first via wirings is a single first via wiring, the first inductance is a self-inductance of the single first via wiring”, it is unclear how is the first inductance larger than the second inductance but also achieve uniform inductance across the device as described to be the inventive concept.
In the instance “when the one or plurality of second via wirings is a single second via wiring, the second inductance is a self-inductance of the single second via wiring”, it is unclear how is the first inductance larger than the second inductance. Applicant’s disclosure does not describe an embodiment having only a single second via wiring. It is also unclear how inductance characteristics as claimed or disclosed are obtained for such embodiment.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. CN 111354640 A (Yin).
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In re claim 1, as best understood, Yin discloses (e.g. FIGs. 2 & 5) a semiconductor device comprising:
a substrate 10,20;
a metal layer 60 provided under the substrate 10,20;
a plurality of source electrodes 31 provided on the substrate and including a pair of first source electrodes 311 (two first source electrodes 311 at respective edges of region a, ¶ 40) and a pair of second source electrodes 312 (plural second source electrodes 312 between two first source electrodes 311, ¶ 40), “the pair of first source electrodes 311 being closest to ends of the plurality of source electrodes 31” (as best understood, first source electrodes 311 being the last source electrodes in region a are considered closest to ends) arranged in a direction in which the plurality of source electrodes 31 are arranged, “the pair of second source electrodes 312 being second closest to the ends of the plurality of source electrodes 31” (as best understood, second source electrodes 312 are further inside region a than first source electrodes 311);
one or a plurality of first via wirings 50 (in holes 41) that overlap with one of the pair of first source electrodes 311 in a plan view (see FIG. 5), penetrate through the substrate 10,20, and electrically connect the metal layer 60 and the one of the pair of first source electrodes 311; and
one or a plurality of second via wirings 50 (in holes 42) that overlap with one of the pair of second source electrodes 312 in the plan view (see FIG. 5), penetrate through the substrate 10,20, and electrically connect the metal layer 60 and the one of the pair of second source electrodes 312;
“wherein a first inductance between the one of the pair of first source electrodes 311 and the metal layer 60 via the one or plurality of first via wirings 50 (in holes 41) is larger than a second inductance between the one of the pair of second source electrodes 312 and the metal layer 60 via the one or plurality of second via wirings 50 (in holes 42) (as best understood, see FIG. 5, ¶ 58).
In re claim 2, Yin discloses (e.g. FIGs. 2 & 5) wherein
the one or plurality of first via wirings 50 (in holes 41) are a plurality of first via wirings (two holes 41 shown in FIG. 5),
the one or plurality of second via wirings 50 (in holes 42) are a plurality of second via wirings (two holes 42 shown in FIG. 5), and
a first interval L3 between the plurality of first via wirings 41 adjacent to each other is smaller than a second interval L4 between the plurality of second via wirings 42 adjacent to each other (¶ 58).
In re claim 3, Yin discloses (e.g. FIGs. 2 & 5) wherein
a number of the plurality of first via wirings 50 (in two holes 41) is equal to or less than a number of the plurality of second via wirings 50 (in two holes 42), and
a first area in a plan view (see FIG. 5) in which each of the plurality of first via wirings 41 is in contact with one of the pair of first source electrodes 311 is equal to or less than a second area in the plan view in which each of the plurality of second via wirings 42 is in contact with one of the pair of second source electrodes 312.
In re claim 9, as best understood, Yin discloses (e.g. FIG. 5) wherein
when the one or plurality of first via wirings is a plurality of first via wirings (two holes 41), the first inductance is a sum of an inductance obtained by combining self-inductances of the plurality of first via wirings 41 and a mutual inductance between the plurality of first via wirings 41 (¶ 58),
when the one or plurality of second via wirings is a plurality of second via wirings (two holes 42), the second inductance is a sum of an inductance obtained by combining self-inductances of the plurality of second via wirings 42 and a mutual inductance between the plurality of second via wirings 42.
In re claim 10, Yin discloses (FIG. 5) further comprising:
a plurality of gate electrodes 32 provided on the substrate; and
a plurality of drain electrodes 33 provided on the substrate;
wherein each of the plurality of gate electrodes 32 is sandwiched between one of the plurality of source electrodes 31 and one of the plurality of drain electrodes 33.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights