DETAILED ACTION
This office action is in response to amendment filed 6/22/2026.
Claims 1-8 and 10-13 are pending. Claim 9 has been canceled. Claims 11-13 are new. Claims 4-8 have been withdrawn. Claim 1 has been amended.
Claim Objections
Claims 4-8 are objected to because of the following informalities:
Amendments to the claims filed on or after July 30, 2003 must comply with 37 CFR 1.121(c) which states:
(c) Claims. Amendments to a claim must be made by rewriting the entire claim with all changes (e.g., additions and deletions) as indicated in this subsection, except when the claim is being canceled. Each amendment document that includes a change to an existing claim, cancellation of an existing claim or addition of a new claim, must include a complete listing of all claims ever presented, including the text of all pending and withdrawn claims, in the application. The claim listing, including the text of the claims, in the amendment document will serve to replace all prior versions of the claims, in the application. In the claim listing, the status of every claim must be indicated after its claim number by using one of the following identifiers in a parenthetical expression: (Original), (Currently amended), (Canceled), (Withdrawn), (Previously presented), (New), and (Not entered).
Claims 4-8 were previously withdrawn due to restriction requirement. These claims should be identified as withdrawn as their proper status.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-3 and 9-13 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 reciting “one or a plurality of first via wirings …; and one or a plurality of second via wirings …; wherein a first inductance between the one of the pair of first source electrodes and the metal layer via the one or plurality of first via wirings is larger than a second inductance between the one of the pair of second source electrodes and the metal layer via the one or plurality of second via wirings” lacks adequate written description. Applicant’s specification describes a combination of plural first via wirings 28a and plural second via wirings 28b as shown in FIGs. 1 and 9-13, and a combination of one first via wiring 28a and plural second via wirings 28b as shown in FIG. 14. However, there is no disclosure to a combination of one first via wiring and one second via wiring, nor disclosure to a combination of plural first via wirings and one second via wiring. Furthermore, there is no disclosure of the claimed inductance values for these undisclosed combinations. Therefore, Applicant’s disclosure fails to provide written description for the entirety of claimed invention.
Claim 11 reciting “wherein the first inductance is a self-inductance of a single first via wiring and the second inductance is a self-inductance of a single second via wiring” lacks adequate written description. Applicant’s disclosures does not specifically describe an embodiment having a single first via wiring in combination with a single second via wiring. Nor does the disclosure provide description for the inductance of a single second via wiring as compared to a single first via wiring. Even if there is support for the claimed combination, such embodiment would not pertain to the elected Species I as shown in FIG. 1 specifically directed to a device embodiment having two first via wirings 28a and two second via wirings 28b.
Other claims are rejected for depending on a rejected claim.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-3 and 9-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 containing mixed recitations to “one or a plurality of first via wirings” and "one or a plurality of second via wirings” with “the plurality of first via wirings” and “the plurality of second via wirings” render the claim indefinite due to improper antecedent basis. The inconsistent recitations throughout the claim makes it unclear if the claim in fact requires a plurality of first/second via wirings. It is unclear whether the intended scope of the claim is “one or more” first/second via wirings or a “plurality” of first/second via wirings.
Claim 1 reciting “a first inductance between the one of the pair of first source electrodes and the metal layer via the one or plurality of first via wirings is larger than a second inductance between the one of the pair of second source electrodes and the metal layer via the one or plurality of second via wirings” and “the first inductance is 1.05 times or more of the second inductance” renders the claim indefinite” renders the claim indefinite. It is unclear what constitutes an inductance “between the one of the pair of first/second source electrodes and the metal layer via the one or plurality of first/second via wirings”. Is the inductance referring to the total inductance associated with the first/second source electrode, the metal layer, and the first/second via wirings? Or is the inductance associated with the first/second via wirings only? Or is the inductance measured for some other parts or combination of the first/second source electrode, the metal layer, and the first/second via wirings? Applicant’s invention, as best understood, is aimed at ensuring the inductance is equal among the source electrodes. It is unclear what the claimed first/second inductance is intended to be a measurement of and how does the difference in inductance achieve the disclosed uniformity across the device. The claim also apparently sets a lower limit on the difference between first inductance and the second inductance to be 1.05 times or more, implying the difference can be infinitely large. Again, since the inventive concept pertains to achieving uniform inductance across the device, it is unclear what is intended by the “first inductance” and the “second inductance” as claimed, which can apparently be very different and appears to be against the concept of uniform inductance as disclosed.
Furthermore, the correspondence between “the one or plurality of first via wirings” and “the one or plurality of second via wirings” recited in claim 1 is indefinite. More specifically, Applicant’s specification describes a combination of plural first via wirings 28a and plural second via wirings 28b as shown in FIGs. 1 and 9-13, and a combination of one first via wiring 28a and plural second via wirings 28b as shown in FIG. 14. However, there is no disclosure to a combination of one first via wiring and one second via wiring, nor disclosure to a combination of plural first via wirings and one second via wiring. There is a lack of specificity on how the inductance characteristic remain true for these undisclosed combinations encompassed by the claim.
Claim 1 reciting “the pair of first source electrodes being closest to ends of the plurality of source electrodes” and “the pair of second source electrodes being second closest to the ends of the plurality of source electrodes” render the claim indefinite. It is unclear what constitutes “ends of the plurality of source electrodes”. Does “end” refer to an ending face, an ending one of the source electrode or some arbitrary demarcation? If the “end” is referring to the last outermost one of the source electrode, what constitutes a source electrode that is “closest”? In this case, is the closest source electrode the same as the last source electrode or is it referring to the next closest source electrode? Furthermore, are the pair of the source electrodes closest to the same end? Or are the pair of source electrodes closest to respective different ends?
Claim 2 reciting “a plurality of first via wirings” and “a plurality of second via wirings” render the claim indefinite. It is unclear if these are intended to be the same as “the plurality of first via wirings” and “the plurality of second via wirings” previously recited in claim 1. Furthermore, recitations to “a first interval” and “a second interval” are similarly indefinite because it is unclear if these are intended to be the same as the “first interval” and the “second interval” previously recited in claim 1.
Claim 3 reciting “a number of the plurality of first via wirings is equal to or less than a number of the plurality of second via wirings” render the claim indefinite for improperly broadening claim 1. Claim 1 previously recites the number of the plurality of first via wirings is equal to the number of the plurality of second via wirings. It is unclear how can it be further limited by reciting the number is “less than” in claim 3.
Claim 3 reciting “a first area in a plan view in which each of the plurality of first via wirings is in contact with one of the pair of first source electrodes is equal to or less than a second area in the plan view in which each of the plurality of second via wirings is in contact with one of the pair of second source electrodes” render the claim indefinite for improperly broadening claim 1. Claim 1 previously recites the first area is equal to the second area. It is unclear how can it be further limited by reciting the first area is “less than” in claim 3.
Claim 11 reciting “wherein the first inductance is a self-inductance of a single first via wiring and the second inductance is a self-inductance of a single second via wiring” renders the claim indefinite. Firstly, there is a lack of antecedent basis. It is unclear if “a single first via wiring” is referring to either the “one or a plurality of first via wirings” or “the plurality of first via wirings” previously recited in claim 1. Similarly, it is unclear if “a single second via wiring” is referring to either the “one or a plurality of second via wirings” or “the plurality of second via wirings” previously recited in claim 1. Furthermore, if both the first inductance and the second inductance are self-inductances of respective single first via wiring and single second via wiring, it is unclear how can the first inductance be larger than the second inductance. Applicant’s disclosure does not provide clear and unequivocal description to a device with a single first via wiring and a single second via wiring, such that the second self-inductance of the single second via wiring is larger than the first self-inductance of the single first via wiring. Furthermore, the inventive concept pertains to achieving uniform inductance across the device; it is further unclear how would having a second self-inductance of the single second via wiring that is larger than a first self-inductance of the single first via wiring achieve uniform inductance as intended by the disclosed invention.
Claim 12 reciting “wherein the first inductance is a sum of an inductance obtained by combining self-inductances of the plurality of first via wirings and a mutual inductance between the plurality of first via wirings” renders the claim indefinite. Claim 1 previously recite the first inductance to be “between the one or the pair of the first source electrodes and the metal layer via the one or plurality of first via wirings”. Claim 12 appearing to be redefining the first inductance. It is unclear how whether these inductances is intended to be the same or different. Furthermore, it is unclear how does the first inductance as defined in claim 12 is intended to further limit the scope what is recited in claim1. Furthermore, the inventive concept pertains to achieving uniform inductance across the device; it is further unclear how would setting a second inductance of the plural second via wirings to be larger than a first inductance of the plural first via wirings achieve uniform inductance as intended by the disclosed invention.
Claim 13 is indefinite for reasons similar to claim 12.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-3 and 9-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yin et al. CN 111354640 A (Yin).
PNG
media_image1.png
618
638
media_image1.png
Greyscale
In re claim 1, as best understood, Yin discloses (e.g. FIGs. 2 & 5) a semiconductor device comprising:
a substrate 10,20;
a metal layer 60 provided under the substrate 10,20;
a plurality of source electrodes 31 provided on the substrate and including a pair of first source electrodes 311 (two first source electrodes 311 at respective edges of region a, ¶ 40) and a pair of second source electrodes 312 (plural second source electrodes 312 between two first source electrodes 311, ¶ 40), “the pair of first source electrodes 311 being closest to ends of the plurality of source electrodes 31” (as best understood, first source electrodes 311 being the last source electrodes in region a are considered closest to ends) arranged in a direction in which the plurality of source electrodes 31 are arranged, “the pair of second source electrodes 312 being second closest to the ends of the plurality of source electrodes 31” (as best understood, second source electrodes 312 are further inside region a than first source electrodes 311);
one or a plurality of first via wirings 50 (in holes 41) that overlap with one of the pair of first source electrodes 311 in a plan view (see FIG. 5), penetrate through the substrate 10,20, and electrically connect the metal layer 60 and the one of the pair of first source electrodes 311; and
one or a plurality of second via wirings 50 (in holes 42) that overlap with one of the pair of second source electrodes 312 in the plan view (see FIG. 5), penetrate through the substrate 10,20, and electrically connect the metal layer 60 and the one of the pair of second source electrodes 312;
“wherein a first inductance between the one of the pair of first source electrodes 311 and the metal layer 60 via the one or plurality of first via wirings 50 (in holes 41) is larger than a second inductance between the one of the pair of second source electrodes 312 and the metal layer 60 via the one or plurality of second via wirings 50 (in holes 42) (as best understood, see FIG. 5, ¶ 58, larger mutual inductance between holes 41 due to smaller distance L3 than distance L4 between holes 42),
wherein a first interval L3 between the plurality of first via wirings 50 (in holes 41) adjacent to each other is smaller than a second interval L4 between the plurality of second via wirings 50 (in holes 42) adjacent to each other (see FIG. 5, ¶ 58),
wherein a number of the plurality of first via wirings 50 (in two holes 41 shown in FIG. 5) is equal to a number of the plurality of second via wirings 50 (in two holes 42 shown in FIG. 5) and a first area in a plan view in which each of the plurality of the first via wirings 50 (in holes 41) is in contact with one of the pair of the first source electrodes 311 is equal to a second area in the plain view in which each of the plurality of second via wirings 50 (in holes 42) is in contact with one of the pair of the second source electrodes 312 (see FIG. 5, same size holes 41 and 42, thus same contact area between the wirings 50 in holes 41,42 and source electrodes 311,312).
Yin teaches the distance L3 between holes 41 being less than the distance L4 between holes 42 results in greater mutual inductance between wirings in holes 41 than between wirings in holes 42, which is desirable to achieve same output signal among the different gates 32 and to improve output efficiency (¶ 58). Although Yin does not explicitly disclose the first mutual inductance of wirings in holes 41 is greater by a magnitude of 1.05 times or more compared to the second mutual inductance of wirings in holes 42, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the distances L3 and L4 to vary the mutual inductances between the wirings in holes 41 and 42 so as to obtain same output signal with the different gates 32 and the achieve desired output efficiency as disclosed by Yin. Forming Yin’s device with distances L3 and L4 such that the first mutual inductance between the wirings in holes 41 is 1.05 times or more than the second mutual inductance between wirings in holes 42 would have been obvious through routine optimization. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
In re claim 2, as best understood, Yin discloses (e.g. FIGs. 2 & 5) wherein
the one or plurality of first via wirings 50 (in holes 41) are “a plurality of first via wirings” (two holes 41 shown in FIG. 5),
the one or plurality of second via wirings 50 (in holes 42) are “a plurality of second via wirings” (two holes 42 shown in FIG. 5), and
“a first interval” L3 between the plurality of first via wirings 41 adjacent to each other is smaller than “a second interval” L4 between the plurality of second via wirings 42 adjacent to each other (¶ 58).
In re claim 3, as best understood, Yin discloses (e.g. FIGs. 2 & 5) wherein
a number of the plurality of first via wirings 50 (in two holes 41) “is equal to or less than” a number of the plurality of second via wirings 50 (in two holes 42), and
a first area in a plan view (see FIG. 5) in which each of the plurality of first via wirings 41 is in contact with one of the pair of first source electrodes 311 “is equal to or less than” a second area in the plan view in which each of the plurality of second via wirings 42 is in contact with one of the pair of second source electrodes 312.
In re claim 10, Yin discloses (FIG. 5) further comprising:
a plurality of gate electrodes 32 provided on the substrate; and
a plurality of drain electrodes 33 provided on the substrate;
wherein each of the plurality of gate electrodes 32 is sandwiched between one of the plurality of source electrodes 31 and one of the plurality of drain electrodes 33.
In re claim 11, as best understood, Yin discloses (e.g. FIG. 5) wherein the first inductance (as best understood, self-inductance of wiring 50 in one hole 41) is a self-inductance of a single first via wiring (i.e. of wiring in one hole 41 only) and the second inductance (as best understood, self-inductance of wiring 50 in one hole 42) is a self-inductance of a single second via wiring (i.e. of wiring in one hole 42 only).
In re claim 12, as best understood, Yin discloses (e.g. FIG. 5) wherein the first inductance is a sum of an inductance obtained by combining self-inductances of the plurality of first via wirings (self-inductance of wirings 50 in respective holes 41 shown in FIG. 5) and a mutual inductance between the plurality of first via wirings (mutual inductance between wirings 50 of adjacent holes 41 shown in FIG. 5) (¶ 58).
In re claim 13, as best understood, Yin discloses (e.g. FIG. 5) wherein the second inductance comprises a sum of an inductance obtained by combining self-inductances of the plurality of second via wirings (self-inductance of wirings 50 in respective holes 42 shown in FIG. 5) and a mutual inductance between the plurality of second via wirings (mutual inductance between wirings 50 of adjacent holes 42 shown in FIG. 5) (¶ 58).
Response to Arguments
Applicant's arguments filed 6/22/2026 have been fully considered but they are not persuasive.
Regarding § 112 rejections, Applicant argues claim amendments remedy the outstanding rejections (Remark, page 6-7).
This is not persuasive. Pending claims contains numerous § 112(a) and § 112(b) issues as detailed in the rejections above. More specifically, ¶ [0067] essentially repeats the claim language reciting “a first inductance between one of the source electrodes 12a and the metal layer 28 via one or the plurality of via wirings 28a is larger than a second inductance between one of the source electrodes 12b and the metal layer 28 via one or the plurality of via wirings 28b” in a summary statement. There is no clear and detailed description to a single second via wiring in combination with one or a plurality of first via wirings, such that the uniform inductance across the device is achieved as disclosed to be the intended inventive concept. The specification does not provide detail description comparing inductance value of a single second via wiring to inductance of one or a plurality of first via wirings, nor does it show how the uniform inductance is achieved by such combinations. Therefore, Applicant’s disclosure fails to provide written description for the entirety of claimed invention.
Applicant alleges ¶ 67-83 describes the difference in inductance (Remark, page 7).
This is not persuasive. There is a great amount of confusion among various disclosed inductances and claimed inductances. As best understood, Applicant’s invention sought to minimize the difference between the source inductances Lsa, Lsb and Lsc among the plural source electrodes. According to Applicant’s disclosure, as best understood, this is be achieved with higher mutual inductance between the first via wirings 28a relative to second via wirings 28b (¶ 54,56,62,66; FIG. 1, FIG. 9, FIG. 12, FIG. 14) and/or higher total self-inductance of the first via wirings 28a relative to second via wirings 28b (¶ 58,60,62,64,66; FIG. 10, FIG. 11, FIG. 12, FIG. 13, FIG. 14). Various ways of obtaining higher mutual inductance between the first via wirings 28a and/or higher total self-inductance of the first via wirings 28a are disclosed in various embodiments. However, the total inductance of the first source electrodes Lsa is intended to be same or similar as the total inductance of the second source electrode Lsb (¶ 54,56,58,60,62,64,66).
It is unclear what is intended by the claimed “first inductance” or the “second inductance”. Claim 1 recites “a first inductance between the one of the pair of first source electrodes and the metal layer via the one or plurality of first via wirings” and “a second inductance between the one of the pair of second source electrodes and the metal layer via the one or plurality of second via wirings”. They appear to be referring to overall inductances of source electrodes rather than the specific “mutual inductance” and “self-inductance” associated with the first via wirings or the second via wirings. But the overall inductances of the first source electrodes and the second source electrodes are understood to be the same or similar instead of being “larger than” and having a difference of “1.05 times or more” as claimed. Therefore, it remains unclear what is intended by the “first inductance” and the “second inductance” as claimed.
Regarding Yin, Applicant argues source electrodes 311 at the edges have few via holes than middle source electrodes 312 (Remark, page 7). This is not persuasive. The rejection is based on embodiment shown in FIG. 5 of Yin. Yin teaches in FIG. 5 two via holes 41 in edge source electrodes 311 separated by distance L3, two via holes 42 in middle source electrodes 312 separated by distance L4. Yin further discloses due to the smaller distance L3<L4, the mutual inductance between adjacent wiring holes 41 of edge source electrodes 311 is greater than mutual inductance between adjacent wiring holes 42 of middle source electrodes 312 (¶ 58).
Applicant further argues Yin teaches uniform inductance across all gate instead of different inductance (Remark, page 8).
This is not persuasive. As discussed in associated with the § 112 rejections above, Applicant’s invention also sought to achieve uniform inductance across the device. The difference exist in the mutual inductance between via wirings and/or total self-inductance of the via wirings depending on the location of the via wirings. The invention as disclosed is similar to Yin teaching setting a smaller distance L3 to increase the mutual inductance between adjacent wiring holes 41 at the edge so as to maintain uniform or same output. I.e. the overall inductance when considered in combination with mutual inductances between different source electrodes would be similar in Applicant’s invention and as disclosed by Yin.
Applicant further argues Yin fails to teach the number of first via wirings is equal to the number of second via wirings and the area of the first via wirings in contact with the first source electrode is equal to the area of the second via in contact with the second source electrode (Remark, page 8).
This is not persuasive. Yin teaches as shown in FIG. 5 two first via wirings 50 in two holes 41 and two second via wirings 50 in two holes 42. Therefore the numbers of the via wirings in holes 41 and 42 are the same. Furthermore, FIG. 5 teaches the holes 41 and 42 having a same size. Therefore, the contact area between the wirings 50 in holes 41 and first source electrodes 311 would be the same as the contact area between the wirings in holes 42 and second source electrodes 312.
Applicant further argues Yin fails to teach the “first inductance” is 1.05 times or more of the “second inductance”, as best understood (Remark, page 8).
This is not persuasive. Yin teaches the distance L3 between holes 41 being less than the distance L4 between holes 42 results in greater mutual inductance between wirings in holes 41 than between wirings in holes 42, which is desirable to achieve same output signal among the different gates 32 and to improve output efficiency (¶ 58). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the distances L3 and L4 to vary the mutual inductances between the wirings in holes 41 and 42 so as to obtain same output signal with the different gates 32 and the achieve desired output efficiency as disclosed by Yin. Forming Yin’s device with distances L3 and L4 such that the first mutual inductance between the wirings in holes 41 is 1.05 times or more than the second mutual inductance between wirings in holes 42 would have been obvious through routine optimization. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” See MPEP 2144.05 II. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); see also Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969). For more recent cases applying this principle, see Merck & Co. Inc. v. Biocraft Lab. Inc., 874 F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); Smith v. Nichols, 88 U.S. 112, 118-19 (1874); In re Williams, 36 F.2d 436, 438 (CCPA 1929). See also KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 416 (2007).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights