DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 32 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 32 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential structural cooperative relationships of elements, such omission amounting to a gap between the necessary structural connections. See MPEP § 2172.01. The omitted structural cooperative relationships are: “a metal material is different from the first seed layer and the under-bump pattern” in lines 5 and 6. It is unclear how “a metal material” is related to the rest of the structure. For the purpose of examination the examiner will assume that “a metal material refers to the under-bump pattern.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 22, 23, 24, 26, 27, 28, 29, 30, 31, and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0335441) in view of Chang (US 2020/0381348).
Regarding claim 22.
Kim teaches a method of manufacturing a semiconductor package comprising: forming a redistribution substrate (fig 2e[para 0026]); and placing a semiconductor chip (fig 2f:130[para 0037]) on the redistribution substrate (fig 2f:120[para 0037]), wherein forming the redistribution substrate includes: forming a first seed layer (fig 2b:111[para 0022]) on a carrier substrate (fig 2b:171[para 0021]); forming a first dielectric pattern (fig 2c:113[para 0024]) including a first opening on the first seed layer (fig 2c,2d:111[para 0024]); forming an under-bump pattern (fig 2b:112[para 0024]) within the first opening (fig 2c,d[para 0024.0025]);
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forming a second dielectric pattern (fig 2E:121a[para 0027]) including a second opening on the first dielectric pattern (fig 2E:113[para 0027]) and the under-bump pattern (fig 2e:112[para 0027]), the second opening exposing a top surface of the under-bump pattern (fig 2e:112[para 0028]); sequentially forming a second seed layer (fig2e:121b[para 0029]) and a conductive layer (fig 2e:121c[para 0031]) that fill the second opening and extend to a top surface of the second dielectric pattern (fig 2e:121a[para 0031]); and forming a redistribution pattern (fig 2e:121b,121c[para 0031]) by patterning the second seed layer (fig 2e:121b[para 0031]) and the conductive layer (fig 2e:121c[para 0031]), wherein the second opening overlaps the first opening in a vertical direction, wherein a bottom surface of the under- bump pattern (fig 2e:112[para 0028]) contact a top surface of the first seed layer (fig 2e:111[para 0024]), wherein a bottom surface of the second dielectric pattern (fig 2e:121a[para 0027]) contacts a top surface of the under-bump pattern (fig 2e:112[para 0027]), and wherein a width of the top surface of the under-bump pattern (fig 2e:112[para 0025]) is the same as a width of the first opening (fig 2e[para 0025]).
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Kim does not teach the bottom surface of the first dielectric pattern is in contact with the top surface of the first seed layer
Chang teaches wherein a bottom surface of the first dielectric pattern (fig 2b:20d1[para 0035]) and a bottom surface of the under- bump pattern (fig 2c:21[para 0036]) contact a top surface of the first seed layer (fig 2c:20s1[para 0036]), wherein the bottom surface of the first dielectric pattern (fig 2c:20d1[para 0036]) and the bottom surface of the under-bump pattern (fig 2c:21[para 0036]) are at the same vertical level (fig 2c[para 0036])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bottom surface of the dielectric layer to be inContact with the top surface of the first seed layer in order to enable the use of a damascene process to form the under bump pattern and thereby improve dimensional accuracy and reduce metal residue.
Regarding claim 23.
Kim in view of Chang teaches the method of claim 22
Kim does not teach the first dielectric pattern and the second dielectric pattern comprise the same material
Chang teaches the first dielectric pattern (fig 1:10d1[para 0024]) and the second dielectric pattern (fig 1:10d2[para 0024]) include the same dielectric material ([para 0024]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the first dielectric pattern and the second dielectric pattern comprise the same material in order for the layers to comprises uniform properties of thermal expansion
Regarding claim 24.
Kim in view of Chang teaches the method of claim 22, further:
Kim teaches the first dielectric pattern (fig 2f:113[para 0027]) and the second dielectric pattern (fig 2f:121a[para 0027]) include a photosensitive polymer (ie polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO) [para 0035]).
Regarding claim 26.
Kim in view of Chang teaches the method of claim 22, further:
Kim teaches forming the under- bump pattern (fig 2e:112[para 0023]) includes performing an electroplating process using the first seed layer (fig g 2b:111[para 0023]) as an electrode ([para 0023]).
Regarding claim 27.
Kim in view of Chang teaches the method of claim 22. Further:
Kim teaches the under-bump pattern (fig 2e:112[para 0023]) and the first seed layer (fig 2e:111[para 0022]) include different metal materials ([para 0012,0024]), and the under-bump pattern (fig 2e:112[para 0024]) is in direct contact with a sidewall of the first dielectric pattern (fig 2e:113[para 0024]) exposed by the first opening (fig 2c,2d).
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Regarding claim 28.
Kim in view of Chang teaches the method of claim 22, further:
Kim teaches a level difference between the top surface of the under-bump pattern (fig 2d:112[para 0025]) and a top surface of the first dielectric pattern (fig 2d:113[para 0025]) is less than a thickness of the under-bump pattern (fig 2d:112[para 0025]).
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Regarding claim 29.
Kim in view of Chang teaches the method of claim 22, further:
Chang teaches disposing a release layer (fig 2a:29r[para 0034]) between the carrier substrate (fig 2a:29[para 0034]) and the first seed layer (fig 2a:20s1[para 0034]) before forming the first seed layer (fig 2a:20s1[para 0034]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a release film in order to facilitate the removal of the carrier substrate.
Regarding claim 30.
Kim in view of Chang teaches the method of claim 29, further:
Chang teaches exposing the first seed layer (fig 2j:20s1[para 0034]) by removing the carrier substrate (fig 2j:29[para 0034]) and the release layer (fig 2a:29r[para 0034]); and removing the first seed layer (fig 2j:20s1) to expose a lower surface of the first dielectric pattern (fig 2j:20d1[para 0034]) and a lower surface of the under-bump pattern (fig 2j:21,20s2,20r1[para 0045]).
Regarding claim 31.
Kim in view of Chang teaches the structure of claim 30, further:
Kim teaches forming an external connection terminal (fig 2L:150[para 0050]) directly on the lower surface of the under-bump pattern (fig 2l:112[para 0050]).
Chang teaches a second embodiment comprising forming an external connection terminal (fig 1:12[para 0029]) directly on the exposed lower surface (fig 1:11a2[para 0025]) of the under-bump pattern (fig 1:11,10s1,10r1[para 0029]).
Regarding claim 33.
Kim in view of Chang teaches the structure of claim 22 further:
Kim teaches the redistribution pattern (fig 2e:121b,121c[para 0034]) includes a via portion and a wiring portion on the via portion (fig 2e), the via portion is formed within the second opening (fig 2e[para 0026,0027]), the wiring portion is formed on the top surface of the second dielectric pattern (fig 2e:121a[para 0026,0027]) and the via portion, and a thickness of the under-bump pattern (fig 2e:112[para 0023]) is greater than a thickness of the wiring portion (fig 2e[para 0029,0031]).
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Regarding claim 34.
Kim in view of Chang teaches the method of claim 33, further:
Chang teaches the thickness of the under-bump pattern (fig 2c,2d:21,20s2,20r1) is [greater than] the thickness of the wiring portion (fig 2d).
Given the teaching of the references, it would have been obvious to determine the optimum thickness ratio of the under-bump pattern to the wiring portion. See In re Aller, Lacey and Hall (10 USPQ 233-237) It is not inventive to discover optimum or workable ranges by routine experimentation. Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575,1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 25 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim (US 2020/0335441) in view of Chang (US 2020/0381348) as applied to claim 22 and further in view of Wang (US 2019/0393160).
Regarding claim 25.
Kim in view of Chang teaches elements of the claim 22 above.
Kim teaches forming (fig 2c[para 0024]) the first dielectric pattern (fig 2d:113[para 0024]) includes: coating a first dielectric layer (fig 2c:113[para 0024]) on the first seed layer (fig 2b:111[para 0022]);
Kim in view of Chang does not teach the steps of photo-patterning
Wang teaches forming the first dialectic pattern (fig 2:140[para 0050]) includes:coating a first dielectric layer (fig 2:140[para 0050]);forming a preliminary opening by performing an exposure and development process [para 0050] on the first dielectric layer (fig 9:140[para 0050]); and forming the first opening by curing the first dielectric layer (fig 9:140[para 0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a photosensitive polymer and patterning, developing and curing (paragraph 50) in order that the image is transferred to the dielectric, unwanted material is removed, and the structure is solidified thereby forming a part of the overall structure.
Claim(s) 32 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kim (US 2020/0335441) in view of Chang (US 2020/0381348) as applied to claim 29 and further in view of Hu (US 2020/0126923).
Regarding claim 32.
Kim in view of Chang teaches method of the claim 29 above.
Kim teaches exposing the first seed layer (2j:111[para 0048]) by removing the carrier substrate (171) (paragraph 48) (fig 2j) forming a mask pattern (not shown) including a third opening (opening can be formed on seed layer 151) exposing [a] seed layer (fig 2l:151[para 0050]) on a lower surface of the first seed layer (fig 2L:111[para 0051,0052]); forming a lower under-bump pattern (2L:152[para 0050]) within the third opening (fig 2L[para 0052]), wherein a metal material ([para 0052]) is different from the first seed layer (111:[para 0022]) and the under-bump pattern (112[para 0023]); removing the mask pattern (fig 2L[para 0052]); and forming a first seed pattern (fig 2L:151[para 0052,0053]) by patterning the seed layer (fig 2L:151[para 0052]).
Chang teaches exposing the first seed layer (fig 2J:20s1[para 0045]) by removing the carrier substrate (2J:29[para 0045])) and the release layer (fig 2j:29r[para 0045]) (paragraph 45)
Kim in view of Chang does not teach that the seed layer is the first seed layer.
Hu teaches a mask pattern (104) including a third opening exposing the first the seed layer (Sl1) on a lower surface of the seed layer (fig 16) (paragraph 38).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the mask pattern and third opening of the first seed layer in order to eliminate the step of forming an additional seed layer.
Claim(s) 35, 36, 37, 38, 39, and 41 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2020/0335441) in view of Chang (US 2020/0381348).
Regarding claim 35.
Kim teaches a method of manufacturing a semiconductor package (fig 1:190[para 0019]) comprising: forming a redistribution substrate (fig 2e:120[para 0026]); and placing a semiconductor chip (fig 2f:130[para 0037]) on the redistribution substrate (fig 2f:120[para 0037]), wherein forming the redistribution substrate (fig 2f:120[para 0026]) includes: forming a first seed layer (fig 2b:111[para 0022]) on a carrier substrate (fig 2b:171[para 0021]); forming a first dielectric pattern (fig 2d:113[para 0024]) including a first opening on the first seed layer (fig 2d:111[para 0024,0025]); forming an under-bump pattern (fig 2d:112[para 0025]) within the first opening (fig 2d:0025]);
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forming a second dielectric pattern (fig 2e:121a[para 0027]) including a second opening on the first dielectric pattern (fig 2e:110[para 0026]) and the under-bump pattern (fig 2e:112[para 0026,0027]), wherein the second opening exposes a top surface of the under-bump pattern (fig 2e:112[para 0027]); and forming a redistribution pattern (fig 2e:121b,121c[para 0026]) that fills the second opening and extends onto a top surface of the second dielectric pattern (fig 2e:121a[para 0031]), wherein the second opening overlaps the first opening in a vertical direction (fig 2e{0026]), wherein a bottom surface of the under- bump pattern (fig 2c:112[para 0024]) contact a top surface of the first seed layer (fig 2c:111[para 0024]) , wherein a bottom surface of the second dielectric pattern (fig 2e:121a[para 0026]) contacts a top surface of the under-bump pattern (fig 2e:112[para 0027]), and wherein a width of the top surface of the under-bump pattern (fig 2d:112[para 0024]) is the same as a width of the first opening (fig 2d,2e).
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Kim does not teach the bottom surface of the first dielectric pattern is in contact with the top surface of the first seed layer
Chang teaches wherein a bottom surface of the first dielectric pattern ((fig 2c:20d1[para 0035]) and a bottom surface of the under- bump pattern (fig 2c:21[para 0036]) contact a top surface of the first seed layer (fig 2c:20s1[para 0035], wherein the bottom surface of the first dielectric pattern (fig 20d1) and the bottom surface of the under-bump pattern (fig 2c:21[para 0035.0036]) are at the same vertical level (fig 2c)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the bottom surface of the dielectric layer to be in contact with the top surface of the first seed layer in order to enable the use of a damascene process to form the under-bump pattern and thereby improve dimensional accuracy and reduce metal residue.
Regarding claim 36.
Kim in view of Chang teaches the method of claim 35.
Kim teaches the first seed layer (fig 2d:111[para 0022]) is spaced apart from a side surface of the first dielectric pattern (fig 2c,2e:110[para 0024]).
Regarding claim 37.
Kim in view of Chang teaches the method of claim 35.
Kim teaches forming the redistribution pattern includes: sequentially forming a second seed layer (fig 2e:121b[para 0029]) and a conductive layer (fig 2e:121c[para 0029]) that fill the second opening and extend to the top surface of the second dielectric pattern (fig 2e:121a[para 0027]); and patterning the second seed layer (fig 2e:121b[para 0028]) and the conductive layer (fig 2e:121c[para 0031]), wherein the redistribution pattern (fig 2e:121b,121c[para 0026]) includes a via portion and a wiring portion on the via portion, the via portion is formed within the second opening, and the wiring portion is formed on the top surface of the second dielectric pattern (fig 2e:121a[para 0026]) and the via portion (fig 2e[para 0031]).
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Regarding claim 38.
Kim in view of Chang teaches the method of claim 37.
Kim teaches the second seed layer (fig 2e:121b[para 0029]) is formed directly on the top surface of the under-bump pattern (fig 2e:112[para 0028]) and contacts the top surface of the under-bump pattern (fig 3e:112[para 0031]).
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Regarding claim 39.
Kim in view of Chang teaches the method of claim 35.
Kim teaches wherein the first seed layer (fig 2d:111[para 0022]) and the under-bump pattern (fig 2d:112[para 0023]) include different metal materials ([para 0022,0023]), and wherein the under-bump pattern (fig 2d:112[para 00) is in direct contact with the first dielectric pattern (fig 2d:113[para 0024]).
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Regarding claim 41.
Kim in view of Chang teaches the method of claim 35.
Kim teaches the under- bump pattern (fig 2d:112[para 0024]) includes forming the top surface of the under-bump pattern (fig 2d:112[para 0025]) at a vertical level equal to a vertical level of a top surface of the first dielectric pattern (fig 2d:110[para 0025]).
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Claim(s) 40 is/are rejected under 35 U.S.C. 102a1 as unpatententable over Kim (US 2020/0335441) in view of Chang (US 2020/0381348) as applied to claim 35 and further in view of Wang (US 2019/0393160).
Regarding claim 40.
Kim in view of Chang teaches elements of the claim 35 above.
Chang teaches forming the first dielectric pattern includes: coating a first dielectric layer (fig 2b:20d1[para 0035]) [ ] on the first seed layer (fig 2b:20s1[para 0035])
Kim in view of Chang does not teach the steps of photo-patterning
Wang teaches forming the first dielectric pattern includes: coating a first dielectric layer ((fig 2:140[para 0050]) including a photosensitive dielectric material (PBO) on [...] layer (fig 2:104[para 0050]; forming a first preliminary opening by performing an exposure and development process on the first dielectric layer (fig 2:140[para 0050]) (“patterned using photolithography techniques. PBO is a photosensitive material and may be patterned by exposing the PBO layer in accordance with a desired pattern, developing, and curing” paragraph 50.); and curing the first dielectric layer to form the first opening from the first preliminary opening ([para 0050]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a photosensitive polymer and patterning, developing and curing (paragraph 50) in order that the image is transfer to the dielectric, unwanted material is removed, and the structure is solidified thereby forming a part of the overall structure.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 January 16, 2026