Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s remarks/amendments of claims 11-19 in the reply filed on October 28th, 2025 are acknowledged. Claims 11and 15 have been amended. Claims 1-10 and 20-29 have been cancelled. New claims 30-40 have been added. Claims 11-19 and 30-40 are pending.
Action on merits of claims 1-19 and 30-40 as follows.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 1-19 and 21 are rejected on the ground of non-statutory obviousness-type double patenting as being unpatentable over claims 1-23 of U.S. Patent No. US 11,069,674 hereinafter as PAT ‘674. Although the conflicting claims are not identical, they are not patentably distinct from each other because both claim a same structure and the examined claims are similar to that of the patent’s claims. A species claim anticipates a generic claim; therefore, the patent’s claims anticipate the instant examined claims. MPEP 806.04(i). To be more specific below is a table with the respective claims of the instant application and the co-pending claims.
Instant Claims (18/244524)
PAT ‘674
2
3
2
4
20
5
2
6
10
7
12
8
13
9
14
10
16
Claim 11: A semiconductor device comprising: a first terminal and a second terminal; and at least two pairs of anti-serially connected pn-junction structures coupled between the first and second terminals, each of the pn-junction structures having a corresponding junction grading coefficient, and a first pair and a second pair of the at least two pairs of anti-serially connected pn-junctions structures respectively have first and second junction grading coefficients mi and m2, respectively, where the junction grading coefficients mi and m2 have values configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals.
Claim 1: A semiconductor device comprising: “n” pairs of pn-junction structures, with n is an integer≥2, wherein the i-th pair, with i∈{1, . . . , n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type comprises an i-th junction grading coefficient m.sub.i, wherein the junction grading coefficients m.sub.1, m.sub.2 of the first and second pair of the n pairs of pn-junction structures result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m.sub.1, m.sub.2 are 0.25.
Claim 11: a first connecting terminal and a second connecting terminal, wherein the “n” pairs of pn-junction structures are connected between the first and second terminal.
12
1
13, 22
13
14
10
Claim 15: A semiconductor device comprising: n pairs of pn-junction structures, where n is an integer >2, an i-th pair of the n pairs including two pn-junction structures of an i-th type that are anti-serially connected and the pn-junction structure of the i-th type having an i-th junction grading coefficient mi; and at least one pair of the n pairs of pn-junction structures arranged as a pair of two composite pn-junction structures, each composite pn-junction structure having a first partial pn-junction structure and a second partial pn-junction structure, the first partial pn-junction structure having a first partial junction grading coefficient mii, and the second partial pn-junction structure having a second partial junction grading coefficient mi2 different than the first partial junction grading coefficient mii, and the i-th junction grading coefficient mi of the composite pn-junction structure being based on a combination of the first and second partial junction grading coefficients mii, mi2.
Claim 1: A semiconductor device comprising: “n” pairs of pn-junction structures, with n is an integer≥2, wherein the i-th pair, with i∈{1, . . . , n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type comprises an i-th junction grading coefficient m.sub.i, wherein the junction grading coefficients m.sub.1, m.sub.2 of the first and second pair of the n pairs of pn-junction structures comprises a first junction grading coefficient with m.sub.1≤0.48 and a second pair of the n pairs of pn-junction structures comprises a second junction grading coefficient m.sub.2≥0.52.
16
2
17
13
18
19
19
Claim 40: A semiconductor device comprising: a first terminal and a second terminal; and at least two pairs of anti-serially connected pn-junction structures coupled between the first and second terminals, wherein a first pair and a second pair of the at least two pairs of anti-serially connected pn-junctions structures comprise first and second junction grading coefficients m1 and m2, respectively, and wherein the junction grading coefficients m1 and m2 have values selected to reduce generation of spurious odd harmonic signals across the first and second terminals.
Claim 1: A semiconductor device comprising:
“n” pairs of pn-junction structures, with n is an integer≥2, wherein the i-th pair, with i∈{1, . . . , n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type comprises an i-th junction grading coefficient m.sub.i, wherein at least a first pair of the n pairs of pn-junction structures comprises a first junction grading coefficient with m.sub.1≤0.48 and a second pair of the n pairs of pn-junction structures comprises a second junction grading coefficient m.sub.2≥0.52, and wherein the junction grading coefficients m.sub.1, m.sub.2 of the first and second pair of the n pairs of pn-junction structures result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m.sub.1, m.sub.2 are 0.25.
Claim 11: a first connecting terminal and a second connecting terminal, wherein the “n” pairs of pn-junction structures are connected between the first and second terminal.
35 USC § 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 30 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The limitation: “m1 and m2 are the same” as recited in claim 30 is not disclosed in specification.
35 USC § 112(f)/sixth paragraph
CLAIM INTERPRETATION
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “the junction grading coefficients configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminal…; …” as recited in claims 11 , 15 and 40.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
If applicant wishes to provide further explanation or dispute the examiner’s interpretation of the corresponding structure, applicant must identify the corresponding structure with reference to the specification by page and line number, and to the drawing, if any, by reference characters in response to this Office action.
For more information, see MPEP § 2173 et seq. and Supplementary Examination Guidelines for Determining Compliance With 35 U.S.C. 112 and for Treatment of Related Issues in Patent Applications, 76 FR 7162, 7167 (Feb. 9, 2011).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 11-12, 14, 30-31, 36-37-39 and 40 are rejected under 35 U.S.C. 103 as being unpatentable over De Vreede (US 2008/0191260, hereinafter as Vree ‘260).
Regarding Claim 11, Vree ‘260 teaches a semiconductor device comprising:
a first terminal and a second terminal (Fig. 5b, (100); [0050]); and
at least two pairs of anti-serially connected pn-junction structures coupled between the first and second terminals (see Fig. 5b), wherein each of the pn-junction structures comprising a corresponding junction grading coefficient, wherein a first pair and a second pair of the at least two pairs of anti-serially connected pn-junctions structures comprise first and second junction grading coefficients m1 and m2, respectively, and wherein the junction grading coefficients m1 and m2 have values (see para. [0066]).
Thus, Vree ‘260 is shown to teach all the features of the claim with the exception of explicitly the limitation: “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select the values of junction grading coefficients of the pn-junction structures configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further, it would have been obvious in the absence of a showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize to adjust the values of junction grading coefficients as a result effective variable that depends on the design of the device.
Examiner notes that claim 11 contains functional limitation “to reduce a signal power level of a spurious third harmonic signal across the first and second terminals” (emphasis added). According to MPEP 2173(05) g. "the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals” is nothing else than the result achieved by the invention.
Regarding Claim 40, Vree ‘260 teaches a semiconductor device comprising:
a first terminal and a second terminal (Fig. 5b, (100); [0050]); and
at least two pairs of anti-serially connected pn-junction structures coupled between the first and second terminals, wherein a first pair and a second pair of the at least two pairs of anti-serially connected pn-junctions structures comprise first and second junction grading coefficients m1 and m2, respectively, and wherein the junction grading coefficients m1 and m2 have values (see para. [0066]).
Thus, Vree ‘260 is shown to teach all the features of the claim with the exception of explicitly the limitation: “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select the values of junction grading coefficients of the pn-junction structures configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further, it would have been obvious in the absence of a showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize to adjust the values of junction grading coefficients as a result effective variable that depends on the design of the device.
Examiner notes that claim 40 contains functional limitation “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals” (emphasis added). According to MPEP 2173(05) g. "the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals” is nothing else than the result achieved by the invention.
Regarding Claim 12, Vree ‘260 teaches the signal power level of the spurious third harmonic signal is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients are equal (see para. [0066]).
Further, it has been held to be within the general skill of a worker in the art to have the signal power level of the spurious third harmonic signal is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the signal power level of the spurious third harmonic signal is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case when this improves the performance of the semiconductor device.
Regarding Claim 14, Vree ‘260 teaches the pn-junction structure of the at least two pairs of anti-serially connected pn-junction structures is a diode structure with an anode region and a cathode region (see Fig. 5b; [0051]).
Regarding Claim 30, Vree ‘260 teaches m1 and m2 are the same (see Fig. 1; para. [0051]).
Since the areas of the junctions (20,30) are equal to each other so as to provide a device that is highly symmetric, it would obviously appear that m1 and m2 are the same.
Regarding Claim 31, Vree ‘260 teaches m1 and m2 = 0.5 (see para. [0066]).
Thus, Vree ‘260 is shown to teach all the features of the claim with the exception of explicitly the limitation: “m2 = 0.25”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select the values of junction grading coefficients of the pn-junction structures m2 = 0.25, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further, it would have been obvious in the absence of a showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize to adjust the values of junction grading coefficients as a result effective variable that depends on the design of the device.
Regarding Claim 36, Vree ‘260 is shown to teach all the features of the claim with the exception of explicitly the limitation: “first to n junction grading coefficients mi to mn satisfy within a tolerance range of +/- 0.05 the following ellipse equation:
PNG
media_image1.png
42
128
media_image1.png
Greyscale
= 1, with I= 16, wherein parameters ai are determined based on a zero bias capacitance Cjoi and a junction voltage potential Vji of the pn-junction structure of an i-th type”.
However, it has been held to be within the general skill of a worker in the art to select the first to n junction grading coefficients mi to mn satisfy within a tolerance range of +0.05 on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the first to n junction grading coefficients mi to mn satisfy within a tolerance range of +/- 0.05 when this improves the performance of the semiconductor device.
Regarding Claim 37, Vree ‘260 teaches at least two pairs of anti-serially connected pn-junction structures are arranged in a stacked configuration in a semiconductor substrate (10) (see Fig. 3, para. [0032]).
Regarding Claim 38, Vree ‘260 teaches m1 and m2 = 0.5 (see para. [0066]), thus each junction grading coefficient of a respective pn-junction structure of the first pair is the same.
Regarding Claim 39, Vree ‘260 teaches m1 and m2 = 0.5 (see para. [0066]), thus each junction grading coefficient of a respective pn-junction structure of the second pair is the same.
Claims 15-19 and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Vree ‘260 in view of Wright (US 2016/0329918, hereinafter as Wrig ‘918).
Regarding Claim 15, Vree ‘260 teaches a semiconductor device comprising:
a first terminal and a second terminal (Fig. 5b, (100); [0050]); and
n pairs of pn-junction structures, an i-th pair of the n pairs including two pn-junction structures of an i-th type that are anti-serially connected and the pn-junction structure of the i-th type comprising an i-th junction grading coefficient mi (see para. [0066]); wherein at least one pair of the n pairs of pn-junction structures is a pair of two composite pn-junction structures, each composite pn-junction structure comprising a first partial pn-junction structure and a second partial pn-junction structure (see Fig. 4), wherein the first partial pn-junction structure comprises a first partial junction grading coefficient mi1, and the second partial pn-junction structure comprising a second partial junction grading coefficient mi2, and the i-th junction grading coefficient mi of the composite pn-junction structure being based on a combination of the first and second partial junction grading coefficients mi1, mi2.
Thus, Vree ‘260 is shown to teach all the features of the claim with the exception of explicitly the limitation: “n is an integer >2, and a second partial junction grading coefficient mi2 different than the first partial junction grading coefficient mi1.
Wrig ‘918 teaches n is an integer >2 (see Fig. 2); and a second partial junction grading coefficient mi2 different than the first partial junction grading coefficient mi1 (see para. [0032]). Since the second effective area that is smaller than the first effective area and each have a second parasitic capacitance that is smaller than the first parasitic capacitance (see para. [0032]), it would obviously appear that the second partial junction grading coefficient mi2 different than the first partial junction grading coefficient mii.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Vree ‘260 by having n is an integer >2, and the first and second junction grading coefficient are different from each other in order to reduce second harmonics related to parasitic capacitances in anti-series varactor applications (see abstract; para. [0035]) as suggested by Wrig ‘918.
Thus, Vree ‘260 and Wrig ‘918 are shown to teach all the features of the claim with the exception of explicitly the limitation: “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals”.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to select the values of junction grading coefficients mi1 and mi2 of the pn-junction structures configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Further, it would have been obvious in the absence of a showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). Therefore, one of ordinary skill in the art, before the effective filing date of the claimed invention, would recognize to adjust the values of junction grading coefficients as a result effective variable that depends on the design of the device.
Examiner notes that claim 15 contains functional limitation “to reduce a signal power level of a spurious third harmonic signal across the first and second terminals” (emphasis added). According to MPEP 2173(05) g. "the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “configured to reduce a signal power level of a spurious third harmonic signal across the first and second terminals” is nothing else than the result achieved by the invention.
Further, it has been held to be within the general skill of a worker in the art to have the second partial junction grading coefficient mi2 different than the first partial junction grading coefficient mi1 on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the second partial junction grading coefficient mi2 different than the first partial junction grading coefficient mi1 when this improves the performance of the semiconductor device.
Regarding Claim 16, Vree ‘260 teaches a first pair and a second pair, one of the first pair and the second pair including a composite pn-junction structure having a diode structure formed on a semiconductor substrate (Fig. 2, (10); [0052]) and a voltage dependent capacitance structure (see para. [0060]) laterally adjacent the pn-junction structure on the semiconductor substrate.
Regarding Claim 17, Vree ‘260 teaches the first and second partial junction grading coefficients mi1 and mi2 have values determined by doping profiles of respective regions defining the pn-junction structure (see para. [0017]).
Wrig ‘918 teaches the voltage dependent capacitance and relative areas of the respective regions defining the pn-junction structure and the voltage dependent capacitance (see para. [0043]).
Regarding Claim 18, Vree ‘260 teaches an oxide region (see para. [0034] and [0052]) adjoining a semiconductor region, and wherein the voltage dependent capacitance includes an inversion layer formed in the semiconductor region along vertical sidewalls of a deep isolation trench structure adjoining the semiconductor region.
Regarding Claim 19, Vree ‘260 teaches the first and second partial pn-junction structures of a first type pn-junction structure and the first and second partial pn-junction structure of a second type pn-junction structure are arranged together in a laterally isolated common region of a semiconductor substrate (10) (see Fig. 4 ).
Regarding Claim 32, Vree ‘260 teaches m1 and m2 = 0.5 (see para. [0066]).
Wrig ‘918 teaches a second grading coefficient m2 different than the first grading coefficient m1 (see para. [0032]). Since the second effective area that is smaller than the first effective area and each have a second parasitic capacitance that is smaller than the first parasitic capacitance (see para. [0032]), it would obviously appear that the second grading coefficient m2 different than the first grading coefficient m1.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Vree ‘260 as applied to claim 11 above, and further in view of Yao (US 2018/0047718, hereinafter as Yao ‘718).
Regarding Claims 13 and 22, Vree ‘260 is shown to teach all the features of the claim with the exception of explicitly the limitations: “an electrostatic discharge device”.
Yao ‘718 teaches an electrostatic discharge device (see para. [0006] and abstract).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Vree ‘260 by having an electrostatic discharge device for the purpose of protecting the high-speed data transfer interface such as HDMI, USB, DVI and the like (see para. [0005]) as suggested by Yao ‘718.
Claim 33-35 are rejected under 35 U.S.C. 103 as being unpatentable over Vree ‘260 and Wrig ‘918 as applied to claim 32 above, and further in view of Johansson (US 2004/0235257, hereinafter as Joha ‘257).
Regarding Claims 33, Vree ‘260 teaches m1 and m2 = 0.526 (see para. [0066]) which overlaps claim range of m2>0.5.
Vree ‘260 and Wrig ‘918 are shown to teach all the features of the claim with the exception of explicitly the limitation: “the first junction grading coefficient m1 is <05”.
Joha ‘257 teaches the junction grading coefficient m1= 1/3 (see para. [0020]) which is overlap claim range of m1 <0.5.
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Vree ‘260 and Wrig ‘918 by having the first junction grading coefficient m1 <0.5 in order to obtain a linear relationship between voltage and frequency (see para. [0020] and [0028]) as suggested by Joha ‘257.
Regarding Claims 34, Vree ‘260 teaches m2 = 0.526 (see para. [0066]) which overlaps claim range of m2>0.52.
Vree ‘260, Wrig ‘918 and Joha ‘257 are shown to teach all the features of the claim with the exception of explicitly the limitation: “m2 = 0.52”.
However, it has been held to be within the general skill of a worker in the art to select the second junction grading coefficient m2 = 0.52 on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select the second grading coefficient m2 = 0.52 when this improves the performance of the semiconductor device.
Regarding Claims 35, Joha ‘257 teaches the junction grading coefficient m1= 1/3 (see para. [0020]) which is overlap claim range of m1 ≤ 0.45.
Response to Arguments
Applicant's arguments, with regards to claims 1-19 and 30-40, filed on October 28th, 2025 have been fully considered but are moot in view of the new ground of rejection.
Interviews After Final
Applicants note that an interview after a final rejection is permitted in order to place the application in condition for allowance or to resolve issues prior to appeal. However, prior to the interview, the intended purpose and content of the interview should be presented briefly, preferably in writing. Upon review of the agenda, the Examiner may grant the interview if the examiner is convinced that disposal or clarification for appeal may be accomplished with only nominal further consideration. Interviews merely to restate arguments of record or to discuss new limitations will be denied. See MPEP § 714.13
Conclusion
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner Dzung Tran whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Supervisor Sue Purvis can be reached on 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/DZUNG TRAN/
Primary Examiner, Art Unit 2893
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