DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 6, 8, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al US 2022/0093564 (Chen 1) and further in view of Chen et al US 2015/0270247 (Chen 2).
Pertaining to claim 1, Chen 1 teaches a semiconductor package comprising:
a first redistribution layer 100 including a first insulating layer and a first conductive pattern disposed in the first insulating layer See Figure 1;
a first connection terminal 188 disposed on a first surface of the first redistribution layer;
a stacked memory module 150 disposed on second surface of the first redistribution layer 100 see Figure 8; and
a dummy structure 140 disposed between the first redistribution layer 100 and spaced apart from the stacked memory module 150 see Figure 1.
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Chen 1 fails to teach:
a second redistribution layer disposed on the stacked memory module, and including a second insulating layer and a second conductive pattern disposed in the second insulating layer;
a first bump disposed on a first surface of the second redistribution layer, and in contact with the stacked memory module; and
a first semiconductor chip disposed on second surface of the second redistribution layer;
Chen 2 teaches:
a second redistribution layer 402/404/406 disposed on stacked memory module 110/510 see [0022], and including a second insulating layer 402 and a second conductive pattern 404/406 disposed in the second insulating layer;
a first bump 408 disposed on a first surface of the second redistribution layer, and in contact with the stacked memory module 510 see Figure 3D; and
a first semiconductor chip 410 disposed on second surface of the second redistribution layer See Figure 3D;
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It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Chen 2 with the device of Chen 1. The ordinary artisan would have done so for at least the purpose of interfacing the memory stack structure of Chen 1 with additional functionality by connecting to more processing elements as taught by Chen 2 and shown in Figure 3D.
Pertaining to claim 4, Chen 1 in view of Chen 2 teaches the semiconductor package of claim 1, further comprising a via 108 of Chen 2 see Figure 3D disposed between the first redistribution layer 204 and the second redistribution layer 402/404/406, wherein the via electrically connects the first redistribution layer with the second redistribution layer See Figure 3D.
Pertaining to claim 6, Chen 1 in view of Chen 2 teaches the semiconductor package of claim 1, wherein the first redistribution layer includes a passivation layer 170 covering the first surface of the first redistribution layer, wherein a first pad 182 is exposed from the passivation layer 170, and the first connection terminal 188 is disposed on the first pad 182 see Figure 1.
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Pertaining to claim 8, Chen 1 in view of Chen 2 teaches the semiconductor package of claim 1, further comprising a second semiconductor chip 410 see Figure 3D of Chen 2 disposed on the second redistribution layer and disposed at one side of the first semiconductor chip 410 (there are two 410 elements), wherein the first semiconductor chip is different from the second semiconductor chip. They are different sizes at the very least (Figure 3D), see also [0049] Chen 2
Pertaining to claim 12, Chen 1 in view of Chen 2 teaches the semiconductor package of claim 1, wherein the dummy structure 140 includes silicon. Chen 1 [0038]
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al US 2022/0093564 (Chen 1) and further in view of Chen et al US 2015/0270247 (Chen 2) and further in view of Huang et al US 2020/0051936.
Pertaining to claim 13, Chen 1 teaches a semiconductor package comprising:
a first redistribution layer 100 including a first insulating layer and a first conductive pattern disposed in the first insulating layer See Figure 1;
a first connection terminal 188 disposed on the first redistribution layer 100;
a stacked memory module 150 disposed on the first redistribution layer 100 see Figure 8; and
a dummy structure 140 disposed between the first redistribution layer 100 and spaced apart from the stacked memory module 150 see Figure 8.
Chen 1 fails to teach:
a second redistribution layer disposed on the stacked memory module, and including a second insulating layer and a second conductive pattern disposed in the second insulating layer;
a first semiconductor chip disposed on the second redistribution layer;
a first bump disposed on the first semiconductor chip, and electrically connecting the first semiconductor chip with the second redistribution layer
Chen 2 teaches:
a second redistribution layer 402/404/406 disposed on stacked memory module 110/510 see [0022], and including a second insulating layer 402 and a second conductive pattern 404/406 disposed in the second insulating layer;
a first semiconductor chip 410 disposed on the second redistribution layer See Figure 3D;
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to incorporate the teachings of Chen 2 with the device of Chen 1. The ordinary artisan would have done so for at least the purpose of interfacing the memory stack structure of Chen 1 with additional functionality by connecting to more processing elements as taught by Chen 2 and shown in Figure 3D.
Chen 1 in view of Chen 2 fails to teach:
a first bump disposed on the first semiconductor chip, and electrically connecting the first semiconductor chip with the second redistribution layer (Chen 2 teaches wire bonds 412) However, bumps were an obvious alternative to wire bonding at the time the invention was filed. Huang teaches connecting a semiconductor package to a device package analogous to what is taught by both Chen 1 and Chen 2, the package 350 being connected to the second redistribution layer 330 using bumps 340 see Figure 3J. It would have been within the scope of one of ordinary skill in the art at the time the invention was filed to combine the teachings of Chen 1/Chen 2 and Huang to enable the electrical connection step of Chen 1/Chen 2to be performed according to the teachings of Huang because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed connection step of Chen 1/Chen 2and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claim 14, Chen 1/Chen 2/Huang teach the semiconductor package of claim 13, wherein the stacked memory module is in contact with a bottom surface of the second redistribution layer. In Chen 2 module 510 is in electrical contact with second redistribution layer 402/404/406
Pertaining to claim 15, Chen 1/Chen 2/Huang teach the semiconductor package of claim 13, wherein a height of the stacked memory module is a same as a height of the dummy structure in a direction perpendicular to an upper surface of the first redistribution layer. See Chen 1 Figure 1 the dummy element 140 is the same height as the memory stack 150.
Claim(s) 2, 3, 10, 11, 16, 17, 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al US 2022/0093564 (Chen 1) and further in view of Chen et al US 2015/0270247 (Chen 2) and further in view of Huang et al US 2020/0051936 as applied to claims 1 and 13 above respectively.
Pertaining to claims 11 and 19, Chen 1/Chen 2/Huang teach the semiconductor package of claim 13, but Chen 2 does not teach wherein the first bump includes a first pillar layer and a first solder layer, wherein the first pillar layer is disposed on a bottom surface of the first semiconductor chip, wherein the first solder layer is disposed on the first pillar layer, and the first pillar layer is in contact with the second redistribution layer. Chen 2 teaches a simple solder bump. Chen 1 however teaches a pillar/solder connection arrangement between a redistribution layer and additional elements. See Chen 1 elements 184 (pillar) and 186 (solder). It would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the pillar/solder connection of Chen 1 in place of the solder bump of Chen 2 because one of ordinary skill in the art at the time the invention was filed would have been motivated to look to alternative suitable methods of performing the disclosed connection step of Chen 1/Chen 2and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Pertaining to claims 2 and 18, Chen 1/Chen 2/Huang teach a plurality of first terminals (See Chen 1 elements 188) (see Chen 2 elements 212) but are silent with regards to the distance between said plurality of terminals being about 50µm to about 75µm. However, the spacing of these features directly impact size and function of the overall device (too close they could short, for example, or could be too difficult to manufacture).
Pertaining to claims 3 and 16, Chen 1/Chen 2/Huang teach wherein a width of the first connection terminal is about 100µm to about 150µm in a direction parallel with the second surface of the first redistribution layer. Huang teaches in an analogous art with a similar package device, connection terminals 340 within this range (318 is 100µm to 200µm which places element 340 close to this range see [0036]).
For claims, 2, 3, 16 and 18, It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of the contact and the thickness of the redistribution layer through routine experimentation and optimization to obtain optimal or desired device performance because thickness is a result-effective variable (size of final device, function and prevention of damage/fragility) and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Pertaining to claims 10 and 17, Chen 1 teaches a redistribution layer 100. Chen 1 teaches elements t1 and t2 having thicknesses ranging from 5µm to 20µm see Figure 1 and [0037]. This would place the redistribution layer 100 of Chen 2 firmly near this thickness range. It would have been obvious to one of ordinary skill in the art of making semiconductor devices to determine the workable or optimal value for the width of the contact and the spacing distance of the contacts through routine experimentation and optimization to obtain optimal or desired device performance because size and spacing are result-effective variables and there is no evidence indicating that it is critical or produces any unexpected results and it has been held that it is not inventive to discover the optimum or workable ranges of a result-effective variable within given prior art conditions by routine experimentation. See MPEP § 2144.05
Given the teaching of the references, it would have been obvious to determine the optimum thickness, temperature as well as condition of delivery of the layers involved. See In re Aller, Lacey and Hall (10 USPQ 233-237) “It is not inventive to discover optimum or workable ranges by routine experimentation.” Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Any differences in the claimed invention and the prior art may be expected to result in some differences in properties. The issue is whether the properties differ to such an extent that the difference is really unexpected. In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicants have the burden of explaining the data in any declaration they proffer as evidence of non-obviousness. Ex parte Ishizaka, 24 USPQ2d 1621, 1624 (Bd. Pat. App. & Inter. 1992).
An Affidavit or declaration under 37 CFR 1.132 must compare the claimed subject matter with the closest prior art to be effective to rebut a prima facie case of obviousness. In re Burckel, 592 F.2d 1175, 201 USPQ 67 (CCPA 1979).
Allowable Subject Matter
Claims 5, 7 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Pertaining to claim 5, the prior art does not teach nor suggest wherein the dummy structure is in contact with the first and second redistribution layers in combination with the memory stack being bump connected to the second redistribution layer (claim 1)
Pertaining to claim 7, the prior art does not teach nor suggest wherein the dummy structure is provided as a plurality of dummy structure, the plurality of dummy structures disposed around the stacked memory module.
Pertaining to claim 9, the prior art does not teach nor suggest wherein the dummy structure includes first and second dummy structures that have first and second widths being different.
Claims 20 is allowed.
The following is an examiner’s statement of reasons for allowance: The primary reason for the allowance of the claims is the specific requirement wherein the dummy structure is in contact with the first and second redistribution layers while the memory stack is bump connected to the second redistribution layer and on the upper surface of the first redistribution layer (note that Chen 1 teaches the dummy structure being coplanar with the top of the memory stack), in all of the claims which is not found in the prior art references.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS J TOBERGTE whose telephone number is (571)272-6458. The examiner can normally be reached M-F 7:30-4:30.
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/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817