DETAILED ACTION
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier.
Such claim limitation is: “circuitry to receive …” in claims 1-7 and “processors to receive …” in claims 15-20.
Because this claim limitation is being interpreted under 35 U.S.C. 112(f), it is being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this limitation interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation to avoid it being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation recites sufficient structure to perform the claimed function so as to avoid it being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-22 are rejected under 35 U.S.C. 103 as being unpatentable over Chalfin (US 2024/0,036,919) in view of Yu (US 11,093,225).
Referring to claims 1, 8 and 15, Chalfin discloses a processor (fig. 5, system 500) comprising:
circuitry (fig. 5, processor 110) to perform instructions (para.0060, command stream) in memory (fig. 5, memory 520) that [cause the circuitry to receive parameter comprised in ] comprises a kernel invocation (fig. 4, sequence of commands to be executed 410), [the parameter] to indicate dependency of second software kernel (fig. 2, task 210; para.0013, second command) on first software kernel (fig. 2, task 220; para.0013, first command), and
as a result (fig. 4, generating tasks 420) of receiving the kernel invocation, schedule the second software kernel and the first software kernel to be performed according to the dependency (fig. 2, tasks 210/220; para.0047, dependency tracker 16 schedules task 210/220).
Yu discloses the instructions cause the circuitry to receive parameter (21:6-20, explicit dependency information) comprised in a kernel invocation (21:6-20, neural network algorithm model instructions), the parameter to indicate dependency (21:6-20, dependency information for subsequent instruction; fig. 10, S1020) of second software kernel on first software kernel (21:6-20, current instruction; fig. 10, S1010).
Chalfin and Yu are analogous art because they are from the same field of endeavor in instruction execution using dependency information. Before the time of the filing, it would have been obvious to a person of ordinary skill in the art, having the teaching of Chalfin and Yu before him or her to modify the dependency tracker of Chalfin to include the explicit dependency information of Yu, thereafter the dependency tracker tracks execution with the explicit dependency information. The suggestion and/or motivation for doing so would be obtaining advantage of improved scheduling for execution parallelism (7:43-60) as suggested by Yu. Therefore, it would have been obvious to combine Chalfin with Yu to obtain the invention as specified in the instant application claims.
As to claims 2-3, 9-10 and 16-17, Chalfin discloses the processor of claim 1, wherein the dependency indicates that the first software kernel is to be performed before the second software kernel (para.0010, first/parent command before second/child command).
As to claims 4, 11 and 18, Chalfin discloses the processor of claim 1, wherein the circuitry is to perform the second software kernel and the first software kernel according to the dependency (para.0010, second command dependency).
As to claims 5, 12 and 19, Chalfin discloses the processor of claim 1, wherein the first software kernels and the second software kernel are associated with two grids (para.0029, concurrent processing) comprising a thread (para.0029, threads) to perform the first software kernel and the second software kernel based on the dependency (para.0010, dependency tracker).
As to claims 6 and 13, Chalfin discloses the processor of claim 1, wherein the circuitry is to cause the first software kernel to indicate dependency of the second software kernel using a graphics processing unit GPU (para.0029, GPU).
As to claims 7, 14 and 20, Chalfin discloses the processor of claim 1, wherein the circuitry is to cause the first software kernel and the second software kernel to be scheduled to be performed in an order (para.0047, sequence of commands; para.0048, desired order) based on the dependency.
As to claim 21, Yu discloses the processor of claim 1, wherein the first software kernel (fig. 10, current instruction S1010) is to indicate any dependencies (fig. 10, dependency information S1020) of the child software kernel (fig. 10, subsequent instruction) launched at runtime (fig. 10, execution S1010) by the first software kernel. (see TSM analysis above in claim 1).
As to claim 22, Yu discloses the processor of claim 1, wherein the circuitry is to use the dependency to construct a graph (fig. 12, directed acyclic graph DAG is generated S1220) to use to schedule (1:42-51, instruction scheduling) the second software kernel and the first software kernel. (see TSM analysis above in claim 1).
Conclusion
Applicant’s amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, this action is made final. See MPEP §706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire in THREE MONTHS from the mailing date of this action. In the event a first reply is filled within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date of the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136 (a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than six months from the date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Cheng-Yuan Tseng whose telephone number is (571)272-9772, and fax number is (571)273-9772. The examiner can normally be reached on Monday through Friday from 09:00 to 17:30 Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alicia Harrington can be reached on (571)272-2330. The fax phone number for the organization where this application or proceeding is assigned is (571)273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866)217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800)786-9199 (IN USA OR CANADA) or (571)272-1000.
/CHENG YUAN TSENG/Primary Examiner, Art Unit 2615
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