Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Objections
Claim 3 is objected to because of the following informalities: “spaced apart a lateral direction” should be changed to “spaced apart in a lateral direction”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “close” in claim 4 is a relative term which renders the claim indefinite. The term “close” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. One of skill in the art would not understand how close it must be to be considered close.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 13-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fukuzumi et al. (US Pub. No. 2016/0079164 A1), hereafter referred to as Fukuzumi.
As to claim 1, Fukuzumi discloses a semiconductor device (fig 1, [0017]), comprising:
a peripheral circuit (200);
a stacked structure (100) comprising a first side (bottom side) and a second side (top side) along a vertical direction, and comprising alternating conductive layers (WL; [0024]) and first insulating layers (40; [0024]);
a memory string (MS; [0023]) extending through the stacked structure (100);
a bonding structure (fig 1, 73, 75, 74, 76, dielectric interlayers) located between the first side (bottom side) of the stacked structure (100) and the peripheral circuit (200) in the vertical direction and connected with the memory string (MS) and the peripheral circuit (200);
a second insulating layer (45) located at the second side (top side) of the stacked structure (100); and
a conductor structure (71) located in the second insulating layer (45).
As to claim 2, Fukuzumi discloses the semiconductor device of claim 1 (paragraphs above),
a substrate (5) located on a side of the peripheral circuit (200) far from the bonding structure (74a); and
a semiconductor layer (substrate 10) located between the second side (top side) of the stacked structure (100) and the second insulating layer (45), wherein the memory string (MS) is in contact with the semiconductor layer (10; [0026]).
As to claim 3, Fukuzumi discloses the semiconductor device of claim 2 (paragraphs above),
wherein the conductor structure comprises a first conductor structure (71) and a second conductor structure (BG) spaced apart in a lateral direction.
As to claim 4, Fukuzumi discloses the semiconductor device of claim 3 (paragraphs above),
wherein the first conductor structure (see fig 8, 111) comprises a first surface and a second surface along the vertical direction (top and bottom surfaces), and the first surface is close to the semiconductor layer (10) relative to the second surface (bottom surface);
the second conductor structure (BG) comprises a third surface and a fourth surface along the vertical direction (top and bottom surfaces), and the third surface (top) is close to the semiconductor layer (10) relative to the fourth surface (bottom); and
the first surface and the third surface are coplanar (fig 8, BG and 110 are coplanar).
As to claim 5, Fukuzumi discloses the semiconductor device of claim 1 (paragraphs above),
wherein the bonding structure comprises a dielectric layer (75) and bonding pad (74b) in the dielectric layer (75); and
the bonding pad (74b) is connected with at least one of the memory string (MS) and the peripheral circuit (200).
As to claim 6, Fukuzumi discloses the semiconductor device of claim 1 (paragraphs above),
wherein the bonding structure comprises an array interconnection layer (76) located between the peripheral circuit (200) and the first side of the stacked structure (bottom side of 100);
the array interconnection layer (76) comprises an array interconnection structure (lower 76) and a first bonding pad (upper 76); and
the array interconnection structure is located between and connected with the first bonding pad (76) and the memory string (MS) in the vertical direction.
As to claim 7, Fukuzumi discloses the semiconductor device of claim 6 (paragraphs above),
wherein the bonding structure comprises a peripheral interconnection layer (lower 76) located between the array interconnection layer (76) and the peripheral circuit (200);
the peripheral interconnection layer comprises a peripheral interconnection structure and a second bonding pad (lower 76 and 79); and
the peripheral interconnection structure is located between and connected with the second bonding pad and the peripheral circuit in the vertical direction (lower 76 and 79 and 200 and fig 6 shown with 91 and 93).
As to claim 8, Fukuzumi discloses the semiconductor device of claim 7 (paragraphs above),
wherein the first bonding pad and the second bonding pad are contacted and connected in the vertical direction (74a and 76 including 93 and 91 shown in fig 6).
As to claim 9, Fukuzumi discloses the semiconductor device of claim 2 (paragraphs above),
a through contact (fig 9, 121) penetrating through the semiconductor layer (10) and connected with the conductor structure (72) and the peripheral circuit (200), wherein the through contact (121) is isolated from the semiconductor layer (portion of BG by the dielectric layer 45).
As to claim 13, Fukuzumi discloses a method for forming a semiconductor device (figs 6-8; [0011]), comprising:
forming a peripheral circuit (200);
forming a stacked structure (100) comprising a first side (bottom side) and a second side (top side) along a vertical direction, and comprising alternating conductive layers and first insulating layers (WL/40; [0024]);
forming memory strings (MS) extending through the stacked structure (100) from the second side (top side) of the stacked structure (100);
bonding the memory strings and the peripheral circuit (figs 6-7, W1 bonded to W2);
forming a second dielectric layer (45) on the second side (top side) of the stacked structure (100); and
forming conductor structures (fig 8, 111/110; [0109]) located in the second dielectric layer (45).
As to claim 14, Fukuzumi discloses the method of claim 13 (paragraphs above),
further comprising prior to bonding the memory strings and the peripheral circuit, forming an array interconnection layer between the peripheral circuit and the first side of the stacked structure (fig 6, array interconnection layer 73/91 in dielectric is formed before the bonding),
wherein the array interconnection layer comprises an array interconnection structure (73) and a first bonding pad (91), and the array interconnection structure (73/91) is located between and connected with the first bonding pad (91) and the memory strings (MS) in the vertical direction.
As to claim 15, Fukuzumi discloses the method of claim 14 (paragraphs above),
further comprising prior to bonding the memory strings and the peripheral circuit (fig 6 shows before bonding), forming a peripheral interconnection layer (76) located between the array interconnection layer (73) and the peripheral circuit (200),
wherein the peripheral interconnection layer comprises a peripheral interconnection structure (76) and a second bonding pad (93), and the peripheral interconnection structure (76) is located between and connected with the second bonding pad (93) and the peripheral circuit (200) in the vertical direction.
As to claim 16, Fukuzumi discloses the method of claim 15 (paragraphs above),
wherein bonding the memory strings and the peripheral circuit comprises bonding the first bonding pad and the second bonding pad (figs 6-7, 91 bonded to 93).
As to claim 17, Fukuzumi discloses the method of claim 13 (paragraphs above),
wherein forming the peripheral circuit comprises obtaining a substrate (5) and forming the peripheral circuit (W2) on the substrate (5); and
forming the stacked structure comprises forming an initial semiconductor layer (10) and forming the stacked structure (W1) on the initial semiconductor layer (10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10-12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzumi in view of Park et al. (US Pub. No. 2016/0204111 A1), hereafter referred to as Park.
As to claim 10, Fukuzumi discloses the semiconductor device of claim 2 (paragraphs above),
Fukuzumi does not disclose wherein the semiconductor layer comprises a single crystalline silicon.
Nonetheless, Park discloses a memory string that is formed as a NAND memory string (figs 1-2, [0064]) and wherein a single crystalline silicon layer is used as the silicon layer in the memory device ([0133]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the memory string of Fukuzumi as a NAND memory string with a single crystalline silicon layer as taught by Park since the NAND memory string with single crystalline silicon layer allows for forming a highly effective non-volatile layout with the semiconductor material with good electron mobility properties.
As to claim 11, Fukuzumi discloses the semiconductor device of claim 1 (paragraphs above),
Fukuzumi does not disclose wherein the memory sting comprises a NAND string.
Nonetheless, Park discloses a memory string that is formed as a NAND memory string (figs 1-2, [0064]) and wherein a single crystalline silicon layer is used as the silicon layer in the memory device ([0133]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the memory string of Fukuzumi as a NAND memory string with a single crystalline silicon layer as taught by Park since the NAND memory string with single crystalline silicon layer allows for forming a highly effective non-volatile layout with the semiconductor material with good electron mobility properties.
As to claim 12, Fukuzumi in view of Park disclose the semiconductor device of claim 11 (paragraphs above),
Park further discloses wherein the NAND string comprises:
a semiconductor channel (fig 3A, 156) extending vertically through the stacked structure (132);
a tunneling layer (154) between the stacked structure (132) and the semiconductor channel (156); and
a storage layer ([0081]) between the tunneling layer (154) and the stacked structure (132).
As to claim 18, Fukuzumi discloses the method of claim 17 (paragraphs above),
wherein forming the second dielectric layer on the second side of the stacked structure comprises thinning the initial semiconductor layer to a semiconductor layer (fig 7, substrate W1 is thinned by removing layer 10; [0092]); and
the semiconductor layer (BG) is located between the second side (top side) of the stacked structure (100) and the second dielectric layer (45).
Fukuzumi does not disclose forming the second dielectric layer on the semiconductor layer.
Nonetheless, Park discloses forming a second dielectric layer (fig 3C, 226) to cover the conductor layers (216).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the second dielectric layer of Park on the conductive layer of Fukuzumi such that further electrical interconnection layers can be formed.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzumi in view of Watanabe et al. (US Pub. No. 2019/0157324 A1), hereafter referred to as Watanabe.
As to claim 20, Fukuzumi discloses the method of claim 13 (paragraphs above),
Fukuzumi does not disclose wherein the bonding comprises at least one of a thermal treatment and a plasma treatment.
Nonetheless Watanabe discloses a bonding process of two substrate (fig 5C, 20 and 30) that similarly joins interlayer dielectric layers (32/24) and conductor layers (37/26) using a thermal treatment ([0083]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to using thermal treatment of Watanabe to join the conductor and dielectric layers of Fukuzumi since this will form secure and long lasting connection between substrates.
Allowable Subject Matter
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest further comprising forming a through contact extending through the semiconductor layer and connected with the conductor structures and the peripheral circuit, as recited in claim 19 and including the limitations of the independent claim and intervening claims.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2017/0221863A1 and US Patent No. 9,929,050B2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 1/6/2026