DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 6/12/2026 has been entered.
Response to Arguments
Applicant's arguments regarding the amended claims filed on May 7, 2026, have been fully considered but remain unpersuasive. While the Chen reference illustrates perfectly vertical sidewalls, it is well established in the art that some finite slope is expected and routine. Furthermore, conventional processing and patterning techniques inherently yield the claimed shape.
Both Lin and Saigal demonstrate that the opening used to form the conductive via can initially feature sloped sidewalls. This inherently results in a sloped via profile, meaning the vertical sidewall over the via physically overlaps the dielectric layer along the vertical axis. Because the newly recited geometry is simply the result of standard patterning processes and yields no unexpected results or benefits, it is rendered obvious by the cited prior art.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Chen et al. (US 20110193232 A1) in view of Saigal et al. (US 6426282 B1).
PNG
media_image1.png
716
708
media_image1.png
Greyscale
CLAIM 1 Lin et al. discloses a electronic package, comprising: a semiconductor die 12/10;
a conductive landing pad 113 (Chen et al. figs. 3&6 & 13) on the semiconductor die (Chen et al. Fig. 1 & 11);
PNG
media_image2.png
238
420
media_image2.png
Greyscale
PNG
media_image3.png
284
424
media_image3.png
Greyscale
an insulating film 117 over the semiconductor die (Fig. 1), the insulating film 117 along a side and over a top of the conductive landing pad 113 but not along a bottom of the conductive landing pad, (Chen et al. Fig. 4)) and,
PNG
media_image4.png
376
448
media_image4.png
Greyscale
the insulating film 117 having an opening 119 over at least a portion of the conductive landing pad 113;
a conductive via 129a on a first portion of the conductive landing pad 113, the conductive via 129a in the opening 119 of the insulating film 117, the conductive via 129a comprising copper [¶26 – “…. the conductive pillar 129 may include an electrically conductive material such as copper or copper alloy…..”, and the conductive via having an uppermost surface (Chen et al. Fig. 6- i.e. dotted line, or top surface of 129b);
a dielectric layer 123 on the insulating film 117, the dielectric layer on a second portion of the conductive landing pad, the dielectric layer in the opening of the insulating film, the dielectric layer laterally adjacent to and in direct physical contact with the conductive via, and the dielectric layer having an uppermost surface (Chen et al. Fig. 6) and a bottom most surface,
PNG
media_image5.png
716
708
media_image5.png
Greyscale
the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad .
PNG
media_image6.png
438
624
media_image6.png
Greyscale
Further regarding, “wherein the conductive via is vertically overlapping with and in direct contact with a portion of the dielectric layer in the opening of the insulating film along a vertical axis and below an uppermost surface of the dielectric layer”, while subjectively supported by the Applicant’s figure, the scope of this limitation is understood to be simply describing the negative slope of the conductive via’s sidewall. It would be considered an obvious modification to a PHOSITA to allow for the via to have a negative slope (e.g. upper portion of via wider than lower portion) such that, “wherein the conductive via is vertically overlapping with and in direct contact with a portion of the dielectric layer in the opening of the insulating film along a vertical axis and below an uppermost surface of the dielectric layer,” as such configuration was known and used by a PHOSIA.
As shown in Figure 3, Saigal depicts a structure analogous to the claimed invention. Specifically, Saigal discloses a dielectric layer 308 disposed within an opening of an insulating layer 306 that contacts a landing pad (e.g., pad 106/304). Conductive via 310 is formed within this opening and contacts dielectric layer 308. When forming this structure, the slope of the sidewalls of the conductive via 310 is dictated by the profile of the original opening formed in the insulating layer 306. Depending on the specific patterning and etching processes employed, this opening inherently exhibits a tapered or sloped profile. The subsequently deposited dielectric layer 308 conforms to this sloped profile, which is then transferred to the conductive via 310 filling the opening. Saigal thus demonstrates that it was well-known in the art to form conductive vias within openings having tapered sidewalls, thereby resulting in a conductive via with a negative slope that meets the structural limitations of the claim.
PNG
media_image7.png
290
416
media_image7.png
Greyscale
It would have been obvious to a person of ordinary skill in the art (POSITA) at the time of the invention to modify the insulating layer opening of Chen to incorporate the sloped or tapered sidewalls taught by Saigal. A POSITA would have been motivated to utilize sloped sidewalls to improve step coverage during subsequent material deposition (such as the dielectric layer and via metallization) and to prevent voids or defects in the via fill, which are known technical benefits of tapered via profiles.
Implementing Saigal’s tapered sidewall profile in Chen's insulating layer would predictably result in Chen's conductive via having a sloped profile, thereby causing a portion of the via to overlap with the dielectric layer along a vertical axis. This modification represents nothing more than the predictable application of a known technique (tapering sidewall openings for improved step coverage, as taught by Saigal) to a known device ready for improvement (Chen) to yield predictable results. Therefore, the claimed invention is obvious under 35 U.S.C. § 103. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 417 (2007) (holding that "looking to items in the prior art which demonstrate the high degree of predictability in the art" can support a finding of obviousness).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-5 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lin et al. (US 9219016 B2) in view of Chen et al. (US 20110193232 A1) in view of Saigal et al. (US 6426282 B1).
PNG
media_image8.png
466
810
media_image8.png
Greyscale
CLAIM 1 Lin et al. discloses a electronic package, comprising: a semiconductor die 12/10;
a conductive landing pad 28 on the semiconductor die 12/10;
an insulating film 114 over the semiconductor die, the insulating film along a side and over a top of the conductive landing pad but not along a bottom of the conductive landing pad, (The insulating layer is shown to have dotted line. This dotted line in the figure is understood to be a interface between the identified insulating film and another insulating film which is below the pad. Note that the original disclosure of the application does not provide explicit support for no insulating material below and contact a bottom surface of the pad. The only support for the limitation is found in the figure showing a insulating film on the top surface and side surface. The support and understanding of the claim simply means that this film is on the claimed surfaces and not on the bottom. Lin et al. which forms the device structure in a conventional build up process, provides a structurally analogous insulating film over a portion of the top surface and covering the side. This insulating film does not continue to be on the bottom surface.) and,
the insulating film (not labeled) having an opening over at least a portion of the conductive landing pad;
a conductive via 34 on a first portion of the conductive landing pad 28, the conductive via 34 in the opening of the insulating film, the conductive via comprising copper, and the conductive via having an uppermost surface (Fig. 1);
a dielectric layer 30 on the insulating film (Fig. 1), the dielectric layer on a second portion of the conductive landing pad, the dielectric layer in the opening of the insulating film, the dielectric layer laterally adjacent to and in contact with the conductive via, and wherein the conductive via is vertically overlapping with and in direct contact with a portion of the dielectric layer in the opening of the insulating film along a vertical axis and below an uppermost surface of the dielectric layer (Fig. 1 – The conductive via of Lin has a negative slope profile, thus the sidewall of conductive via overlaps dielectric layer 30A withing the opening.).
Regarding the conductive via comprising copper and in direct physical contact with the insulating film, this feature would have been an obvious variant to one of ordinary skill in the art (POSITA) at the time of the invention.
The UBM layer [32] in Lin is a well-known, optional component that primarily serves secondary functions such as promoting adhesion or preventing diffusion. It would have been obvious to a POSITA to omit this optional layer if its specific function was not desired for a particular application. By omitting the UBM layer [32], the copper-containing pillar [34] would naturally be in direct physical contact with the dielectric layer [30], thereby meeting the applicant’s claimed feature of a "first dielectric layer laterally adjacent to and in direct contact with the copper of the conductive via." Therefore, the claimed invention is merely an obvious modification of the prior art.
The Examiner directs the applicant to Chen et al., particularly paragraphs 26 and figures 1-6, for a teaching of the optional nature of UBM layers and their known function. Lin et al. teaches the analogous structure, and the claimed invention simply involves omitting the UBM layer as taught by Chen et al. The POSITA was aware that copper metallization was capable of being formed in direct physical contact with a dielectric, thus not requiring further intervening layers for electrical contact.
This analysis aligns with the principle discussed in MPEP § 2144.04(II)(A), which states that omission of an element and its function is obvious if the function of the element is not desired.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lin et al. with a copper pillar in direct physical contact with the dielectric layer as taught by Chen et al., since simple substitution of one known element for another (omitting the UBM layer) to obtain predictable results (direct electrical contact without the secondary benefits of adhesion/diffusion barriers) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
Further regarding, “the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad”, while subjectively supported by the Applicant’s figure, the scope of this limitation is not fully understood. Alternative to the interpretation as applied above, it would be considered an obvious modification to a PHOSITA to allow for the thickness of the insulation layer to be thicker than that of the landing pad such that when the dielectric layer is formed thereover and within the opening, “the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad,” as such configuration was known and used by a PHOSIA.
Saigal Fig. 3 depicts a structure analogous to the cited prior art. Dielectric layer 308 contacts via 310 and is within an opening of insulating layer 306, contacting landing pad 106. As the dielectric layer 308 extends outwardly from the pad 304, its bottommost surface which contacts the landing pad and upper surface of the insulation layer may be described as being above the uppermost surface of the landing pad. As shown below, the bottommost surface remains above the uppermost surface of the landing pad as it extends outwardly.
PNG
media_image7.png
290
416
media_image7.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the insulating layer of Lin and Chen with a thicker non conformal insulation layer, since applying a known technique to a known device ready for improvement (i.e. greater dielectric thickness over the substrate) to yield predictable results (increased isolation, protection, etc.) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Claim 2-5 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lin et al. (US 9219016 B2) in view of Chen et al. (US 20110193232 A1) in view of Saigal et al. (US 6426282 B1) in view of Hsu et al. (US 20110278716 A1) and/or Belanger et al. (US 20100193949 A1).
CLAIM 2. Lin et al. in view of Chen et al. in view of Saigal et al. disclose a electronic package of claim 1, wherein uppermost surface of the dielectric layer is co-planar with the uppermost surface of the conductive via (Fig. 1). Note: The device of Lin comprises a conductive line and via of Lin. A via region of the conductive material effectively ends at the claimed location, as such this location is effectively coplanar. Further note, to make integral or separable is considered a obvious variant in the art (see MPEP 2144.04). This interpretation is based upon the only provided figure (5G0 by the applicant’s that depicts all recited limitation. It is noted that the conductive line is depicted in the same integral manner as shown by Lin.
As suggested in Fig. 6 Chen, the top surface of 129A is coplanar with the top surface of dielectric 123, implying the claimed structural relation ship.
None the less, as shown in Hsu, the conductive line portion of Lin is known to be capable of being removed through planarization should one desire the via to be a conductive bump or pillar structure. Belanger et al. fig. 1B additionally demonstrates planarized pillar via structure over a pad.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the via shape of Lin with the planarized surface shape as demonstrated in Hso and Belanger, since applying a known technique to a known device ready for improvement to yield predictable results is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 3. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger disclose a electronic package of claim 1, wherein the conductive via and the conductive landing pad form a bumpless interface (Lin Fig. 1 & Chen Fig. 6).
CLAIM 4. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger disclose a electronic package of claim 1, wherein the conductive via has tapered sidewalls (Lin et al. Fig. 1).
CLAIM 5. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger disclose a electronic package of claim 1, wherein the insulating film is a passivating film (Lin Fig. 1 & Chen Fig. 6 - This limitation does not provide any further distinction. Passivating film as best understood from the written description is a function of a insulating/dialectic film.).
Claim 6-12 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger et al. in view of Chou et al. (US 20070205520 A1).
CLAIM 6. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger disclose a electronic package of claim 1, however is silent upon wherein the insulating film is photo-sensitive . At the time of the invention it was known in the art to select photo-sensitive dielectric/insulating materials to form the analogous layers. Photosensitive
layers may be used to pattern and remain as dielectric/insulating layers thereby reducing steps and cost by simplifying production. For support see Chow et al., which effectively form a substantially similar device structure. The analogous dielectric layer 39 of Chou et al. is disclosed to be capable of being formed of a photo sensitive material for ease of patterning, see paragraph 75 of Chou et al.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to select a photosensitive dielectric, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
CLAIM 7. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a electronic package, comprising: a semiconductor die; a conductive landing pad on the semiconductor die, the conductive landing pad having a top surface having an inner region within a perimeter region; an insulating film over the semiconductor die, the insulating film along a side and over a top of the conductive landing pad but not along a bottom of the conductive landing pad and, the insulating film on the perimeter region of the top surface of the conductive landing pad but not on the inner region of the top surface of the conductive landing pad; a conductive via on a first portion of the inner region of the top surface of the conductive landing pad, the conductive via comprising copper,; a dielectric layer on the insulating film, the dielectric layer on a second portion of the inner region of the top surface of the conductive landing pad, the first portion of the inner region of the top surface of the conductive pad within the second portion of the inner region of the top surface of the conductive pad, the dielectric layer laterally adjacent to and in contact with the conductive via, and the dielectric layer having an uppermost surface (Lin Fig. 1 & Chen Fig. 6– See regarding claim 1) and wherein the conductive via is vertically overlapping with and in direct contact with a portion of the dielectric layer in the opening of the insulating film along a vertical axis and below an uppermost surface of the dielectric layer (Fig. 1 – The conductive via of Lin has a negative slope profile, thus the sidewall of conductive via overlaps dielectric layer 30A withing the opening.).
Regarding the conductive via comprising copper and in direct physical contact with the insulating film, this feature would have been an obvious variant to one of ordinary skill in the art (POSITA) at the time of the invention.
The UBM layer [32] in Lin is a well-known, optional component that primarily serves secondary functions such as promoting adhesion or preventing diffusion. It would have been obvious to a POSITA to omit this optional layer if its specific function was not desired for a particular application. By omitting the UBM layer [32], the copper-containing pillar [34] would naturally be in direct physical contact with the dielectric layer [30], thereby meeting the applicant’s claimed feature of a "first dielectric layer laterally adjacent to and in direct contact with the copper of the conductive via." Therefore, the claimed invention is merely an obvious modification of the prior art.
The Examiner directs the applicant to Chen et al., particularly paragraphs 26 and figures 1-6, for a teaching of the optional nature of UBM layers and their known function. Lin et al. teaches the analogous structure, and the claimed invention simply involves omitting the UBM layer as taught by Chen et al. The POSITA was aware that copper metallization was capable of being formed in direct physical contact with a dielectric, thus not requiring further intervening layers for electrical contact.
This analysis aligns with the principle discussed in MPEP § 2144.04(II)(A), which states that omission of an element and its function is obvious if the function of the element is not desired.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lin et al. with a copper pillar in direct physical contact with the dielectric layer as taught by Chen et al., since simple substitution of one known element for another (omitting the UBM layer) to obtain predictable results (direct electrical contact without the secondary benefits of adhesion/diffusion barriers) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
Further regarding, “the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad”, while subjectively supported by the Applicant’s figure, the scope of this limitation is not fully understood. Alternative to the interpretation as applied above, it would be considered an obvious modification to a PHOSITA to allow for the thickness of the insulation layer to be thicker than that of the landing pad such that when the dielectric layer is formed thereover and within the opening, “the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad,” as such configuration was known and used by a PHOSIA.
Saigal Fig. 3 depicts a structure analogous to the cited prior art. Dielectric layer 308 contacts via 310 and is within an opening of insulating layer 306, contacting landing pad 106. As the dielectric layer 308 extends outwardly from the pad 304, its bottommost surface which contacts the landing pad and upper surface of the insulation layer may be described as being above the uppermost surface of the landing pad. As shown below, the bottommost surface remains above the uppermost surface of the landing pad as it extends outwardly.
PNG
media_image7.png
290
416
media_image7.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the insulating layer of Lin and Chen with a thicker non conformal insulation layer, since applying a known technique to a known device ready for improvement (i.e. greater dielectric thickness over the substrate) to yield predictable results (increased isolation, protection, etc.) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
CLAIM 8. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a electronic package of claim 7, wherein uppermost surface of the dielectric layer is co-planar with the uppermost surface of the conductive via (Lin et al. fig. 1 – See regarding claim 2
CLAIM 9. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a electronic package of claim 7, wherein the conductive via and the conductive landing pad forma bumpless interface (Lin Fig. 1 & Chen Fig. 6).
CLAIM 10. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a electronic package of claim 7, wherein the conductive via has tapered sidewalls (Lin fig. 1).
CLAIM 11. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a electronic package of claim 7, wherein the insulating film is a passivating film (Lin Fig. 1 & Chen Fig. 6– This limitation is not understood to provide any further distinction from the insulating layer.).
CLAIM 12. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a electronic package of claim 7, however is silent upon wherein the insulating film is photo-sensitive . At the time of the invention it was known in the art to select photo-sensitive dielectric/insulating materials to form the analogous layers. Photosensitive
layers may be used to pattern and remain as dielectric/insulating layers thereby reducing steps and cost by simplifying production. For support see Chow et al., which effectively form a substantially similar device structure. The analogous dielectric layer 39 of Chou et al. is disclosed to be capable of being formed of a photo sensitive material for ease of patterning, see paragraph 75 of Chou et al.
It would have been obvious to one having ordinary skill in the art at the time the invention was made to select a photosensitive dielectric, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim 13-20 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Lin et al in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. in supporting view of Cheah et al. (US 20110140268 A1)
CLAIM 13-20. Lin et al. in view of Chen et al. in view of Saigal et al. in view of Hsu in view of Belanger in view of Chou et al. discloses a computer system, comprising: a system bus (Chou ¶101 – semiconductor packages such as shown in Lin are known to have a bus.); and an electronic package coupled to the system bus, the electronic package comprising: a semiconductor die (Lin fig. 1); a conductive landing pad on the semiconductor die (Lin fig. 1); an insulating film over the semiconductor die the insulating film along a side and over a top of the conductive landing pad but not along a bottom of the conductive landing pad, (The insulating layer is shown to have dotted line. This dotted line in the figure is understood to be a interface between the identified insulating film and another insulating film which is below the pad. Note that the original disclosure of the application does not provide explicit support for no insulating material below and contact a bottom surface of the pad. The only support for the limitation is found in the figure showing a insulating film on the top surface and side surface. The support and understanding of the claim simply means that this film is on the claimed surfaces and not on the bottom. Lin et al. which forms the device structure in a conventional build up process, provides a structurally analogous insulating film over a portion of the top surface and covering the side. This insulating film does not continue to be on the bottom surface.) (Lin fig. 1), the insulating film having an opening over at least a portion of the conductive landing pad(Lin fig. 1); a conductive via on a first portion of the conductive landing pad, the conductive via in the opening of the insulating film,(Lin fig. 1); a dielectric layer on the insulating film, the dielectric layer on a second portion of the conductive landing pad, the dielectric layer in the opening of the insulating film, the dielectric layer laterally adjacent to and in contact with the conductive via 34 [lower portion located within the dielectric/insulating layers opening], and the dielectric layer having an uppermost surface (Lin fig. 1) and wherein the conductive via is vertically overlapping with and in direct contact with a portion of the dielectric layer in the opening of the insulating film along a vertical axis and below an uppermost surface of the dielectric layer (Fig. 1 – The conductive via of Lin has a negative slope profile, thus the sidewall of conductive via overlaps dielectric layer 30A withing the opening.).
It is further noted the claimed feature of a “bus” and the further features of a processor, display, memory, camera, and/or a digital sound recorder are all generically known components that are part of a chip/die package that would have landing pads and conductive pillars. These are all notoriously well known in the art and do not add any non-obvious patentable distinction. All electronic components will be expected to be coupled to the system bus in some manner, as a buss is what distributes power, and in a electronic device, the device components require power to operate.
Per Cheah et al. discloses the conventional knowledge of a chip/die package combination of a system bus in combination with a “processor”, “memory”, “digital sound recorder”, “camera”, and/or “display” that will be coupled to the system bus (¶74).
Note regarding claim 20, “voice recognition device” provides not structural distinction, as at best it is understood as software, thus would simply be some form of processor, memory and sound recording element., as such would be structurally analogous to the “digital sound recorder”.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Regarding the conductive via comprising copper and in direct physical contact with the insulating film, this feature would have been an obvious variant to one of ordinary skill in the art (POSITA) at the time of the invention.
The UBM layer [32] in Lin is a well-known, optional component that primarily serves secondary functions such as promoting adhesion or preventing diffusion. It would have been obvious to a POSITA to omit this optional layer if its specific function was not desired for a particular application. By omitting the UBM layer [32], the copper-containing pillar [34] would naturally be in direct physical contact with the dielectric layer [30], thereby meeting the applicant’s claimed feature of a "first dielectric layer laterally adjacent to and in direct contact with the copper of the conductive via." Therefore, the claimed invention is merely an obvious modification of the prior art.
The Examiner directs the applicant to Chen et al., particularly paragraphs 26 and figures 1-6, for a teaching of the optional nature of UBM layers and their known function. Lin et al. teaches the analogous structure, and the claimed invention simply involves omitting the UBM layer as taught by Chen et al. The POSITA was aware that copper metallization was capable of being formed in direct physical contact with a dielectric, thus not requiring further intervening layers for electrical contact.
This analysis aligns with the principle discussed in MPEP § 2144.04(II)(A), which states that omission of an element and its function is obvious if the function of the element is not desired.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Lin et al. with a copper pillar in direct physical contact with the dielectric layer as taught by Chen et al., since simple substitution of one known element for another (omitting the UBM layer) to obtain predictable results (direct electrical contact without the secondary benefits of adhesion/diffusion barriers) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385).
Further regarding, “the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad”, while subjectively supported by the Applicant’s figure, the scope of this limitation is not fully understood. Alternative to the interpretation as applied above, it would be considered an obvious modification to a PHOSITA to allow for the thickness of the insulation layer to be thicker than that of the landing pad such that when the dielectric layer is formed thereover and within the opening, “the bottommost surface of the dielectric layer above an uppermost surface of the conductive landing pad,” as such configuration was known and used by a PHOSIA.
Saigal Fig. 3 depicts a structure analogous to the cited prior art. Dielectric layer 308 contacts via 310 and is within an opening of insulating layer 306, contacting landing pad 106. As the dielectric layer 308 extends outwardly from the pad 304, its bottommost surface which contacts the landing pad and upper surface of the insulation layer may be described as being above the uppermost surface of the landing pad. As shown below, the bottommost surface remains above the uppermost surface of the landing pad as it extends outwardly.
PNG
media_image7.png
290
416
media_image7.png
Greyscale
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the insulating layer of Lin and Chen with a thicker non conformal insulation layer, since applying a known technique to a known device ready for improvement (i.e. greater dielectric thickness over the substrate) to yield predictable results (increased isolation, protection, etc.) is considered obvious to one of ordinary skill in the art (KSR International Co. v. Teleflex Inc., 550 U.S.-, 82 USPQ2d 1385).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JARRETT J. STARK
Primary Examiner
Art Unit 2822
2/23/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
Prosecution Insights