DETAILED ACTION
The Amendment filed July 14, 2025 and the information disclosure statement (IDS) filed April 14, 2025 have been entered. Claims 1-24 are pending. Claim 1 is independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 14, 2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-16 and 20-24 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sumbul et al. (US 2019/0043560) in view of Noel et al. (US 2019/0189198).
Regarding independent claim 1, Sumbul et al. teach a circuit, comprising:
a memory array (see e.g., FIG. 1A) including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each memory cell storing a bit of weight data for an in-memory computation operation (e.g., para. 0021: … compute-in-memory circuitry enables …);
wherein the memory is divided into a plurality of sub-arrays (e.g., FIG. 2: PARTITION[0-3]) of memory cells, each sub- array including at least one row of said plural rows and said plural columns;
a local bit line (LBL) for each column of the sub-array;
computation circuitry coupling each memory cell in the column of the sub-array to the local bit line for each column of the sub-array, said computation circuitry configured to logically combine a bit of feature data for the in-memory computation operation with the stored bit of weight data to generate a logical output on the local bit line (see e.g., FIG. 2 and accompanying disclosure, e.g., para. 0050: … an example of a compute-in memory circuit that performs …);
a plurality of global bit lines (GBL);
wherein a plurality of local bit lines are capacitively (e.g., para. 0075: Charge-sharing the BLBs on the GBL …with the pre-condition that LBL and GBL capacitances are known.1) coupled for charge sharing to each global bit line (e.g., para. 0044-0045, 0050: … a global charge-sharing CIM circuit …);
a word line drive circuit for each row having an output connected to drive the word line of the row (see e.g., FIG. 2 and accompanying disclosure);
a row controller circuit coupled to the word line drive circuits and configured to simultaneously actuate only one word line per sub-array during said in-memory computation operation (see e.g., FIG. 2 and accompanying disclosure, e.g., para. 0050: … which can access multiple rows simultaneously per subarray); and
a column processing circuit that senses analog signals on the global bit lines generated in response to said charge sharing, converts the analog signals to digital signals, performs digital signal processing calculations on the digital signals and generates a decision output for the in-memory computation operation (see e.g., FIG. 2 and accompanying disclosure, e.g., para. 0044: … a CIM circuit, a sense amplifier (not shown) couple to the bitcell converts the local bitline voltage to a full-swing …, i.e., local bitline voltage (which is an analog small signal) to full-swing (which is a logical “0” or “1”), in other words, it can be interpreted ADC).
Sumbul et al’ simultaneously actuate one word line per sub-array during said in-memory computation operation (see e.g., FIG. 2 and accompanying disclosure, e.g., para. 0050: … which can access multiple rows simultaneously per subarray) does not specifically define amended “only” one word line per sub-array.
However, actuating only one word line per sub-array in a multi-array memory circuit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Noel et al. teach in FIG. 3 and accompanying disclosure, e.g., para. 0092: … two bits stored in two cells of a same column … or in a cell … of array A1 and in a cell … of array A2 … simultaneously actives …
Sumbul and Noel are analogous art because they both are directed to SRAM memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Sumbul with the specified features of Noel because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Noel et al. to the teaching of Sumbul et al. such that a memory, as taught by Sumbul et al., utilizes activating one word line per sub-array, as taught by Noel et al., for the purpose of enhancing memory read operation.
Regarding claim 2, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach each column of the memory array has an associated global bit line, and wherein the plurality of local bit lines that are coupled for charge sharing with each global bit line comprise local bit lines in a corresponding column of the plurality of sub-arrays (see e.g., FIG. 2 and accompanying disclosure, e.g., para. 0044-0045, 0050: … a global charge-sharing CIM circuit …).
Regarding claims 3-4, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 2.
Sumbul et al. further teach wherein said feature data is applied to each row of memory cells having an actuated word line; where a logic state of a word line signal on the actuated word line provides said bit of feature data (see e.g., para. 0039: … inputs X and weights W in memory, i.e., feature data “X” compared to weights “W”).
Regarding claim 5, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 3.
Sumbul et al. further teach wherein a precharge voltage level on each local bit line in the sub-array provides said bit of feature data (e.g., para 0053: … multiple BLs can be precharged ...; further it is an inherent characteristic in a memory system).
Regarding claim 6, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 3.
Sumbul et al. further teach wherein a voltage level of a word line signal on the actuated word line provides said bit of feature data (see e.g., FIG. 5 and e.g., para. 0039: … inputs X and weights W in memory, i.e., feature data “X” compared to weights “W”).
Regarding claim 7, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach each sub-array has an associated global bit line, and wherein the plurality of local bit lines that are coupled for charge sharing with each global bit line comprise local bit lines in the sub-array (e.g. FIG. 2 and accompanying disclosure).
Regarding claim 8, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 7.
Sumbul et al. further teach wherein each column of the memory array has an associated feature data line selectively connected to the local bit lines in corresponding columns of the plurality of sub-arrays, and wherein said feature data is applied to the feature data lines (see e.g., FIG. 5 and e.g., para. 0039: … inputs X and weights W in memory, i.e., feature data “X” compared to weights “W”).
Regarding claim 9, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 8.
Sumbul et al. further teach a switch configured to selectively connect each local bit line to the associated feature data line (see e.g., FIG. 2 and accompanying disclosure), and wherein said switch is selectively actuated to precharge each local bit line to a voltage level of the bit of feature data (e.g., para 0053: … multiple BLs can be precharged ...; further it is an inherent characteristic in a memory system).
Regarding claim 10, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach a charge sharing circuit comprising a cc connected between each local bit line of said plurality of local bit lines and the global bit line (see e.g., FIG. 2 and accompanying disclosure, e.g., para. 0044-0045, 0050: … a global charge-sharing CIM circuit …).
Regarding claim 11, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach a first capacitance associated each local bit line of said plurality of local bit lines; a second capacitance associated with the global bit line (e.g., para. 0038: … BLPs … CBLPs … capacitances are …; further para. 0075: … LBL and GBL capacitances are known, i.e., the claimed local bit line and global bit line capacitances are known technology).
Regarding claims 12-15, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 11.
Sumbul et al. do not explicitly disclose wherein the first capacitance comprises a parasitic capacitance; wherein the second capacitance comprises a parasitic capacitance; wherein the first capacitance comprises a device capacitance; and wherein the second capacitance comprises a device capacitance.
However, Sumbul et al. disclose in e.g., para. 0075 that LBL and GBL capacitances are known technology.
Further, the Office takes OFFICIAL NOTICE that a well-known technology for a type of static random access memory for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize static random access memory used as configuration random access memory in local and global bit line capacitances are parasitic and/or device capacitances because these conventional technology are well established in the art of the memory devices.
Regarding claim 16, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach a first precharge circuit for each local bit line, said first precharge circuit configured to precharge the local bit line to a first precharge voltage level; and a second precharge circuit for each global bit line, said second precharge circuit configured to precharge the global bit line to a second precharge voltage level (e.g., para. 0037: system 100 precharges …, para. 0055: … LBSs and GBLs are precharged …; further, pre-charge circuit in a memory system is a well-known technology).
Regarding claim 20, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach each word line drive circuit is powered from a positive supply voltage level, and further comprising a voltage modulation circuit configured to modulate said positive supply voltage level to have a selected one of a plurality voltage levels dependent on the multi-bit feature data (see e.g., FIG. 5 and accompanying disclosure).
Regarding claim 21, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach said weight data comprises multi-bit weight data stored in plural memory cells of multiple columns of the memory array, and wherein said column processing circuit is coupled to corresponding multiple global bit lines and configured to process multiple analog signals on the multiple global bit lines (e.g., para. 0037: Weighing the rows …; para. 0039: … inputs X and weights W …).
Regarding claim 22, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 21.
Sumbul et al. further teach said column processing circuit comprises a multiplexing circuit configured to sequentially select analog signals from the multiple global bit lines for processing (e.g., para. 0068: … multiple rows in sequence …; para. 0084: … access to sequences of columns to access …).
Regarding claim 23, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 21.
Sumbul et al. further teach said column processing circuit comprises a weighting circuit configured to perform a weighted charge sharing for the analog signal of each one of the multiple global bit lines to produce a weighted signal and then perform a combination charge sharing of the weighted signals (e.g., para. 0084: … access to sequences of columns to access …).
Regarding claim 24, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 1.
Sumbul et al. further teach the memory cells are static random access memory (SRAM) cells (FIGS. 1B-C).
Claims 17-19 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Sumbul et al. (US 2019/0043560) in view of Noel et al. (US 2019/0189198), further in view of Zheng et al. (US 2014/0269091).
Regarding claim 17, Sumbul et al. and Noel et al., as combined, teach the limitations of claim 16.
Sumbul et al. further teach said feature data comprises multi-bit feature data, and further comprising a voltage modulation circuit (see e.g., FIG. 5 and accompanying disclosure).
Sumbul et al. are silent with respect to voltage modulation circuit configured to modulate said first precharge voltage level to have a selected one of a plurality voltage levels dependent on the multi-bit feature data.
Zheng et al. teach the deficiencies in e.g., para. 0014: … precharge circuitry … the second voltage level … dependent on a data value stored with that activated memory cell …
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Zheng et al. to the teaching of Sumbul et al. and Noel et al., as combined, such that a memory, as taught by Sumbul et al. and Noel et al., utilizes a pre-charging circuitry, as taught by Zheng et al., for the purpose of performing fast access of memory operations.
Regarding claims 18-19, Sumbul et al. Noel et al., and Zheng et al., as combined, teach the limitations of claim 17.
Sumbul et al. further teach wherein said selected one of the plurality voltage levels is applied as the first precharge voltage level for all first precharge circuits within a given sub-array (e.g., para. 0071: … system performs current summing per subarray on the precharged LBLs …, i.e., precharged sub-array base); and wherein said selected one of the plurality voltage levels is applied as the first precharge voltage level for all first precharge circuits within a given row of the sub-array (e.g., para. 0055: … LBSs and GBLs are precharged …, i.e., precharing level applied withing a given row and column of the array).
Response to Arguments
Applicant’s Amendment filed 07/14/2025, with respect to the rejection(s) of claims 1-24 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUNG IL CHO whose telephone number is (571)270-0137. The examiner can normally be reached on M-Th, 7:30AM-5PM; Every other F, 7:30AM-4PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached on 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825
1 Further, cc (coupling cap) between local bit line and global bit line is an inherent characteristic in a memory device. See, for example, Lee et al. (US 2009/0109768), FIG. 3.
Prosecution Insights