DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of species A, fig. 1, claims 1-20, in the reply filed on 1/20/26 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4-12, 14-17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeng et al. US Publication No. 2020/0152603 A1 (from the IDS).
Jeng anticipates:
1. A semiconductor package, comprising (see fig. 10):
a first redistribution wiring layer (20) having first redistribution wirings (22);
a first semiconductor chip (30 right) disposed on the first redistribution wiring layer, the first semiconductor chip being arranged such that a front surface on which first chip pads are formed faces the first redistribution wiring layer (20), and the first semiconductor chip (30 right) having a first thickness;
a second semiconductor chip (30 left) disposed on the first redistribution wiring layer (20), the second semiconductor chip (30 left) being spaced apart from the first semiconductor chip (30 right) and arranged such that a front surface on which second chip pads are formed faces the first redistribution wiring layer (20), the second semiconductor chip (30 left) having a second thickness that is less than the first thickness;
a sealing member (40) covering the first semiconductor chip and the second semiconductor chip on the first redistribution wiring layer;
a plurality of conductive vias (36C or 84) provided in the sealing member (40) and electrically connected to the first redistribution wirings (20);
a second redistribution wiring layer (70) disposed on the sealing member and having second redistribution wirings (72) electrically connected to the plurality of conductive vias (36C or 84); and
at least one third semiconductor chip (50) disposed on the second redistribution wiring layer (70) and electrically connected to the second redistribution wirings (72). See Jeng at para. [0001] – [0071], figs. 1-10.
2. The semiconductor package as claimed in claim 1, wherein the sealing member (40) exposes an upper portion of the first semiconductor chip (30 right), fig. 10.
4. The semiconductor package as claimed in claim 1, wherein the second redistribution wiring layer (70) overlaps the second semiconductor chip (30 left), fig. 10.
5. The semiconductor package to claim 1, further comprising:
at least one interposer connector (36) disposed on the first redistribution wiring layer (20) and adjacent to the second semiconductor chip (30 left),
wherein the at least one interposer connector comprises:
a connector substrate (e.g. substrate of 36) having a first surface facing the first redistribution wiring layer and a second surface opposite to the first surface;
the plurality of conductive vias (36C) penetrating the connector substrate; and
conductive bumps (32 in fig. 2E) provided on the first surface and electrically connected to the plurality of conductive vias (36C), and
wherein the conductive bumps (32) are electrically connected to the first redistribution wirings (22), fig. 10.
6. The semiconductor package as claimed in claim 5, wherein the at least one interposer connector further comprises:
first connector pads (e.g. In fig. 2E, electrodes directly below 36C) respectively disposed on end portions of the plurality of conductive vias (36C) on the first surface of the connector substrate and to which the conductive bumps (32 in fig. 2E) are bonded; and
second connector pads (e.g. In fig. 2E, electrodes directly above 36C) respectively disposed on other end portions of the plurality of conductive vias (36C) on the second surface of the connector substrate, fig. 10.
7. The semiconductor package as claimed in claim 6, wherein the second connector pads (e.g. In fig. 2E, electrodes directly above 36C) are electrically connected to the second redistribution wirings (72), fig. 10.
8. The semiconductor package as claimed in claim 6, wherein the connector substrate (36) includes a silicon material, para. [0031].
9. The semiconductor package as claimed in claim 1, wherein the first semiconductor chip (30 right) is mounted on the first redistribution wiring layer (20) via conductive bumps (32 in fig. 2E) that are disposed on the first chip pads, and the second semiconductor chip (30 left) is mounted on the first redistribution wiring layer (20) via conductive bumps (32 in fig. 2E) that are disposed on the second chip pads, fig. 10.
10. The semiconductor package as claimed in claim 1, wherein the first and second semiconductor chips include a logic chip, and the at least one third semiconductor chip includes a memory chip, para. [0030], [0035].
Regarding claim 11:
Jeng teaches the limitations as applied to claims 1, 5 and 6 above.
Jeng further teaches the added limitations:
the first redistribution wiring layer (20) including a first chip mounting region (e.g. region of 30 right), a second chip mounting region (e.g. region of 30 left) and a connector region (e.g. region of 36) spaced apart from each other,
…
at least one interposer connector (36) disposed on the connector region on the first redistribution wiring layer (20).
Regarding claim 12:
Jeng teaches the limitations as applied to claim 2 above.
Regarding claim 14:
Jeng teaches the limitations as applied to claim 4 above.
Regarding claim 15:
Jeng teaches the limitations as applied to claim 8 above.
Regarding claim 16:
Jeng teaches the limitations as applied to claim 9 above.
Regarding claim 17:
Jeng teaches the limitations as applied to claim 10 above.
Jeng further teaches:
19. The semiconductor package as claimed in claim 11, further comprising: external connection members (64) disposed on an outer surface of the first redistribution wiring layer (20) and electrically connected to the first redistribution wirings (22), fig. 10.
Regarding claim 20:
Jeng teaches the limitations as applied to claims 1, 5, 6 and 11 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 4-12 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al., US Publication No. 2022/0352138 A1 in view of Lee et al., US Publication No. 2022/0310577 A1.
Choi teaches:
1. A semiconductor package, comprising (see fig. 12B):
a first redistribution wiring layer (500) having first redistribution wirings (510/520/530);
a first semiconductor die (700) disposed on the first redistribution wiring layer, the first semiconductor chip being arranged such that a front surface on which first chip pads (721) are formed faces the first redistribution wiring layer (500), and the first semiconductor die having a first thickness;
a second semiconductor chip (210 bottom right) disposed on the first redistribution wiring layer, the second semiconductor chip being spaced apart from the first semiconductor die and arranged such that a front surface on which second chip pads (215) are formed faces the first redistribution wiring layer (500), the second semiconductor chip (210 bottom right) having a second thickness that is less than the first thickness (e.g. of 700);
a sealing member (400) covering the first semiconductor die and the second semiconductor chip on the first redistribution wiring layer;
a plurality of conductive vias (217) provided in the sealing member and electrically connected to the first redistribution wirings (500);
a second redistribution wiring layer (300) disposed on the sealing member and having second redistribution wirings (e.g. 310, 320, or wiring lines para. [0040]) electrically connected to the plurality of conductive vias; and
at least one third semiconductor chip (100) disposed on the second redistribution wiring layer (300) and electrically connected to the second redistribution wirings. See Choi at para. [0001] – [0142], figs. 1-13.
Regarding claim 1:
Choi teaches a first semiconductor die (700) comprising a silicon wafer, para. [0116].
Choi does not expressly teach a first semiconductor chip.
Choi’s first semiconductor die (700) is disposed between two memory stacks (200) in fig. 12B.
In an analogous art, Lee teaches (see fig. 4B) a semiconductor chip (610) disposed between two memory stacks (60), para. [0103 – [0106]. The semiconductor chip (610) may be a system-on-chip (SOC), a central processing unit (CPU) or a graphic processing unit (GPU), para. [0052].
It would have been obvious to a person of ordinary skill in the art to modify Choi’s first semiconductor die to be a semiconductor chip in order to integrate a system-on-chip (SOC), a central processing unit (CPU) or a graphic processing unit (GPU) into the package.
Choi further teaches:
2. The semiconductor package as claimed in claim 1, wherein the sealing member (400) exposes an upper portion of the first semiconductor chip (700) (e.g. The exposed portion of 700 is covered by underfill 471 in fig. 12B.)
4. The semiconductor package as claimed in claim 1, wherein the second redistribution wiring layer (300) overlaps the second semiconductor chip (210 bottom right), fig. 12B.
5. The semiconductor package to claim 1, further comprising:
at least one interposer connector (e.g. 220 on right stack directly above 210 bottom right; or 220 on left stack) disposed on the first redistribution wiring layer (500) and adjacent to the second semiconductor chip (e.g. 210 bottom right),
wherein the at least one interposer connector comprises:
a connector substrate (e.g. 220 is a semiconductor chip) having a first surface (e.g. bottom surface) facing the first redistribution wiring layer and a second surface (e.g. top surface) opposite to the first surface;
the plurality of conductive vias (217) penetrating the connector substrate; and
conductive bumps (633) provided on the first surface and electrically connected to the plurality of conductive vias (217), and
wherein the conductive bumps (633) are electrically connected to the first redistribution wirings (510/520/530), fig. 12B.
6. The semiconductor package as claimed in claim 5, wherein the at least one interposer connector (e.g. 220 on right stack directly above 210 bottom right; or 220 on left stack) further comprises:
first connector pads (e.g. rectangular pads directly below 217) respectively disposed on end portions of the plurality of conductive vias (217) on the first surface of the connector substrate and to which the conductive bumps (633) are bonded; and
second connector pads (e.g. rectangular pads directly above 217) respectively disposed on other end portions of the plurality of conductive vias (217) on the second surface of the connector substrate, fig. 12B.
7. The semiconductor package as claimed in claim 6, wherein the second connector pads (e.g. rectangular pads directly above 217) are electrically connected to the second redistribution wirings (e.g. 310, 320, or wiring lines para. [0040]), fig. 12B.
8. The semiconductor package as claimed in claim 6, wherein the connector substrate includes a silicon material (e.g. 220 is a semiconductor chip so it is inherent or obvious that the connector substrate includes silicon material, para. [0048])
9. The semiconductor package as claimed in claim 1, wherein the first semiconductor chip (700) is mounted on the first redistribution wiring layer (500) via conductive bumps (723) that are disposed on the first chip pads (721), and the second semiconductor chip (210 bottom right) is mounted on the first redistribution wiring layer (500) via conductive bumps (643) that are disposed on the second chip pads (215), fig. 12B.
Regarding claim 10:
Choi further teaches:
wherein the second semiconductor chip includes a logic chip (210 bottom right), and the at least one third semiconductor chip includes a memory chip (e.g. upper 220 or 230), para. [0049].
Choi does not expressly teach the first semiconductor chip (700) includes a logic chip.
Lee teaches the first semiconductor chip (610) may be a logic chip, para. [0052].
Regarding claim 11:
Choi and Lee teach the limitations as applied to claims 1, 5 and 6 above. In claim 5, the interposer connector is interpreted to be element (220 on left stack) in fig. 12B.
Choi teaches the added limitations:
the first redistribution wiring layer (500) including a first chip mounting region (e.g. region of 700), a second chip mounting region (e.g. region of 200 right) and a connector region (e.g. region of 200 left) spaced apart from each other,
…
at least one interposer connector (e.g. 220 on left stack) disposed on the connector region on the first redistribution wiring layer (500)
Regarding claim 12:
Choi and Lee teach the limitations as applied to claim 2 above.
Regarding claim 14:
Choi and Lee teach the limitations as applied to claim 4 above.
Regarding claim 15:
Choi and Lee teach the limitations as applied to claim 8 above.
Regarding claim 16:
Choi and Lee teach the limitations as applied to claim 9 above.
Regarding claim 17:
Choi and Lee teach the limitations as applied to claim 10 above.
Choi further teaches:
18. The semiconductor package as claimed in claim 11, wherein, when viewed from a plan view, the connector substrate (e.g. of 220 on left stack) has a rectangular shape having a short side in a first direction and a long side in a second direction orthogonal to the first direction, fig. 12A.
19. The semiconductor package as claimed in claim 11, further comprising: external connection members (600) disposed on an outer surface of the first redistribution wiring layer (500) and electrically connected to the first redistribution wirings, fig. 12B.
Regarding claim 20:
Choi and Lee teach the limitations as applied to claims 1, 5, 6 and 11 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Choi with the teachings of Lee because forming the first semiconductor die to be a semiconductor chip enables the integration of a system-on-chip (SOC), a central processing unit (CPU) or a graphic processing unit (GPU) into the package. See Lee at para. [0052].
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jeng, as applied to claim 1 above, in further view of Yoo et al., US Publication No. 2022/0013474 A1.
Regarding claim 3:
Jeng teaches all the limitations of claims 1 and 11 above, but is silent:
wherein the first thickness is in a range of 0.5 mm to 1.0 mm, and the second thickness is in a range of 0.1 mm to 0.5 mm.
Jeng's first semiconductor chip is a system-on-chip (e.g. logic chip), para. [0030].
In analogous art, Yoo teaches:
(see figs. 2 and 4) “For example, the thicknesses of the logic chips 31 and 32…may be about 0.65 to 0.72 mm”, para. [0050].
Yoo teaches a thickness that overlaps the claimed range.
One of ordinary skill in the art modifying Jeng with Yoo to form the first chip to have a thickness between 0.65 to 0.72 mm would find it obvious to form the second chip to have a thickness in a range of 0.1 mm to 0.5 mm because Jeng teaches the second chip is thinner than the first chip in fig. 10.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Jeng with the teachings of Yoo because a thickness in a range of 0.5 mm to 1.0 mm is an recognized thicknesses for a logic chip in a semiconductor package. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Lee, as applied to claims 1 and 11 above, in further view of Yoo et al., US Publication No. 2022/0013474 A1.
Regarding claims 3 and 13:
Choi and Lee teach all the limitations of claims 1 and 11 above, but are silent:
wherein the first thickness is in a range of 0.5 mm to 1.0 mm, and the second thickness is in a range of 0.1 mm to 0.5 mm.
Lee teaches the first semiconductor chip is a logic chip and the second semiconductor chip is a memory chip of a HBM stack, para. [0052], [0055].
In analogous art, Yoo teaches:
(see figs. 2 and 4) “For example, the thicknesses of the logic chips 31 and 32 and the memory stacks 41 to 48 may be about 0.65 to 0.72 mm”, para. [0050].
The logic chip is about 0.65 to 0.72 mm, which is within the claimed range.
The memory chip is one of four chips in fig. 4. Thus, one memory chip is approximately ¼ of the stack height = 0.65/4 to 0.72/4 mm = 0.16-0.18 mm, which is within the claimed range.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Choi with the teachings of Yoo because a first thickness in a range of 0.5 mm to 1.0 mm, and the second thickness in a range of 0.1 mm to 0.5 mm are art recognized thicknesses for a logic chip and memory chip, respectively, in a semiconductor package. See MPEP § 2144.07, Art Recognized Suitability for an Intended Purpose.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michele Fan whose telephone number is 571-270-7401. The examiner can normally be reached on M-F from 7:30 am to 4 pm.
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/Michele Fan/
Primary Examiner, Art Unit 2818
22 April 2026
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