DETAILED ACTION
This Office action responds to the application filed on 03/15/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-9, & 13-15 rejected under 35 U.S.C. 102(a)(2) as being anticipated by Moriyama (US 20190006300).
Regarding Claim 1, Moriyama (see, e.g., fig. 15, annotated fig. 15 #1) shows a semiconductor integrated circuit comprising:
a substrate SB (see, e.g., fig. 2, para.0061-0063) that is formed with a semiconductor;
a circuit element formation region C1-C4 (see, e.g., annotated fig. 1, para.0064) that is formed on the substrate,
and includes an element QL1 & QL2 (see, e.g., fig. 2, para.0061-0062) formed with a semiconductor;
a wiring line M4 & M5 that is drawn from the circuit element formation region (see, e.g., para.0060-0061) onto the substrate in a pad formation region (see, e.g., annotated fig. 1) around the circuit element formation region;
a first protective film IF1 that covers the circuit element formation region,
has a first opening OP2 formed in the pad formation region,
and is formed with an organic material (see, e.g., para.0072);
a bonding pad OPM that has a smaller area than the first opening in a planar view,
is formed on the wiring line on an inner side of the first opening,
and is connected to the wiring line (see, e.g., para.0040, para.0060);
and a second protective film IF2 that is in contact with the first protective film to cover the first protective film,
has an end portion extending toward a center of the first opening between the wiring line and the bonding pad at an edge portion of the bonding pad (see, e.g., annotated fig. 15 #1),
has a second opening OP3 that is formed on the inner side of the first opening
and has the end portion as an edge,
and is formed with an inorganic material (see, e.g., para.00072).
Regarding Claim 2, Moriyama (see, e.g., fig. 15, annotated fig. 15 #2, para.0040) shows the semiconductor integrated circuit according to claim 1,
wherein, in a region of the second opening,
the bonding pad is formed in contact with the wiring line.
Regarding Claim 3, Moriyama (see, e.g., fig. 15, annotated fig. 15 #2) shows the semiconductor integrated circuit according to claim 1,
wherein, in a region in which the end portion extends between the wiring line and the bonding pad,
the wiring line, the second protective film, and the bonding pad are stacked in this order from a side of the substrate.
Regarding Claim claim 1,
wherein the second protective film includes
the end portion,
a sidewall portion that is formed on a sidewall of the first opening of the first protective film
and continues from the end portion,
and an upper layer portion formed on the first protective film.
Regarding Claim 6, Moriyama (see, e.g., para.0070, para.0153) shows the semiconductor integrated circuit according to claim1,
wherein the wiring line is formed with metal,
and the bonding pad is formed with metal.
Regarding Claim 7, Moriyama (see, e.g., fig. 15, annotated fig. 15 #2) shows the semiconductor integrated circuit according to claim 2,
wherein, in a region in which the end portion extends between the wiring line and the bonding pad,
the wiring line, the second protective film, and the bonding pad are stacked in this order from a side of the substrate.
Regarding Claim 8, Moriyama (see, e.g., fig. 15, annotated fig. 15 #3) shows the semiconductor integrated circuit according to claim 2,
wherein the second protective film includes the
end portion,
a sidewall portion that is formed on a sidewall of the first opening of the first protective film
and continues from the end portion,
and an upper layer portion formed on the first protective film.
Regarding Claim 9, Moriyama (see, e.g., fig. 15, annotated fig. 15 #3) shows the semiconductor integrated circuit according to claim 3,
wherein the second protective film includes
the end portion,
a sidewall portion that is formed on a sidewall of the first opening of the first protective film
and continues from the end portion,
and an upper layer portion formed on the first protective film.
Regarding Claim 13, Moriyama (see, e.g., para.0070, para.0153) shows the semiconductor integrated circuit according to claim 2,
wherein the wiring line is formed with metal,
and the bonding pad is formed with metal.
Regarding Claim 14, Moriyama (see, e.g., para.0070, para.0153) shows the semiconductor integrated circuit according to claim 3,
wherein the wiring line is formed with metal,
and the bonding pad is formed with metal.
Regarding Claim 15, Moriyama (see, e.g., para.0070, para.0153) shows the semiconductor integrated circuit according to claim 4,
wherein the wiring line is formed with metal,
and the bonding pad is formed with metal.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 10, 11, 12, & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Moriyama (US 20190006300) in view of Ichihara (US 20080090314).
Regarding Claim 5, Moriyama (see, e.g., para.0070, annotated fig. 15 #4) shows the semiconductor integrated circuit according to claim 1,
further comprising a film BM1 & BM2 that is formed between the bonding pad and the wiring line, and the first protective film,
Moriyama (see, e.g., para.0070) states said film, BM1 & BM2, can be a titanium nitride film or a laminated film including a titanium nitride film and a titanium film.
Moriyama, however, fails to show
the film being provided to enhance adhesion to each.
Although Moriyama does not explicitly state the film is provided to enhance adhesion to each, Ichihara (see, e.g., para.0098) teaches that a film of titanium or titanium nitride would improve adhesion.
Therefore, it would be obvious to one of ordinary skill in the art to interpret the film, BM1 & BM2, of Moriyama as being provided to enhance adhesion to each.
Regarding Claim 10, Moriyama (see, e.g., para.0070, annotated fig. 15 #4) shows the semiconductor integrated circuit according to claim 2,
further comprising a film BM1 & BM2 that is formed between the bonding pad and the wiring line, and the first protective film,
Moriyama (see, e.g., para.0070) states said film, BM1 & BM2, can be a titanium nitride film or a laminated film including a titanium nitride film and a titanium film.
Moriyama, however, fails to show
the film being provided to enhance adhesion to each.
Although Moriyama does not explicitly state the film is provided to enhance adhesion to each, Ichihara (see, e.g., para.0098) teaches that a film of titanium or titanium nitride would improve adhesion.
Therefore, it would be obvious to one of ordinary skill in the art to interpret the film, BM1 & BM2, of Moriyama as being provided to enhance adhesion to each.
Regarding Claim 11, Moriyama (see, e.g., para.0070, annotated fig. 15 #4) shows the semiconductor integrated circuit according to claim 3,
further comprising a film BM1 & BM2 that is formed between the bonding pad and the wiring line, and the first protective film,
Moriyama (see, e.g., para.0070) states said film, BM1 & BM2, can be a titanium nitride film or a laminated film including a titanium nitride film and a titanium film.
Moriyama, however, fails to show
the film being provided to enhance adhesion to each.
Although Moriyama does not explicitly state the film is provided to enhance adhesion to each, Ichihara (see, e.g., para.0098) teaches that a film of titanium or titanium nitride would improve adhesion.
Therefore, it would be obvious to one of ordinary skill in the art to interpret the film, BM1 & BM2, of Moriyama as being provided to enhance adhesion to each.
Regarding Claim 12, Moriyama (see, e.g., para.0070, annotated fig. 15 #4) shows the semiconductor integrated circuit according to claim 4,
further comprising a film BM1 & BM2 that is formed between the bonding pad and the wiring line, and the first protective film,
Moriyama (see, e.g., para.0070) states said film, BM1 & BM2, can be a titanium nitride film or a laminated film including a titanium nitride film and a titanium film.
Moriyama, however, fails to show
the film being provided to enhance adhesion to each.
Although Moriyama does not explicitly state the film is provided to enhance adhesion to each, Ichihara (see, e.g., para.0098) teaches that a film of titanium or titanium nitride would improve adhesion.
Therefore, it would be obvious to one of ordinary skill in the art to interpret the film, BM1 & BM2, of Moriyama as being provided to enhance adhesion to each.
Regarding Claim 16, Moriyama (see, e.g., para.0070, para.0153) shows the semiconductor integrated circuit according to claim 5,
wherein the wiring line is formed with metal,
and the bonding pad is formed with metal.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/F.R.D./ Examiner, Art Unit 2814
Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814