Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response Election/Restriction filed on 05/08/26.
Summary of claims
Claims 1-20 are pending.
Claims 1-20 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Paul Penzes (US Pub. 2010/0162184).
As to claims 1 the prior art teaches a layout design method for an integrated circuit, comprising:
generating a primary layout based on a circuit diagram netlist using a primary standard cell library (see fig 1 element 110), the circuit diagram netlist comprising a first standard cell and a second standard cell, and the primary standard cell library comprising a first standard layout of the first standard cell and a second standard layout of the second standard cell (see fig 1-3 paragraph 0043-0050);
and consolidating the first standard layout and the second standard layout based on a splicing relationship between the first standard layout and the second standard layout in the primary layout to optimize the consolidated layout comprising: adjusting a layout of the first standard layout of the first standard cell in a primary standard cell library (see fig 1 element 110) to obtain a first layout, and using the second standard layout as a second layout or adjusting a layout of the second standard layout of the second standard cell in the primary standard cell library to obtain the second layout such that à sum of areas of the first layout and the second layout is less than a sum of areas of the first standard layout and the second standard layout (see fig 1-4 paragraph 0048-0057).
As to claim 2 the prior art teaches wherein the second standard layout is a standard layout in the primary layout that has a frequency of splicing with the first standard layout higher than a reference value (see fig 2-4 paragraph 0051-0058).
As to claim 3 the prior art teaches wherein a layout area of at least one standard layout of the first standard layout or the second standard layout is greater than a theoretical minimum of the layout area of the at least one standard layout, and the consolidating the first standard layout and the second standard layout to optimize the consolidated layout comprises: reducing an area of the consolidated layout of the first standard layout and the second standard layout (see fig 2-5 paragraph 0055-0060).
As to claim 4, the prior art teaches wherein the consolidating the first standard layout and the second standard layout to optimize the consolidated layout comprises:
identifying a potentially optimizable region in the at least one standard layout of the first standard layout or the second standard layout (see fig 3-5 paragraph 0057-0061);
determining, based on the splicing relationship between the first standard layout and the second standard layout, whether the first standard layout and the second standard layout have restrictions on the potentially optimizable region (see fig 3-5 paragraph 0059-0063);
determining, in response to determining that the first standard layout and the second standard layout have no restrictions on the potentially optimizable region, that the potentially optimizable region is an optimizable region (see fig 4-6 paragraph 0061-0066);
and adjusting a layout of the at least one standard layout comprising the optimizable region to reduce an area of the optimizable region (see fig 4-6 paragraph 0064-0068).
As to claims 5 the prior art teaches wherein the at least one standard layout is implemented based on MOS transistors, and the consolidating the first standard layout and the second standard layout to optimize the consolidated layout comprises: transferring connection relationships on redundant gate polysilicon in the at least one standard layout to other appropriate gate polysilicon and removing the redundant gate polysilicon (see fig 3-6 paragraph 0058-0067).
As to claim 6 the prior art teaches wherein the consolidating the first standard layout and the second standard layout to optimize a consolidated layout comprises: reducing lengths of interconnections in subsequent routing (see fig 4-7 paragraph 0065-0070).
As to claim 7 the prior art teaches wherein the reducing the lengths of interconnections in subsequent routing further comprises: adjusting interconnections between the first standard layout and the second standard layout that is obtained through automatic routing and that is at a different metal layer from interconnections in the first standard layout or the second standard layout to a same metal layer as the interconnections in the first standard layout or the second standard layout (see fig 4-7 paragraph 0068-0073).
As to claim 8, the prior art teaches further comprising:
splitting the optimized consolidated layout into a first optimized layout for the first standard cell and a second optimized layout for the second standard cell (see fig 1-5 paragraph 0045-0053);
and adding the first optimized layout and the second optimized layout to the primary standard cell library to form an optimized standard cell library (see fig 1-5 paragraph 0053-0060).
As to claims 9 the prior art teaches wherein the first optimized layout comprises information for indicating that the first optimized layout needs to be used in combination with the second optimized layout in a layout design, and the second optimized layout comprises information for indicating that the second optimized layout needs to be used in combination with the first optimized layout in a layout design (see fig 1-6 paragraph 0059-0068).
As to claim 10 the prior art teaches wherein the first standard layout, the second standard layout, and the optimized consolidated layout meet process design rules (see fig 1-4 paragraph 0044-0049).
As to claim 11 the prior art teaches an integrated circuit, comprising:
a first standard cell (see fig 1-3 paragraph 0043-0047);
and a second standard cell, wherein a first layout of the first standard cell and a second layout of the second standard cell have a splicing relationship, the first layout is obtained by adjusting a layout of a first standard layout of the first standard cell in a primary standard cell library, and the second layout is a second standard layout of the second standard cell in the primary standard cell library or is obtained by adjusting a layout of the second standard layout of the second standard cell in the primary standard cell library, such that a sum of areas of the first layout and the second layout is less than a sum of areas of the first standard layout and the second standard layout (see fig 1-4 paragraph 0048-0057).
As to claim 12 and 16, the prior art teaches wherein the first standard cell and the second standard cell are implemented based on CMOS transistors, the first layout is obtained by transferring connection relationships on redundant gate polysilicon in the first standard layout to other appropriate gate polysilicon in the first standard layout and removing the redundant gate polysilicon in the first standard layout, and the second layout is the second standard layout or is obtained by transferring connection relationships on redundant gate polysilicon in the second standard layout to other appropriate gate polysilicon in the second standard layout and removing the redundant gate polysilicon in the second standard layout (see fig 4-9 paragraph 0070-0075).
As to claims 13 and 17 the prior art teaches wherein the first standard cell and the second standard cell are two-input Exclusive-OR gates (XOR2s), and the integrated circuit is an adder circuit (see fig 1-3 paragraph 0045-0052).
As to claim 14 the prior art teaches a operation chip, comprising at least one integrated circuit comprising:
a first standard cell (see fig 1-3 paragraph 0043-0047);
and a second standard cell, wherein a first layout of the first standard cell and a second layout of the second standard cell have a splicing relationship, the first layout is obtained by adjusting a layout of a first standard layout of the first standard cell in a primary standard cell library, and the second layout is a second standard layout of the second standard cell in the primary standard cell library or is obtained by adjusting a layout of the second standard layout of the second standard cell in the primary standard cell library, such that a sum of areas of the first layout and the second layout is less than a sum of areas of the first standard layout and the second standard layout (see fig 1-4 paragraph 0048-0057).
As to claim 15 the prior art teaches A computing device, configured to execute an algorithm for mining virtual digital currency, the computer device comprising: at least one operation chip according to claim 14; a control chip; a power supply module; and a heat dissipater, wherein the control chip is coupled to the at least one operation chip and configured to control an operation of the at least one operation chip, the power supply module is configured to provide power to the at least one operation chip and/or the control chip, and the heat dissipater is configured to dissipate heat for the at least one operation chip, the control chip, and/or the power supply module (see fig 1-3 paragraph 0049-0059).
As to claim 18, the prior art teaches wherein the redundant gate polysilicon in the first standard layout and in the second standard layout is different from a dummy polysilicon used as an isolation boundary (see fig 3-7 paragraph 0063-0069).
As to claim 19, the prior art teaches further comprising: analyzing whether a splicing relationship exists among all standard layouts including the first standard layout and the second standard layout in the primary layout and computing statistics on frequencies of splicing between standard layouts (see fig 4-8 paragraph 0073-0078).
As to claim 20, the prior art teaches wherein the consolidating the first standard layout and the second standard layout is in response to determining the splicing relationship between the first standard layout and the second standard layout in the primary layout and determining that the second standard layout is a standard layout in the primary layout that has a frequency of splicing with the first standard layout higher than frequencies of splicing the first standard layout with standard layouts in the primary layout other than the first and second standard layouts (see fig 4-10 paragraph 0076-0080).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/BINH C TAT/Primary Examiner, Art Unit 2851
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