Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This is a response to the amendment filed on 03/06/26. The applicant argument regarding Joseph Hock is not persuasive; therefore, all the rejections based on Joseph Hock is retained and repeated for the following reasons.
Summary of claims
Claims 1-35 are pending.
Claims 1-35 are rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-35 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Joseph Hock (US Pub. 2019/0006858).
As to claims 1 the prior art teaches an ultracapacitor system comprising:
a plurality of ultracapacitor cells connected in series (see fig 3 paragraph 0041-0042; especially, Joseph Hock teaches a plurality of ultracapacitor cells connected in series (see fig 3 paragraph 0042);
a charger electrically connected to at least one of the plurality of ultracapacitor cells (see fig 2-4 paragraph 0042-0048; especially, Joseph Hock teaches a charger electrically connected to at least one of the plurality of ultracapacitor cells as fig 2-4 paragraph 0043-0047);
a plurality of balancing circuits, each balancing circuit being electronically switchable between an activated state in which a corresponding ultracapacitor cell of the plurality of ultracapacitor cells discharges through the balancing circuit and a deactivated state in which the corresponding ultracapacitor cell does not discharge through the balancing circuit (see fig 1-4 paragraph 0015-0025; especially, Joseph Hock teaches a plurality of balancing circuits, each balancing circuit being electronically switchable between an activated state in which a corresponding ultracapacitor cell of the plurality of ultracapacitor cells discharges through the balancing circuit and a deactivated state in which the corresponding ultracapacitor cell does not discharge through the balancing circuit as fig 1-4 paragraph 0016-0024);
and controller circuitry in communication with the charger and the plurality of balancing circuits (see fig 1-3 paragraph 0024-0031; especially, Joseph Hock teaches controller circuitry in communication with the charger and the plurality of balancing circuits as fig 1-3 paragraph 0025-0030).
As to claim 2 the prior art teaches wherein the controller circuitry is configured to control, during a charging operation, a charge current applied by the charger to charge the plurality of ultracapacitor cells (see fig 1-2 paragraph 0024-0026).
As to claim 3 and 25 the prior art teaches wherein the controller circuitry is configured to control the charge current to maintain a constant-current charging mode during at least a portion of the charging operation (see fig 1-2 paragraph 0031-0035).
As to claim 4 and 26 the prior art teaches wherein the controller circuitry is configured to control the charge current to maintain a constant-power charging mode during at least a portion of the charging operation (see fig 1-2 paragraph 0047-0050).
As to claims 5 and 27 the prior art teaches wherein, in the constant-power charging mode, the controller circuitry controls the charge current such that an output power of the charger is maintained at a charge power selected based at least in part on a detected temperature associated with the ultracapacitor system (see fig 1-2 paragraph 0025-0029).
As to claim 6 and 28 the prior art teaches wherein the controller circuitry is configured to derate the charge power using a power derating factor when the detected temperature exceeds a predetermined power derating temperature (see fig 1-2 paragraph 0014-0017).
As to claim 7 the prior art teaches wherein the controller circuitry is further configured to control the charge current based at least in part on an end-of-charge voltage of the plurality of ultracapacitor cells (see fig 1-2 paragraph 0015-0019)
As to claim 8, the prior art teaches wherein the controller circuitry is further configured to determine the end-of-charge voltage based at least in part on a detected temperature associated with the ultracapacitor system (see fig 1-2 paragraph 0017-0021).
As to claim 9 the prior art teaches wherein the controller circuitry is configured to individually activate each of the plurality of balancing circuits (see fig 1-3 paragraph 0040-0043).
As to claim 10 the prior art teaches wherein the controller circuitry is configured to activate one or more of the balancing circuits to lower an overall voltage of the plurality of ultracapacitor cells based at least in part on a detected temperature exceeding a threshold (see fig 2-4 paragraph 0042-0046).
As to claims 11 the prior art teaches wherein the controller circuitry is configured to individually activate one or more of the plurality of balancing circuits to implement a cell balancing operation (see fig 2-4 paragraph 0047-0053).
As to claim 12 and 29 the prior art teaches wherein the cell balancing operation is based at least in part on a lowest cell voltage of a plurality of cell voltages corresponding to the individual ultracapacitor cells (see fig 1-2 paragraph 0023-0027).
As to claim 13 and 30 the prior art teaches wherein, during the cell balancing operation, the controller circuitry activates the balancing circuits corresponding to each of the ultracapacitor cells having a cell voltage greater than the lowest cell voltage (see fig 2-3 paragraph 0034-0037).
As to claim 14 and 31 the prior art teaches wherein, during the cell balancing operation, the controller circuitry activates the balancing circuits corresponding to each of the ultracapacitor cells having a cell voltage exceeding the lowest cell voltage by at least a predetermined voltage difference (see fig 2-3 paragraph 0038-0041).
As to claims 15 and 32 the prior art teaches wherein the cell balancing operation is based at least in part on an average cell voltage of a plurality of cell voltages corresponding to the individual ultracapacitor cells (see fig 1-2 paragraph 0016-0020).
As to claim 16 and 33 the prior art teaches wherein, during the cell balancing operation, the controller circuitry activates the balancing circuits corresponding to each of the ultracapacitor cells having a cell voltage greater than the average cell voltage (see fig 2-3 paragraph 0027-0029).
As to claim 17 and 34 the prior art teaches wherein the controller circuitry implements the cell balancing operation in response to a determination that an overall voltage of the plurality of ultracapacitor cells is greater than or equal to a predetermined balancer start voltage (see fig 2-3 paragraph 0029-0032).
As to claim 18, the prior art teaches controller circuitry is configured to implement the cell balancing operation while the charger is charging the plurality of ultracapacitor cells (see fig 3-4 paragraph 0035-0037).
As to claim 19 and 35 the prior art teaches wherein the controller circuitry implements the cell balancing operation only once per charge cycle of the ultracapacitor system (see fig 3-4 paragraph 0036-0040).
As to claim 20 the prior art teaches wherein each balancing circuit comprises a balancing transistor connected in parallel with the corresponding ultracapacitor cell, the balancing transistor having a gate connected to an output of the controller circuitry (see fig 3-4 paragraph 0039-0043).
As to claims 21 the prior art teaches wherein each balancing circuit further comprises a discharge resistor connected in series with the balancing transistor (see fig 1-2 paragraph 0041-0044).
As to claim 22 the prior art teaches further comprising a redundant transistor electrically connected between the charger and the plurality of ultracapacitor cells, the redundant transistor controllable by the controller circuitry to prevent overcharging of the plurality of ultracapacitor cells (see fig 3-4 paragraph 0044-0046).
As to claim 23 the prior art teaches wherein the controller circuitry is configured to transmit monitoring data to a remote computing device via wired or wireless connection for system monitoring (see fig 3-4 paragraph 0049-0052).
As to claim 24 the prior art teaches a computer-implemented method of charging an array of ultracapacitor cells, the method comprising: under control of controller circuitry of an ultracapacitor system:
controlling a charger in communication with the controller circuitry to supply a charge current to a plurality of ultracapacitor cells (see fig 3 paragraph 0041-0042);
and activating at least one of a plurality of balancing circuits, while the charger supplies the charge current, to implement a cell balancing operation, wherein each of the plurality of balancing circuits is electronically switchable between an activated state in which a corresponding ultracapacitor cell of the plurality of ultracapacitor cells discharges through the balancing circuit and a deactivated state in which the corresponding ultracapacitor cell does not discharge through the balancing circuit (see fig 1-4 paragraph 0015-0030).
Remarks
Applicant’s response and remarks filed on 03/06/26 have been carefully reviewed. Applicant’s arguments have been fully considered but they are not persuasive. Key argument and their response related to the claims are listed as below:
Applicant contends that Joseph Hock do not describe “a plurality of ultracapacitor cells connected in series” probes as claimed, Examiner respectfully disagrees. The prior art (Joseph Hock U.S Pub. 2019/0006858) do teach a plurality of ultracapacitor cells connected in series (see fig 3 paragraph 0041-0042; especially, Joseph Hock teaches a plurality of ultracapacitor cells connected in series (see fig 3 paragraph 0042).
Applicant contends that Joseph Hock do not describe “a charger electrically connected to at least one of the plurality of ultracapacitor cells” probes as claimed, Examiner respectfully disagrees. The prior art (Joseph Hock Pub. 2019/0006858) do teach a charger electrically connected to at least one of the plurality of ultracapacitor cells (see fig 2-4 paragraph 0042-0048; especially, Joseph Hock teaches a charger electrically connected to at least one of the plurality of ultracapacitor cells as fig 2-4 paragraph 0043-0047).
Applicant contends that Joseph Hock do not describe “a plurality of balancing circuits, each balancing circuit being electronically switchable between an activated state in which a corresponding ultracapacitor cell of the plurality of ultracapacitor cells discharges through the balancing circuit and a deactivated state in which the corresponding ultracapacitor cell does not discharge through the balancing circuit” probes as claimed, Examiner respectfully disagrees. The prior art (Joseph Hock U.S Pub. 2019/0006858) do teach a plurality of balancing circuits, each balancing circuit being electronically switchable between an activated state in which a corresponding ultracapacitor cell of the plurality of ultracapacitor cells discharges through the balancing circuit and a deactivated state in which the corresponding ultracapacitor cell does not discharge through the balancing circuit (see fig 1-4 paragraph 0015-0025; especially, Joseph Hock teaches a plurality of balancing circuits, each balancing circuit being electronically switchable between an activated state in which a corresponding ultracapacitor cell of the plurality of ultracapacitor cells discharges through the balancing circuit and a deactivated state in which the corresponding ultracapacitor cell does not discharge through the balancing circuit as fig 1-4 paragraph 0016-0024).
Applicant contends that Joseph Hock do not describe “controller circuitry in communication with the charger and the plurality of balancing circuits” probes as claimed, Examiner respectfully disagrees. The prior art (Joseph Hock U.S Pub. 2019/0006858) do teach controller circuitry in communication with the charger and the plurality of balancing circuits (see fig 1-3 paragraph 0024-0031; especially, Joseph Hock teaches controller circuitry in communication with the charger and the plurality of balancing circuits as fig 1-3 paragraph 0025-0030).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Conclusion
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/BINH C TAT/Primary Examiner, Art Unit 2851
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