Detailed Action
This office action is in response to the amendment filed on November 25th, 2025. Claims 1-8, 10-11, and 13-14 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed November 25th, 2025, have been fully considered but they are not persuasive.
Applicant argues (pgs. 5-6, “Remarks”) that the limitations of claim 9 are incorporated into independent claim 1.
However, examiner notes that the applicant has amended the claim to encompass a broader ranger of values for the leakage current than that originally claimed in claim 9. In this case, as seen below, amended Claim 1 is now rejected by the combination of Dortu and Ananthan.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant’s amendments have overcome the 35 U.S.C. 112(b) rejections of the previous office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Citations and/or reference characters corresponding to the prior art are provided in bold text. Non-bold Reference characters shown in parenthesis are part of the original claim.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 1, 3, 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Dortu et al. (U.S. 4,612,560; hereinafter Dortu) in view of Ananthan et al. (2014/0264239 A1; hereinafter Ananthan).
Regarding Claim 1, Dortu (fig. 1) teaches:
a normally off (Col. 1, Lines 63-65; operating in enhancement mode) MESFET device (see fig. 1) comprising a semiconductor layer (1) (Col. 3, Lines 20-23; 2),
a source contact (2) (Col. 3, Lines 23-25; 3),
a drain contact (3) (Col. 3, Lines 23-25; 4) and
a stacked gate contact (4) (Col. 3, Lines 30-35; 7, 8, 9), wherein the stacked gate contact (4) (7, 8, 9) comprises
a bottom metal layer (41) (7),
a top metal layer (43) (9) and
an insulating layer (42) (8) between the bottom (7) and top metal (9) layers, wherein
the source (2) (3), drain (3) (4) and stacked gate contacts (4) (7, 8, 9) are in contact with the semiconductor layer (1) (2), wherein the bottom metal layer (41) (7) and the semiconductor layer (1) (2) form a Schottky contact (Col. 3, Lines 32-33),
creating a depletion region (5) (Col. 1, Lines 28-30; depleted area) in the semiconductor layer (1) (2) below the bottom metal layer (41) (7), and wherein
extension of the depletion region (5) (depleted area) into the semiconductor layer (1) (2) is configured to be modulated by application of a voltage (Col. 1, Lines 28-30) to the top metal layer (43) (Col. 3, Lines 34-36), and wherein
a thickness of the insulating layer (42) is designed to limit leakage current between the bottom metal layer (41) and the top metal layer (43) in an on-state to less than 4000 A/cm2.
Dortu doesn’t explicitly teach that a thickness of the insulating layer (42) is designed to limit leakage current between the bottom metal layer (41) and the top metal layer (43) in an on-state to less than 4000 A/cm2. Dortu does mention that the gate bias voltage can be raised to 1.5 V without there being any gate leak (Col. 5, Lines 1-4).
However, Ananthan (fig. 4A) teaches a thickness of the insulating layer (42) ([0054], 420) is designed to limit leakage current ([0059], high band gap layer can be 5- 20 nm) between the bottom metal layer (41) ([0054], 450) and the top metal layer (43) ([0054], 410) in an on-state ([0059], half an operating voltage, e.g., about 1 and 2 V) to less than 4000 A/cm2 ([0059], limited to 1000 A/cm2). Ananthan also teaches that the high band gap layer can be optimized to achieve no tunneling current at low applied voltages ([0059]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Dortu to include the optimization of an insulating layer thickness of Ananthan to achieve no tunneling current at low applied voltages.
Regarding Claim 3, Dortu (fig. 1) teaches the normally off MESFET device of claim 1, wherein the semiconductor layer (1) (2) comprises a III-V semiconductor material (Col. 3, Lines 20-23; GaAs or InP).
Regarding Claim 8, Dortu (fig. 1) teaches the normally off MESFET device of claim 1, wherein the bottom metal layer (41) (7) is arranged to be electrically connected, preferably externally (Col. 5, Lines 20-22; 7 may be directly connected to for application of voltage).
Regarding Claim 10, Dortu (fig. 1) teaches the normally off MESFET device of claim 1, wherein the stacked gate contact (4) (7, 8, 9) is configured to have voltages of both polarities (Col. 4, Lines 65-69; Col. 5, Lines 1-4; see fig. 5) applied to the top metal layer (43) (9).
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Dortu and Ananthanas applied to Claim 1 and 3 above, and further in view of Ikeda et al. (2011/0220978 A1; hereinafter Ikeda).
Regarding Claim 2, Dortu doesn’t teach the normally off MESFET device of claim 1, wherein the semiconductor layer (1) comprises a first semiconductor sublayer (11) and a second semiconductor sublayer (12).
However, Ikeda (fig. 6) teaches the semiconductor layer (1) ([0026], 23, 25) comprises a first semiconductor sublayer (11) (23) and a second semiconductor sublayer (12) (25). Ikeda also teaches the two layer structure may form a HEMT and provide high-frequency performance and low on-resistance ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Dortu to include the two layer structure of Ikeda to provide high-frequency performance and low on-resistance.
Regarding Claim 4, Dortu doesn’t teach the normally off MESFET device of claim 3, wherein the semiconductor layer (1) forms a HEMT structure, wherein a first semiconductor sublayer (11) is a substrate layer and a second semiconductor sublayer (12) is a barrier layer, and wherein the first semiconductor sublayer (12) comprises a high electron mobility region.
However, Ikeda (fig. 6) teaches the semiconductor layer (1) ([0026], 23, 25) forms a HEMT ([0003]) structure, wherein a first semiconductor sublayer (11) is a substrate layer (25) and a second semiconductor sublayer (12) is a barrier layer (23), and wherein the first semiconductor sublayer (12) (25) comprises a high electron mobility region ([0027], 24). Ikeda also teaches the two layer structure may form a HEMT and provide high-frequency performance and low on-resistance ([0003]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Dortu to include HEMT structure of Ikeda to provide high-frequency performance and low on-resistance.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dortu and Ananthan as applied to Claim 1 above, and further in view of Thornton (U.S. 6,630,382 B1; hereinafter Thornton).
Regarding Claim 5, Dortu doesn’t explicitly teach the normally off MESFET device of claim 1, wherein the depletion region (5) in the semiconductor layer (1) is created along an entire thickness of the semiconductor layer (1).
However, Thornton (fig. 4) teaches the depletion region (5) (Col. 7, Lines 65-67; 216) in the semiconductor layer (1) (Col. 7, Lines 65-67; 206) is created along an entire thickness (Col. 8, Lines 11-20; W) of the semiconductor layer (1) (206). Thornton also teaches this closes current flow from drain to source when zero bias voltage is applied (Col. 8, Lines 1-2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Dortu to include the depletion region of Ikeda to close current flow from drain to source when zero bias voltage is applied.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Dortu and Ananthan as applied to Claim 1 above, and further in view of Brubaker et al. (2008/0106926 A1; hereinafter Brubaker).
Regarding Claim 6, Dortu doesn’t teach the normally off MESFET device of claim 1, wherein the insulating layer (42) comprises at least two sublayers of different materials.
However, Brubaker (fig. 6) teaches the insulating layer (42) ([0054], 382) comprises at least two sublayers of different materials ([0082], any of the layers may be formed of multiple sublayers). Brubaker also teaches that it is conventional in the art to form both conductive and insulating layers out of multiple sublayers, each comprising a different material ([0082]). One of ordinary skill in the art would have found it obvious to try and use multiple sublayers of different materials for the insulating layer and yielded the predictable results of a functional transistor.
Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to use multiple sublayers of different materials for the insulating layer since this limitation is one of a finite number of identified, predictable potential solutions. This is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Dortu and Ananthan as applied to Claim 1 above, and further in view of Machida et al. (2009/0206363 A1; hereinafter Machida).
Regarding Claim 7, Dortu doesn’t teach the normally off MESFET device of claim 1, wherein the top metal layer (43) comprises a first area (431) and a second area (432), wherein the first and second areas are electrically separated from each other, and wherein the extension of the depletion region (5) into the semiconductor layer (1) is configured to be modulated by application of a voltage to at least one of the first area (431) and the second area (432).
However, Machida (fig. 15) teaches the top metal layer (43) ([0135], 15, 16) comprises a first area (431) (15) and a second area (432) (16), wherein the first (15) and second areas (16) are electrically separated from each other (see fig. 15), and wherein the extension of the depletion region (5) ([0103], 15 and 16 may be in schottky contact with 12a and would thus form a depletion region) into the semiconductor layer (1) ([0103], 12a) is configured to be modulated by application of a voltage ([0011]) to at least one of the first area (431) (15) and the second area (432) (16). Machida also teaches that having two gates allows for individually controlling current flow between the electrodes ([0011]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the semiconductor device of Dortu to include the gate structure of Ikeda to allow for individually controlling current flow between the electrodes.
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Dortu and Ananthan as applied to Claim 1 above, and further in view of Kang et al. (2019/0020311 A1; hereinafter Kang).
Regarding Claim 13, Dortu (fig. 1) teaches an electrical circuit (Col. 5, Lines 50-51), comprising: a first normally-off MESFET device (see fig. 1) of claim 1, wherein the semiconductor layer (1) (2) comprises an n-type semiconductor (Col. 4, Lines 26-28); and a second normally-off MESFET device of claim 1, wherein the semiconductor layer (1') comprises a p-type semiconductor.
Dortu does not teach a second normally-off MESFET device of claim 1, wherein the semiconductor layer (1') comprises a p-type semiconductor.
However, Kang (fig. 2a) teaches an electrical circuit ([0049]), comprising: a first normally-off MESFET device ([0049], 202 may be a MESFET) of claim 1, wherein the semiconductor layer (1) ([0049], n-channel or p-channel) comprises an n-type semiconductor ([0049], 202 and 204 may form a CMOS, FET 202 may be n-channel), and a second normally-off MESFET device ([0049], 204 may be a MESFET) of claim 1, wherein the semiconductor layer (1') (n-channel or p-channel) comprises a p-type semiconductor ([0049], 202 and 204 may form a CMOS, FET 204 may be p-channel). Kang also teaches that this circuit exhibits a higher IIP3 ([0054]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the electrical circuit of Dortu to include the MESFET connection of Kang to form a circuit that exhibits a higher IIP3.
Regarding Claim 14, the combination of Dortu (fig. 1) and Kang (fig. 2a) teaches the electrical circuit of claim 13, wherein the drain contact (3) (Kang, [0050], D of 202) of the first normally-off MESFET device (Kang, 202) is electrically connected to the source contact (2') (Kang, [0050], S of 204) of the second normally-off MESFET device (Kang, 204), wherein the top metal layer (43) (Dortu, 9) of the first normally-off MESFET device (Kang, 202) and the top metal layer (43') (Dortu, 9) of the second normally-off MESFET device (Kang, 204) are electrically connected, and wherein the extension of the depletion region (5, 5') (Dortu, depleted area) into the semiconductor layer (1, 1') (Dortu, 2) in the first normally-off MESFET device (Kang, 202) and in the second normally-off MESFET devices (Kang, 204) is configured to be modulated by application of a voltage to one of the top metal layers (43, 43') (Dortu, 9).
Allowable Subject Matter
Claim 11 is allowed.
The following is an examiner’s statement of reasons for allowance. None of the references cited, either alone or in combination, teach or render obvious the limitations presented in amended Claim 11 wherein “a transistor area is defined as the area spanned between the source contact (2) and the drain contact (3), wherein the step of applying (103) a bottom metal layer (41) comprises extending the bottom metal layer (41) to a stacked gate area different from the transistor area, and wherein the insulating layer (42) is applied onto the bottom metal layer (41) in the stacked gate area”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 27, 2026
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