DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statements (IDS) submitted on March 17, 2023 and May 15, 2023 have been fully considered by the examiner.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the voltage generation element and predefined input signal of claim 19 must be shown or the feature canceled from the claim (see p. 4, l. 30 – p.5, l. 12 of the Specification). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Response to Amendment
4. A preliminary amendment was filed on April 13, 2023.
Claims 1-12 are canceled. Claims 13-24 are added.
The Specification is amended for apparent improved formatting and readability. No new matter has been entered.
Figures 1A-4 and 6 are amended for consistency with the Specification.
Claim Objections
5. Claims 21, 23, and 24 are objected to because of the following informalities.
Claim 21, line 47 recites “at least at least one matrix circuit.” Examiner believes this is a typographical error and should recite, “ at least one matrix circuit.”
Claim 23, lines 51-52 recites “at least at least one matrix circuit.” Examiner believes this is a typographical error and should recite, “ at least one matrix circuit.”
Claim 24, line 48 recites “at least at least one matrix circuit.” Examiner believes this is a typographical error and should recite, “ at least one matrix circuit.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 13-24 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 13 recites the limitation “the matrix circuit” in line 7. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “the at least one matrix circuit,” which finds antecedent basis in line 5.
Claim 13 recites the limitation “the applied voltage” in line 15. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “[[the]] an applied voltage.”
Claim 13 recites the limitation “those bit shifting units that are included in a weight range.” It is unclear what it means to be “included in a weight range.” For example, this could mean the shifter is in the path of a signal determined by the range of weights stored in the memory cells of the matrix, or it could mean the shifter is somehow related to scaling a result consistent with a mathematical range of the weights. For the purpose of this action, the aforementioned limitation shall be interpreted as the shifter is in the path of a signal determined by the range of weights stored in the memory cells of the matrix.
Claim 21 recites the limitation “the matrix circuit” in line 8. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “the at least one matrix circuit,” which finds antecedent basis in line 6.
Claim 21 recites the limitation “the applied voltage” in line 16. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “[[the]] an applied voltage.”
Claim 21 recites the limitation “the column lines of the memory cells of the bit section being connected to the analog-to-digital converter” in lines 27-29. There is insufficient antecedent basis for this limitation in the claim. Because it appears a particular instance of a bit section is in view (i.e., the one “being connected to” a particular instance of an analog-to-digital converter), for the purpose of this action, the aforementioned claim shall be interpreted as “[[the]] column lines of [[the]] memory cells of [[the]] a bit section being connected to [[the]] an analog-to-digital converter.”
Claim 21 recites the limitation “the bit sections included in the weight ranges assigned to the adder” in lines 50-51. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “[[the]] bit sections included in the weight ranges assigned to the adder.”
Claim 21 recites the limitation “for at least one of the input vectors” in step D. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “for at least one of the one or multiple input vectors,” which finds antecedent basis in claim 21, line 1 (and is consistent with dependent claim 22 returning to the verbiage, “one or multiple input vectors” in line 2). Claim 22 depends on claim 21.
Claim 21 recites the limitation “for the bits of the input elements of the input vector having the same value” in step D, sub-step b. It is unclear to what “having the same value” refers.
If the intent is “for the bits…having the same value,” then there is insufficient antecedent basis for “the input vector” and the aforementioned limitation may be interpreted as “for the bits of the input elements of the at least one of the one or multiple input vectors having the same value.”
If the intent is “…the input vector having the same value,” then there is lack of antecedent basis for “the input vector having the same value” and may be interpreted as “[[the]] an input vector having the same value.”
In either case, it is unclear what “having the same value” means (the same as what?).
For the purpose of this action, the aforementioned limitation shall be interpreted as “for the bits of the input elements of the at least one of the one or multiple input vectors having equal value.”
Claim 21 recites the limitation, “assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned” in step A.
There is insufficient antecedent basis for the limitation “the first weight vectors” in step A of the claim. Based on the nearest context, Examiner believes “the first weight vectors” may be intended to reference “predetermined first weight vectors, which finds antecedent basis in line 2 of the claim. For the purpose of this action, “the first weight vectors” shall be interpreted as “the predetermined first weight vectors” in this and subsequent instances of “the first weight vectors” in claims 21-22.
It is apparent to Examiner that “the weight vector to which the adder is assigned” refers to “each first weight vector” of the step because of the “adder” qualifier. However, it also appears from the limitations of step B that a distinction is being made between “first weight vector” and “weight vector."
Therefore, for the purpose of this action, the limitation, “assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned” in step A shall be interpreted as, “assigning an adder of the adders to each weight vector of the predetermined first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned.”
Based on this interpretation, Examiner believes the following interpretation of step B is appropriate:
“B) storing bits of the binary weight elements of the predetermined first weight vectors, for each weight vector, the bits of the binary weight elements of the weight vector being stored in the memory cells that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector, each of the bits of a weight element of the binary weight elements being stored in a row, bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range, and when a bit is stored in a memory cell, the memory cell being placed in the first memory state when the bit has the value 0, and the memory cell being placed in the second memory state when the bit has the value 1;”
However, it is unclear to Examiner how to reconcile “the bits of the binary weight elements of the weight vector being stored in the memory cells that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector” and “each of the bits of a weight element of the binary weight elements being stored in a row.” While each cell (bit) resides in a row and column, the former limitation appears to indicate bits of the binary weight elements are stored in a column direction, while the latter limitation appears to indicate bits of the binary weigh elements are stored in a row direction.
Claim 21 recites the limitation “bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range” in step B. The meaning of this limitation is unclear. It appears “this weight range” refers to “the same weight range,” but this seems to create a circular limitation in which bits stored in a weight range are being stored in the weight range that already store the bits. It is also possible “this weight range” refers to “a weight range” in line 4 of step B.
Examiner believes step B may be related to organization of weights in bit sections, but it is unclear how this is accomplished.
Claim 21 recites in step C, substep iii, the limitation, “the number of bits by which the binary value is to be shifted being predefined for each bit shifting unit, the predefined number of bits being determined as a sum of the value of the bits of the input elements, corresponding to which voltages are applied, and of the value of the bits of the weight elements that are stored in the bit section to which the bit shifting unit is connected via the analog-to-digital converter.” It is unclear how a number of bits can simultaneously be both “predefined” and calculated based on current conditions.
Claim 22 recites the limitation “for at least one of the input vectors” in step H. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “for at least one of the one or multiple input vectors,” which finds antecedent basis in claim 21, line 1.
Claim 23 recites the limitation “the matrix circuit” in line 8. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “the at least one matrix circuit,” which finds antecedent basis in line 5.
Claim 23 recites the limitation “the applied voltage” in line 16. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “[[the]] an applied voltage.”
Claim 23 recites the limitation “the column lines of the memory cells of the bit section being connected to the analog-to-digital converter” in lines 27-29. There is insufficient antecedent basis for this limitation in the claim. Because it appears a particular instance of a bit section is in view (i.e., the one “being connected to” a particular instance of an analog-to-digital converter), for the purpose of this action, the aforementioned claim shall be interpreted as “[[the]] column lines of [[the]] memory cells of [[the]] a bit section being connected to [[the]] an analog-to-digital converter.”
Claim 23 recites the limitation “the bit sections included in the weight ranges assigned to the adder” in line 51. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “[[the]] bit sections included in the weight ranges assigned to the adder.”
Claim 23 recites the limitation “for at least one of the input vectors” in step D. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “for at least one of the one or multiple input vectors,” which finds antecedent basis in claim 23, line 47.
Claim 23 recites the limitation, “assign an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned” in step A.
There is insufficient antecedent basis for the limitation “the first weight vectors” in step A of the claim. Based on the nearest context, Examiner believes “the first weight vectors” may be intended to reference “predetermined first weight vectors,” which finds antecedent basis in line 48 of the claim. For the purpose of this action, “the first weight vectors” shall be interpreted as “the predetermined first weight vectors” in this and subsequent instances of “the first weight vectors” in steps B and C of the claim.
It is apparent to Examiner that “the weight vector to which the adder is assigned” refers to “each first weight vector” of the step because of the “adder” qualifier. However, it also appears from the limitations of step B that a distinction is being made between “first weight vector” and “weight vector."
Therefore, for the purpose of this action, the limitation, “assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned” in step A shall be interpreted as, “assigning an adder of the adders to each weight vector of the predetermined first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned.”
Based on this interpretation, Examiner believes the following interpretation of step B is appropriate:
“B) storing bits of the binary weight elements of the predetermined first weight vectors, for each weight vector, the bits of the binary weight elements of the weight vector being stored in the memory cells that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector, each of the bits of a weight element of the binary weight elements being stored in a row, bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range, and when a bit is stored in a memory cell, the memory cell being placed in the first memory state when the bit has the value 0, and the memory cell being placed in the second memory state when the bit has the value 1;”
However, it is unclear to Examiner how to reconcile “the bits of the binary weight elements of the weight vector being stored in the memory cells that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector” and “each of the bits of a weight element of the binary weight elements being stored in a row.” While each cell (bit) resides in a row and column, the former limitation appears to indicate bits of the binary weight elements are stored in a column direction, while the latter limitation appears to indicate bits of the binary weigh elements are stored in a row direction.
Claim 23 recites the limitation “bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range” in step B. The meaning of this limitation is unclear. It appears “this weight range” refers to “the same weight range,” but this seems to create a circular limitation in which bits stored in a weight range are being stored in the weight range that already store the bits. It is also possible “this weight range” refers to “a weight range” in line 4 of step B.
Examiner believes step B may be related to organization of weights in bit sections, but it is unclear how this is accomplished.
Claim 23 recites the limitation “for the bits of the input elements of the input vector having the same value” in step D, sub-step b. It is unclear to what “having the same value” refers.
If the intent is “for the bits…having the same value,” then there is insufficient antecedent basis for “the input vector” and the aforementioned limitation may be interpreted as “for the bits of the input elements of the at least one of the one or multiple input vectors having the same value.”
If the intent is “…the input vector having the same value,” then there is lack of antecedent basis for “the input vector having the same value” and may be interpreted as “[[the]] an input vector having the same value.”
In either case, it is unclear what “having the same value” means (the same as what?).
For the purpose of this action, the aforementioned limitation shall be interpreted as “for the bits of the input elements of the at least one of the one or multiple input vectors having equal value.”
Claim 21 recites in step C, substep iii, the limitation, “the number of bits by which the binary value is to be shifted being predefined for each bit shifting unit, the predefined number of bits being determined as a sum of the value of the bits of the input elements, corresponding to which voltages are applied, and of the value of the bits of the weight elements that are stored in the bit section to which the bit shifting unit is connected via the analog-to-digital converter.” It is unclear how a number of bits can simultaneously be both “predefined” and calculated based on current conditions.
Claim 24 recites the limitation “the matrix circuit” in line 9. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “the at least one matrix circuit,” which finds antecedent basis in line 7.
Claim 24 recites the limitation “the applied voltage” in line 17. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “[[the]] an applied voltage.”
Claim 24 recites the limitation “the column lines of the memory cells of the bit section being connected to the analog-to-digital converter” in lines 28-30. There is insufficient antecedent basis for this limitation in the claim. Because it appears a particular instance of a bit section is in view (i.e., the one “being connected to” a particular instance of an analog-to-digital converter), for the purpose of this action, the aforementioned claim shall be interpreted as “[[the]] column lines of [[the]] memory cells of [[the]] a bit section being connected to [[the]] an analog-to-digital converter.”
Claim 24 recites the limitation “for at least one of the input vectors” in step D. There is insufficient antecedent basis for this limitation in the claim. For this purpose of this action, the aforementioned limitation shall be interpreted as “for at least one of the one or multiple input vectors,” which finds antecedent basis in claim 24, line 2.
Claim 24 recites the limitation, “assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned” in step A.
There is insufficient antecedent basis for the limitation “the first weight vectors” in step A of the claim. Based on the nearest context, Examiner believes “the first weight vectors” may be intended to reference “predetermined first weight vectors,” which finds antecedent basis in line 48 of the claim. For the purpose of this action, “the first weight vectors” shall be interpreted as “the predetermined first weight vectors” in this and subsequent instances of “the first weight vectors” in steps B and C of the claim.
It is apparent to Examiner that “the weight vector to which the adder is assigned” refers to “each first weight vector” of the step because of the “adder” qualifier. However, it also appears from the limitations of step B that a distinction is being made between “first weight vector” and “weight vector."
Therefore, for the purpose of this action, the limitation, “assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned” in step A shall be interpreted as, “assigning an adder of the adders to each weight vector of the predetermined first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned.”
Based on this interpretation, Examiner believes the following interpretation of step B is appropriate:
“B) storing bits of the binary weight elements of the predetermined first weight vectors, for each weight vector, the bits of the binary weight elements of the weight vector being stored in the memory cells that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector, each of the bits of a weight element of the binary weight elements being stored in a row, bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range, and when a bit is stored in a memory cell, the memory cell being placed in the first memory state when the bit has the value 0, and the memory cell being placed in the second memory state when the bit has the value 1;”
However, it is unclear to Examiner how to reconcile “the bits of the binary weight elements of the weight vector being stored in the memory cells that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector” and “each of the bits of a weight element of the binary weight elements being stored in a row.” While each cell (bit) resides in a row and column, the former limitation appears to indicate bits of the binary weight elements are stored in a column direction, while the latter limitation appears to indicate bits of the binary weigh elements are stored in a row direction.
Claim 24 recites the limitation “bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range” in step B. The meaning of this limitation is unclear. It appears “this weight range” refers to “the same weight range,” but this seems to create a circular limitation in which bits stored in a weight range are being stored in the weight range that already store the bits. It is also possible “this weight range” refers to “a weight range” in line 4 of step B.
Examiner believes step B may be related to organization of weights in bit sections, but it is unclear how this is accomplished.
Claim 24 recites the limitation “for the bits of the input elements of the input vector having the same value” in step D, sub-step b. It is unclear to what “having the same value” refers.
If the intent is “for the bits…having the same value,” then there is insufficient antecedent basis for “the input vector” and the aforementioned limitation may be interpreted as “for the bits of the input elements of the at least one of the one or multiple input vectors having the same value.”
If the intent is “…the input vector having the same value,” then there is lack of antecedent basis for “the input vector having the same value” and may be interpreted as “[[the]] an input vector having the same value.”
In either case, it is unclear what “having the same value” means (the same as what?).
For the purpose of this action, the aforementioned limitation shall be interpreted as “for the bits of the input elements of the at least one of the one or multiple input vectors having equal value.”
Claim 24 recites in step C, substep iii, the limitation, “the number of bits by which the binary value is to be shifted being predefined for each bit shifting unit, the predefined number of bits being determined as a sum of the value of the bits of the input elements, corresponding to which voltages are applied, and of the value of the bits of the weight elements that are stored in the bit section to which the bit shifting unit is connected via the analog-to-digital converter.” It is unclear how a number of bits can simultaneously be both “predefined” and calculated based on current conditions.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 13 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Muralimanohar, et al (US 20180004708 A1), hereinafter Muralimanohar.
Regarding independent claim 13, Muralimanohar teaches a scalar product circuit for computing a binary scalar product of an input vector and a weight vector (¶[0024], [0039]), comprising:
one or multiple adders (FIG. 4; ¶[0050]) that are configured to add received binary values and form a summed binary value (FIG. 4, e.g., 10-bit adders shown between DPE blocks, each feeding subsequent 15-bit and 64-bit adders); and
at least one matrix circuit including memory cells arranged in multiple rows and multiple columns in the form of a matrix (FIG. 2; ¶[0022]), each memory cell of the memory cells including a first memory state and a second memory state (¶[0025] teaches “each resistive memory element may be set to at least two states”), the matrix circuit including a row line for each row of the rows (FIG. 2, 204; ¶[0028]) and a column line for each column of the columns (FIG. 2, 206; ¶[0028]), each memory cell being connected to one row line and to one column line (FIG. 2, each cell is shown connected to one row line and one column line) and being configured to conduct an electrical current into the column line connected to the memory cell (referencing FIG. 2, ¶[0033] teaches “the plurality of column lines 206 may deliver output currents 214”), a current intensity of the current being a function of a voltage that is present at the row line connected to the memory cell (FIG. 2, 210; ¶[0032] teaches “crossbar array 200 may receive a set of input voltages 210 at the plurality of row lines 204”), and of the memory state of the memory cell (referencing FIG. 2, ¶[0025] teaches “each memory cell 208 may include a resistive memory element. A resistive memory element may have a resistance that changes with an applied voltage or current. Furthermore, in some examples, the resistive memory element may ‘memorize’ its last resistance. In this manner, each resistive memory element may be set to at least two states”), the current intensity being equal to zero when a voltage of zero is applied (referencing FIG. 2, ¶[0041] teaches the output current at 214 is the sum of products of Vi and Gi; therefore, if input voltages are zero, output currents will be zero),
and the current intensities for the first and the second memory states being different from one another when the applied voltage has a predetermined voltage value not equal to zero (FIG. 2, transimpedance amplifiers 218 are current-to-voltage converters; if Vi for a given row line is constant (“predetermined”) and the resistance of an associated cell changes, by Ohm’s Law, the current flowing into the associated amplifier will change, resulting in a change in its output voltage);
wherein each matrix circuit of the at least one matrix circuit includes at least one weight range (weights are determined by memristor values and have ranges; ¶[0031-0032]) with one or multiple bit sections, each bit section of the bit sections including at least one column of the memory cells (e.g., FIG. 2 may show up to as many as M “bit sections”), the memory cells within each bit section being configured in such a way that when a voltage having the predetermined voltage value is present at each of the row lines that are connected to the memory cells, and when the memory cells are in the second memory state, the current having the same current intensity is conducted from each memory cell into the column line connected to the memory cell (that is, referencing FIG. 2, if all of the input voltages at 210 are the same and all of the resistances of the memory cells are the same, the output current from each memristor will be the same, which must be true via Ohm’s Law);
wherein the matrix circuit includes, for each bit section, an analog-to-digital converter (¶[0040] teaches “every column may a transimpedance amplifier such as shown at 218, which may in turn be connected to an ADC to digitize the output current from the respective column lines 206”; see also ADCs coupled to dot-product engines DPE in FIG. 4) and a bit shifting unit connected to the analog-to-digital converter (FIG. 4 shows bit shifters, e.g., coupled to the top left ADC following its associated DPE), the column lines of the memory cells of the bit section being connected to the analog-to-digital converter (FIG. 4, each DPE represents the circuit of FIG. 2 (see ¶[0041], which teaches the circuit of FIG. 2 outputs a dot-product, which is digitized by an ADC)), and the analog-to-digital converter being configured to determine a binary value corresponding to the current intensity of a current flowing at an input of the analog-to-digital converter (the output of the circuit of FIG. 2 is a voltage representation of the currents output on the column lines, which is input to an 8-bit ADC in FIG. 4), and to transfer the binary value to the bit shifting unit (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder), each bit shifting unit being configured to shift the bits of the binary value transferred to it by a predefinable number of bits in a direction that arithmetically corresponds to a multiplication by a corresponding power of 2 (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, which represents multiplying by a “predefinable” power of two);
wherein, for each column of the memory cells, a column selection switching element is provided which is configured to activate the column, and when the column is activated, a current corresponding to the voltages present at the row lines and to the memory states of the memory cells being provided by the column line to the analog-to-digital converter connected to the column line, and when the column is not activated, no current being provided by the column line to the analog-to-digital converter connected thereto (This appears to be describing row and column decoders. While not shown in FIG. 2, ¶[0034] teaches “an address decoder may be used to select a row line 204 and activate a drive circuit corresponding to the selected row line 204. The drive circuit for a selected row line 204 can drive a corresponding row line 204 with different voltages corresponding to an input vector or the process of setting resistance values within memory cells 208 of crossbar array 200. Similar drive and decode circuitry may be included for column lines 206”);
wherein, the bit shifting units are connected to one of the adders (e.g., FIG. 4 shows a left-shift-by-2 shifter preceding an adder), in each case those bit shifting units that are included in a weight range being connected to the same adder (the left-shift-by-2 shifter is in a path in which a DPE output current/voltage is determined by the weights stored in the memory cells of the matrix).
Regarding claim 17, Muralimanohar teaches the limitations of claim 13.
Muralimanohar further teaches each of the memory cells includes: i) a memristor (¶[0025-0026]), and/or ii) a semiconductor switching element, and/or (iii) a ferroelectric field effect transistor or a field effect transistor with a floating gate.
Regarding claim 18, Muralimanohar teaches the limitations of claim 13.
Muralimanohar further teaches multiple matrix circuits are provided, the bit shifting units from one weight range in each case being connected to the same adder in two or more of the matrix circuits (FIG. 4, 440 shows multiple DPE blocks, at least two DPE blocks coupled to left-shift-by-2 shifters, the shifters indirectly connected to (through separate 10b adders) the same 15b and 64b adders).
Regarding claim 19, Muralimanohar teaches the limitations of claim 13.
Muralimanohar further teaches a voltage generation element (FIG. 4, DAC Array) is provided which is connected to the row line (FIG. 4, DAC Array is coupled to input of DPE blocks) and configured, as a function of a predefined input signal which may be present in two different value ranges, to generate a voltage of 0 V or a voltage having the predetermined voltage value and apply it to the row line (referencing FIG. 2, ¶[0032] teaches “The set of input voltages 210 may have been converted from an input vector by a digital-to-analog converter (DAC). A drive circuit may deliver the set of input voltages 210 to the crossbar array 200.” ¶[0016] teaches “the highest and lowest voltage values of the input voltages in the first set and second set of input voltages may correspond to a maximum and a minimum voltage,” which are predefined values (see also ¶[0044]). ¶[0036] further teaches grounding row lines (setting the row lines to 0V)).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Muralimanohar, et al (US 20180004708 A1), hereinafter Muralimanohar.
Regarding claim 20, Muralimanohar teaches the limitations of claim 13.
Muralimanohar does not teach the analog-to-digital converters are configured to determine the binary values using 5 bits or fewer. However, the claimed range will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating this range is critical, which is lacking in the present disclosure. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation” – In re Aller, 220 F.2d 454,456,105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05(II)(A).
12. Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Muralimanohar, et al (US 20180004708 A1), hereinafter Muralimanohar, in view of Soliman, et al (T. Soliman et al., "A Ferroelectric FET Based In-memory Architecture for Multi-Precision Neural Networks," 2020 IEEE 33rd International System-on-Chip Conference (SOCC), Las Vegas, NV, USA, 2020, pp. 96-101, doi: 10.1109/SOCC49529.2020.9524750), hereinafter Soliman.
Regarding claim 14, Muralimanohar teaches the limitations of claim 13.
Muralimanohar does not teach each of the memory cells is configured in such a way that when the predetermined voltage value is present, the current intensity of the current that is conducted into the column line when the memory cell is in the second memory state is greater, by a multiple, than the current intensity of the current that is conducted into the column line when the memory cell is in the first memory state, the multiple being at least 100.
Soliman teaches each of the memory cells is configured in such a way that when the predetermined voltage value is present, the current intensity of the current that is conducted into the column line when the memory cell is in the second memory state is greater, by a multiple, than the current intensity of the current that is conducted into the column line when the memory cell is in the first memory state, the multiple being at least 100 (Soliman teaches in p. 97, col. 2, section B, paragraph 2, “a high on/off ratio reaching values in the range 103 – 105”).
Regarding claim 15, Muralimanohar as modified by Soliman teaches the limitations of claim 14.
Muralimanohar does not teach the multiple is at least 1000.
Soliman teaches the multiple is at least 1000 (Soliman teaches in p. 97, col. 2, section B, paragraph 2, “a high on/off ratio reaching values in the range 103 – 105”).
Regarding claim 16, Muralimanohar teaches the limitations of claim 13.
Muralimanohar does not teach each of the memory cells is configured in such a way that when the memory cell is in the first state, no current is conducted into the column line connected to the memory cell (this appears to be the embodiment of FIG. 5 in the instant application, which may utilize an FeFET and adds power supply line 58 to each memory cell; “no current” is presumed to indicate the “off state” of the FeFET, neglecting leakage).
Soliman teaches each of the memory cells is configured in such a way that when the memory cell is in the first state, no current is conducted into the column line connected to the memory cell (Soliman teaches in p. 97, col. 2, section B, paragraph 2, “on” and “off” states of an FeFET, “no current” meaning the FeFET is in the “off” state).
Regarding claims 14 and 16, it would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Soliman into the method of Muralimanohar to use an FeFET to implement each memory cell in a crossbar architecture. The ordinary artisan would have been motivated to modify Muralimanohar in the above manner for the purpose of reducing power consumption (Soliman, TABLE III).
13. Claims 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Muralimanohar, et al (US 20180004708 A1), hereinafter Muralimanohar, in view of Halutz, et al (US 10915297 B1), hereinafter Halutz.
Regarding independent claim 21, Muralimanohar teaches a method for computing binary scalar products of one or multiple input vectors, each including binary input elements, and one or multiple predetermined first weight vectors, each including binary weight elements (¶[0024]; FIG. 6; ¶[0060]), using a scalar product circuit (FIG. 2; ¶[0039] teaches a dot-product) including:
one or multiple adders (FIG. 4; ¶[0050]) that are configured to add received binary values and form a summed binary value (FIG. 4, e.g., 10-bit adders shown between DPE blocks, each feeding subsequent 15-bit and 64-bit adders), and
at least one matrix circuit including memory cells arranged in multiple rows and multiple columns in the form of a matrix (FIG. 2; ¶[0022]), each memory cell of the memory cells including a first memory state and a second memory state (¶[0025] teaches “each resistive memory element may be set to at least two states”), the matrix circuit including a row line for each row of the rows (FIG. 2, 204; ¶[0028]) and a column line for each column of the columns (FIG. 2, 206; ¶[0028]), each memory cell being connected to one row line and to one column line (FIG. 2, each cell is shown connected to one row line and one column line) and being configured to conduct an electrical current into the column line connected to the memory cell (referencing FIG. 2, ¶[0033] teaches “the plurality of column lines 206 may deliver output currents 214”), a current intensity of the current being a function of a voltage that is present at the row line connected to the memory cell (FIG. 2, 210; ¶[0032] teaches “crossbar array 200 may receive a set of input voltages 210 at the plurality of row lines 204”), and of the memory state of the memory cell (referencing FIG. 2, ¶[0025] teaches “each memory cell 208 may include a resistive memory element. A resistive memory element may have a resistance that changes with an applied voltage or current. Furthermore, in some examples, the resistive memory element may ‘memorize’ its last resistance. In this manner, each resistive memory element may be set to at least two states”), the current intensity being equal to zero when a voltage of zero is applied (referencing FIG. 2, ¶[0041] teaches the output current at 214 is the sum of products of Vi and Gi; therefore, if input voltages are zero, output currents will be zero),
and the current intensities for the first and the second memory states being different from one another when the applied voltage has a predetermined voltage value not equal to zero (FIG. 2, transimpedance amplifiers 218 are current-to-voltage converters; if Vi for a given row line is constant (“predetermined”) and the resistance of an associated cell changes, by Ohm’s Law, the current flowing into the associated amplifier will change, resulting in a change in its output voltage),
wherein each matrix circuit of the at least one matrix circuit includes at least one weight range (weights are determined by memristor values and have ranges; ¶[0031-0032]) with one or multiple bit sections, each bit section of the bit sections including at least one column of the memory cells (e.g., FIG. 2 may show up to as many as M “bit sections”), the memory cells within each bit section being configured in such a way that when a voltage having the predetermined voltage value is present at each of the row lines that are connected to the memory cells, and when the memory cells are in the second memory state, the current having the same current intensity is conducted from each memory cell into the column line connected to the memory cell (that is, referencing FIG. 2, if all of the input voltages at 210 are the same and all of the resistances of the memory cells are the same, the output current from each memristor will be the same, which must be true via Ohm’s Law),
wherein the matrix circuit includes, for each bit section, an analog-to-digital converter (¶[0040] teaches “every column may a transimpedance amplifier such as shown at 218, which may in turn be connected to an ADC to digitize the output current from the respective column lines 206”; see also ADCs coupled to dot-product engines DPE in FIG. 4) and a bit shifting unit connected to the analog-to-digital converter (FIG. 4 shows bit shifters, e.g., coupled to the top left ADC following its associated DPE), the column lines of the memory cells of the bit section being connected to the analog-to-digital converter (FIG. 4, each DPE represents the circuit of FIG. 2 (see ¶[0041], which teaches the circuit of FIG. 2 outputs a dot-product, which is digitized by an ADC)), and the analog-to-digital converter being configured to determine a binary value corresponding to the current intensity of a current flowing at an input of the analog-to-digital converter (the output of the circuit of FIG. 2 is a voltage representation of the currents output on the column lines, which is input to an 8-bit ADC in FIG. 4), and to transfer the binary value to the bit shifting unit (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder), each bit shifting unit being configured to shift the bits of the binary value transferred to it by a predefinable number of bits in a direction that arithmetically corresponds to a multiplication by a corresponding power of 2 (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, which represents multiplying by a “predefinable” power of two),
wherein, for each column of the memory cells, a column selection switching element is provided which is configured to activate the column, and when the column is activated, a current corresponding to the voltages present at the row lines and to the memory states of the memory cells being provided by the column line to the analog-to-digital converter connected to the column line, and when the column is not activated, no current being provided by the column line to the analog-to-digital converter connected thereto (This appears to be describing row and column decoders. While not shown in FIG. 2, ¶[0034] teaches “an address decoder may be used to select a row line 204 and activate a drive circuit corresponding to the selected row line 204. The drive circuit for a selected row line 204 can drive a corresponding row line 204 with different voltages corresponding to an input vector or the process of setting resistance values within memory cells 208 of crossbar array 200. Similar drive and decode circuitry may be included for column lines 206”),
wherein, the bit shifting units are connected to one of the adders (e.g., FIG. 4 shows a left-shift-by-2 shifter preceding an adder), in each case those bit shifting units that are included in a weight range being connected to the same adder (the left-shift-by-2 shifter is in a path in which a DPE output current/voltage is determined by the weights stored in the memory cells of the matrix),
wherein the number of the adders of the scalar product circuit correspond to the number of the predetermined first weight vectors (FIG. 4, 440 shows a 2:1 relationship between DPEs and 10-bit adders, and therefore shows a relationship between the number of adders and the number of predetermined weight vectors in the DPE), one or multiple of the weight ranges that are situated in the at least at least one matrix circuit of the scalar product circuit when multiple weight ranges are assigned (weights are determined by memristor values and have ranges; ¶[0031-0032]), being assigned to each of the adders, each of the adders being connected to the bit shifting elements that are connected via the analog-to-digital converters (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder) to the bit sections included in the weight ranges assigned to the adder (e.g., FIG. 2 may show up to as many as M “bit sections” of at least one column, each “included” in the weight ranges, and each “assigned” to an adder (DPE containing bit sections of weights connected to ADC connected to an adder)), the method comprising the following steps:
A) assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned (FIG. 4 shows an output of a column (“bit section”) may be selected by a MUX to be connected to an ADC and an adder following, which can be said to be “assigning” the weights of that bit section to the adder);
B) storing bits of the binary weight elements of the first weight vectors, for each of the first weight vector, the bits of the binary weight elements of the weight vector being stored in the memory cells (¶[0035] teaches programming weight matrix elements into memory cells) that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector (¶[0012] teaches “The input voltage from each row line of the crossbar is weighted by the conductance of the resistive memory cells in each column line and accumulated as the current output from each column line”), each of the bits of a weight element of the binary weight elements being stored in a row (¶[0035-0036] teach weights are stored in a matrix at intersections of rows and columns), bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range, and when a bit is stored in a memory cell, the memory cell being placed in the first memory state when the bit has the value 0, and the memory cell being placed in the second memory state when the bit has the value 1 (¶[0061-0062] teach the lowest conductance state maps to the smallest bit value and the highest conductance state maps to the largest bit value, which may shifted/scaled as desired);
C) activating the columns of memory cells in which bits of the weight elements of the first weight vectors have been stored (e.g., ¶[0017] teaches “The interaction of the first set of input voltages with each crossbar array may each result in the delivery of a set of output currents 125 from each column line of the corresponding crossbar array”);
D) for at least one of the input vectors:
b) for the bits of the input elements of the input vector having the same value, in each case:
i) applying voltages corresponding to the bits to the row lines, voltages corresponding to the bits of various input elements being applied to various row lines, a voltage of 0 V being applied when the particular bit has the value 0, and a voltage having the predetermined voltage value being applied when the particular bit has the value 1 (FIG. 4, 440, the voltages applied to the row lines are determined by the DAC Array, and a DAC may be configured to output 0V when the digital input is zero and a non-zero output when the digital input is 1);
ii) determining binary values by the analog-to-digital converters (FIG. 4, 440, ADC);
iii) shifting the binary values by the bit shifting units in order to obtain shifted binary values, the number of bits by which the binary value is to be shifted being predefined for each bit shifting unit (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, with “2” being “predefined”), the predefined number of bits being determined as a sum of the value of the bits of the input elements, corresponding to which voltages are applied, and of the value of the bits of the weight elements that are stored in the bit section to which the bit shifting unit is connected via the analog-to-digital converter;
iv) adding the shifted binary values by the adders (e.g., FIG. 4 shows an adder following a left-shift-by-2 shifter).
Muralimanohar does not teach setting summed binary values of the adders to zero and reading out the summed binary values as first binary scalar products.
Halutz teaches a matrix multiplication apparatus which sets summed binary values of the adders to zero (Col. 8, l. 65 – Col. 9, l. 1 teaches “At the beginning of a cycle of multiplication of a new pair of input matrices…a multiplexer 64 inputs zero to adder 62”).
Halutz further teaches reading out a multiplication result (Col. 11, ll. 29-36).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Halutz into the method of Muralimanohar to include inputting zero into an adder at the beginning of a new multiplication cycle. The ordinary artisan would have been motivated to modify Muralimanohar in the above manner for the purpose of initializing an accumulator in a multiply-accumulate operation (Halutz Col. 8, l. 65 – Col. 9, l. 4).
Regarding claim 22, Muralimanohar as modified by Halutz teaches the limitations of claim 21.
(Claim 22 appears to apply steps of claim 21 to “second binary scalar products of the one or multiple input vectors and one or multiple predetermined second weight vectors,” which could be represented by a second DPE path in Muralimanohar FIG. 4, 440. Therefore, the mapping of limitations in claim 21 to Muralimanohar are also valid for claim 22 and need not be reiterated here.)
Muralimanohar further teaches second binary scalar products of the one or multiple input vectors and one or multiple predetermined second weight vectors which in each case include binary weight elements are computed, the number of second weight vectors being less than or equal to the number of first weight vectors, including:
E) assigning an adder of the adders to each second weight vector, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned;
F) storing bits of the binary weight elements of the second weight vectors, for each of the second weight vectors, the procedure corresponding to step B) being carried out, the bits of the weight elements of the second weight vectors being stored in columns that are different from the columns in which the bits of the weight elements of the first weight vectors are stored;
G) activating the columns in which bits of the weight elements of the second weight vectors have been stored;
H) for at least one of the input vectors, carrying out the substeps of step D),
except that in substep c) the summed binary values are read out as second scalar products.
14. Claims 23 is rejected under 35 U.S.C. 103 as being unpatentable over Bayat, et al (US 20190213234 A1), hereinafter Bayat, in view of Muralimanohar, et al (US 20180004708 A1), hereinafter Muralimanohar, and further in view of Halutz, et al (US 10915297 B1), hereinafter Halutz.
Regarding independent claim 23, Bayat teaches a module, comprising: a scalar product circuit (claims 1 and 11).
Bayat does not teach the module includes:
one or multiple adders that are configured to add received binary values and form a summed binary value.
Muralimanohar teaches one or multiple adders (FIG. 4; ¶[0050]) that are configured to add received binary values and form a summed binary value (FIG. 4, e.g., 10-bit adders shown between DPE blocks, each feeding subsequent 15-bit and 64-bit adders).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Muralimanohar into the method of Bayat to include adders in a scalar (dot) product circuit. The ordinary artisan would have been motivated to modify Bayat in the above manner for the purpose of adding or subtracting intermediate results (Muralimanohar ¶[0050]).
Muralimanohar further teaches at least one matrix circuit including memory cells arranged in multiple rows and multiple columns in the form of a matrix (FIG. 2; ¶[0022]), each memory cell of the memory cells including a first memory state and a second memory state (¶[0025] teaches “each resistive memory element may be set to at least two states”), the matrix circuit including a row line for each row of the rows (FIG. 2, 204; ¶[0028]) and a column line for each column of the columns (FIG. 2, 206; ¶[0028]),
each memory cell being connected to one row line and to one column line (FIG. 2, each cell is shown connected to one row line and one column line) and being configured to conduct an electrical current into the column line connected to the memory cell (referencing FIG. 2, ¶[0033] teaches “the plurality of column lines 206 may deliver output currents 214”), a current intensity of the current being a function of a voltage that is present at the row line connected to the memory cell (FIG. 2, 210; ¶[0032] teaches “crossbar array 200 may receive a set of input voltages 210 at the plurality of row lines 204”), and of the memory state of the memory cell (referencing FIG. 2, ¶[0025] teaches “each memory cell 208 may include a resistive memory element. A resistive memory element may have a resistance that changes with an applied voltage or current. Furthermore, in some examples, the resistive memory element may ‘memorize’ its last resistance. In this manner, each resistive memory element may be set to at least two states”), the current intensity being equal to zero when a voltage of zero is applied (referencing FIG. 2, ¶[0041] teaches the output current at 214 is the sum of products of Vi and Gi; therefore, if input voltages are zero, output currents will be zero), and the current intensities for the first and the second memory states being different from one another when the applied voltage has a predetermined voltage value not equal to zero (FIG. 2, transimpedance amplifiers 218 are current-to-voltage converters; if Vi for a given row line is constant (“predetermined”) and the resistance of an associated cell changes, by Ohm’s Law, the current flowing into the associated amplifier will change, resulting in a change in its output voltage),
wherein each matrix circuit of the at least one matrix circuit includes at least one weight range (weights are determined by memristor values and have ranges; ¶[0031-0032]) with one or multiple bit sections, each bit section of the bit sections including at least one column of the memory cells (e.g., FIG. 2 may show up to as many as M “bit sections”), the memory cells within each bit section being configured in such a way that when a voltage having the predetermined voltage value is present at each of the row lines that are connected to the memory cells, and when the memory cells are in the second memory state, the current having the same current intensity is conducted from each memory cell into the column line connected to the memory cell (that is, referencing FIG. 2, if all of the input voltages at 210 are the same and all of the resistances of the memory cells are the same, the output current from each memristor will be the same, which must be true via Ohm’s Law),
wherein the matrix circuit includes, for each bit section, an analog-to-digital converter (¶[0040] teaches “every column may a transimpedance amplifier such as shown at 218, which may in turn be connected to an ADC to digitize the output current from the respective column lines 206”; see also ADCs coupled to dot-product engines DPE in FIG. 4) and a bit shifting unit connected to the analog-to-digital converter (FIG. 4 shows bit shifters, e.g., coupled to the top left ADC following its associated DPE), the column lines of the memory cells of the bit section being connected to the analog-to-digital converter (FIG. 4, each DPE represents the circuit of FIG. 2 (see ¶[0041], which teaches the circuit of FIG. 2 outputs a dot-product, which is digitized by an ADC)), and the analog-to-digital converter being configured to determine a binary value corresponding to the current intensity of a current flowing at an input of the analog-to-digital converter (the output of the circuit of FIG. 2 is a voltage representation of the currents output on the column lines, which is input to an 8-bit ADC in FIG. 4), and to transfer the binary value to the bit shifting unit (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder), each bit shifting unit being configured to shift the bits of the binary value transferred to it by a predefinable number of bits in a direction that arithmetically corresponds to a multiplication by a corresponding power of 2 (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, which represents multiplying by a “predefinable” power of two),
wherein, for each column of the memory cells, a column selection switching element is provided which is configured to activate the column, and when the column is activated, a current corresponding to the voltages present at the row lines and to the memory states of the memory cells being provided by the column line to the analog-to-digital converter connected to the column line, and when the column is not activated, no current being provided by the column line to the analog-to-digital converter connected thereto (This appears to be describing row and column decoders. While not shown in FIG. 2, ¶[0034] teaches “an address decoder may be used to select a row line 204 and activate a drive circuit corresponding to the selected row line 204. The drive circuit for a selected row line 204 can drive a corresponding row line 204 with different voltages corresponding to an input vector or the process of setting resistance values within memory cells 208 of crossbar array 200. Similar drive and decode circuitry may be included for column lines 206”),
wherein, the bit shifting units are connected to one of the adders (e.g., FIG. 4 shows a left-shift-by-2 shifter preceding an adder), in each case those bit shifting units that are included in a weight range being connected to the same adder (the left-shift-by-2 shifter is in a path in which a DPE output current/voltage is determined by the weights stored in the memory cells of the matrix); and
a processing unit (FIG. 4, System Controller 430) connected to the scalar product circuit and configured to compute binary scalar products of one or multiple input vectors, each including binary input elements, and one or multiple predetermined first weight vectors, each including binary weight elements, using the scalar product circuit (¶[0049] teaches “system controller 430 and I/O buffer 434 may be provided for managing and aggregating results within the respective clusters),
wherein the number of the adders of the scalar product circuit correspond to the number of the predetermined first weight vectors (FIG. 4, 440 shows a 2:1 relationship between DPEs and 10-bit adders, and therefore shows a relationship between the number of adders and the number of predetermined weight vectors in the DPE), one or multiple of the weight ranges that are situated in the at least at least one matrix circuit of the scalar product circuit when multiple weight ranges are assigned (weights are determined by memristor values and have ranges; ¶[0031-0032]), being assigned to each of the adders, each of the adders being connected to the bit shifting elements that are connected via the analog-to-digital converters (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder) to the bit sections included in the weight ranges assigned to the adder (e.g., FIG. 2 may show up to as many as M “bit sections” of at least one column, each “included” in the weight ranges, and each “assigned” to an adder (DPE containing bit sections of weights connected to ADC connected to an adder)), and the processing unit is configured to:
A) assign an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned (FIG. 4 shows an output of a column (“bit section”) may be selected by a MUX to be connected to an ADC and an adder following, which can be said to be “assigning” the weights of that bit section to the adder);
B) store bits of the binary weight elements of the first weight vectors, for each of the first weight vector, the bits of the binary weight elements of the weight vector being stored in the memory cells (¶[0035] teaches programming weight matrix elements into memory cells) that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector (¶[0012] teaches “The input voltage from each row line of the crossbar is weighted by the conductance of the resistive memory cells in each column line and accumulated as the current output from each column line”), each of the bits of a weight element of the binary weight elements being stored in a row (¶[0035-0036] teach weights are stored in a matrix at intersections of rows and columns), bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range, and when a bit is stored in a memory cell, the memory cell being placed in the first memory state when the bit has the value 0, and the memory cell being placed in the second memory state when the bit has the value 1 (¶[0061-0062] teach the lowest conductance state maps to the smallest bit value and the highest conductance state maps to the largest bit value, which may shifted/scaled as desired);
C) activate the columns of memory cells in which bits of the weight elements of the first weight vectors have been stored (e.g., ¶[0017] teaches “The interaction of the first set of input voltages with each crossbar array may each result in the delivery of a set of output currents 125 from each column line of the corresponding crossbar array”);
D) for at least one of the input vectors:
b) for the bits of the input elements of the input vector having the same value, in each case:
i) apply voltages corresponding to the bits to the row lines, voltages corresponding to the bits of various input elements being applied to various row lines, a voltage of 0 V being applied when the particular bit has the value 0, and a voltage having the predetermined voltage value being applied when the particular bit has the value 1 (FIG. 4, 440, the voltages applied to the row lines are determined by the DAC Array, and a DAC may be configured to output 0V when the digital input is zero and a non-zero output when the digital input is 1);
ii) determine binary values by the analog-to-digital converters (FIG. 4, 440, ADC);
iii) shift the binary values by the bit shifting units in order to obtain shifted binary values, the number of bits by which the binary value is to be shifted being predefined for each bit shifting unit (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, with “2” being “predefined”), the predefined number of bits being determined as a sum of the value of the bits of the input elements, corresponding to which voltages are applied, and of the value of the bits of the weight elements that are stored in the bit section to which the bit shifting unit is connected via the analog-to-digital converter;
iv) add the shifted binary values by the adders (e.g., FIG. 4 shows an adder following a left-shift-by-2 shifter);
Muralimanohar does not teach setting summed binary values of the adders to zero and reading out the summed binary values as first binary scalar products.
Halutz teaches a matrix multiplication apparatus which sets summed binary values of the adders to zero (Col. 8, l. 65 – Col. 9, l. 1 teaches “At the beginning of a cycle of multiplication of a new pair of input matrices…a multiplexer 64 inputs zero to adder 62”).
Halutz further teaches reading out a multiplication result (Col. 11, ll. 29-36).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Halutz into the method of Muralimanohar to include inputting zero into an adder at the beginning of a new multiplication cycle. The ordinary artisan would have been motivated to modify Muralimanohar in the above manner for the purpose of initializing an accumulator in a multiply-accumulate operation (Halutz Col. 8, l. 65 – Col. 9, l. 4).
15. Claims 24 is rejected under 35 U.S.C. 103 as being unpatentable over Muralimanohar, et al (US 20200150923 A1), hereinafter Muralimanohar ‘923, in view of Muralimanohar, et al (US 20180004708 A1), hereinafter Muralimanohar, and further in view of Halutz, et al (US 10915297 B1), hereinafter Halutz.
Regarding independent claim 24, Muralimanohar ‘923 teaches a non-transitory machine-readable memory medium on which is stored a computer program for computing binary scalar products (claim 18) of one or multiple input vectors (¶[0029]).
Muralimanohar ‘923 does not explicitly teach each including binary input elements, and one or multiple predetermined first weight vectors, each including binary weight elements, using a scalar product circuit including: one or multiple adders that are configured to add received binary values and form a summed binary value.
Muralimanohar teaches each including binary input elements (¶[0063] teaches binary input elements), and one or multiple predetermined first weight vectors (¶[0030] teaches “memory cells 208 of crossbar array 200 may be programmed according to an input matrix” and must be “predetermined” to be programmed), each including binary weight elements, using a scalar product circuit including: one or multiple adders (FIG. 4; ¶[0050]) that are configured to add received binary values and form a summed binary value (FIG. 4, e.g., 10-bit adders shown between DPE blocks, each feeding subsequent 15-bit and 64-bit adders).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Muralimanohar into the method of Muralimanohar ‘923 to include positioning memory cells containing weight vectors between row lines and column lines. The ordinary artisan would have been motivated to modify Muralimanohar ‘923 in the above manner for the purpose of calculating new node values of an input vector of node values with respect to a weight matrix (Muralimanohar ¶[0024]).
Muralimanohar further teaches at least one matrix circuit including memory cells arranged in multiple rows and multiple columns in the form of a matrix (FIG. 2; ¶[0022]), each memory cell of the memory cells including a first memory state and a second memory state (¶[0025] teaches “each resistive memory element may be set to at least two states”), the matrix circuit including a row line for each row of the rows (FIG. 2, 204; ¶[0028]) and a column line for each column of the columns (FIG. 2, 206; ¶[0028]),
each memory cell being connected to one row line and to one column line (FIG. 2, each cell is shown connected to one row line and one column line) and being configured to conduct an electrical current into the column line connected to the memory cell (referencing FIG. 2, ¶[0033] teaches “the plurality of column lines 206 may deliver output currents 214”), a current intensity of the current being a function of a voltage that is present at the row line connected to the memory cell (FIG. 2, 210; ¶[0032] teaches “crossbar array 200 may receive a set of input voltages 210 at the plurality of row lines 204”), and of the memory state of the memory cell (referencing FIG. 2, ¶[0025] teaches “each memory cell 208 may include a resistive memory element. A resistive memory element may have a resistance that changes with an applied voltage or current. Furthermore, in some examples, the resistive memory element may ‘memorize’ its last resistance. In this manner, each resistive memory element may be set to at least two states”), the current intensity being equal to zero when a voltage of zero is applied (referencing FIG. 2, ¶[0041] teaches the output current at 214 is the sum of products of Vi and Gi; therefore, if input voltages are zero, output currents will be zero), and the current intensities for the first and the second memory states being different from one another when the applied voltage has a predetermined voltage value not equal to zero (FIG. 2, transimpedance amplifiers 218 are current-to-voltage converters; if Vi for a given row line is constant (“predetermined”) and the resistance of an associated cell changes, by Ohm’s Law, the current flowing into the associated amplifier will change, resulting in a change in its output voltage),
wherein each matrix circuit of the at least one matrix circuit includes at least one weight range (weights are determined by memristor values and have ranges; ¶[0031-0032]) with one or multiple bit sections (e.g., FIG. 2 may show up to as many as M “bit sections”), each bit section of the bit sections including at least one column of the memory cells, the memory cells within each bit section being configured in such a way that when a voltage having the predetermined voltage value is present at each of the row lines that are connected to the memory cells, and when the memory cells are in the second memory state, the current having the same current intensity is conducted from each memory cell into the column line connected to the memory cell (that is, referencing FIG. 2, if all of the input voltages at 210 are the same and all of the resistances of the memory cells are the same, the output current from each memristor will be the same, which must be true via Ohm’s Law),
wherein the matrix circuit includes, for each bit section, an analog-to-digital converter (¶[0040] teaches “every column may a transimpedance amplifier such as shown at 218, which may in turn be connected to an ADC to digitize the output current from the respective column lines 206”; see also ADCs coupled to dot-product engines DPE in FIG. 4) and a bit shifting unit connected to the analog-to-digital converter (FIG. 4 shows bit shifters, e.g., coupled to the top left ADC following its associated DPE), the column lines of the memory cells of the bit section being connected to the analog-to-digital converter (FIG. 4, each DPE represents the circuit of FIG. 2 (see ¶[0041], which teaches the circuit of FIG. 2 outputs a dot-product, which is digitized by an ADC)), and the analog-to-digital converter being configured to determine a binary value corresponding to the current intensity of a current flowing at an input of the analog-to-digital converter (the output of the circuit of FIG. 2 is a voltage representation of the currents output on the column lines, which is input to an 8-bit ADC in FIG. 4), and to transfer the binary value to the bit shifting unit (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder), each bit shifting unit being configured to shift the bits of the binary value transferred to it by a predefinable number of bits in a direction that arithmetically corresponds to a multiplication by a corresponding power of 2 (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, which represents multiplying by a “predefinable” power of two),
wherein, for each column of the memory cells, a column selection switching element is provided which is configured to activate the column, and when the column is activated, a current corresponding to the voltages present at the row lines and to the memory states of the memory cells being provided by the column line to the analog-to-digital converter connected to the column line, and when the column is not activated, no current being provided by the column line to the analog-to-digital converter 14 connected thereto (This appears to be describing row and column decoders. While not shown in FIG. 2, ¶[0034] teaches “an address decoder may be used to select a row line 204 and activate a drive circuit corresponding to the selected row line 204. The drive circuit for a selected row line 204 can drive a corresponding row line 204 with different voltages corresponding to an input vector or the process of setting resistance values within memory cells 208 of crossbar array 200. Similar drive and decode circuitry may be included for column lines 206”),
wherein, the bit shifting units are connected to one of the adders (e.g., FIG. 4 shows a left-shift-by-2 shifter preceding an adder), in each case those bit shifting units that are included in a weight range being connected to the same adder (the left-shift-by-2 shifter is in a path in which a DPE output current/voltage is determined by the weights stored in the memory cells of the matrix),
wherein the number of the adders of the scalar product circuit correspond to the number of the predetermined first weight vectors (FIG. 4, 440 shows a 2:1 relationship between DPEs and 10-bit adders, and therefore shows a relationship between the number of adders and the number of predetermined weight vectors in the DPE), one or multiple of the weight ranges that are situated in the at least at least one matrix circuit of the scalar product circuit when multiple weight ranges are assigned (weights are determined by memristor values and have ranges; ¶[0031-0032]), being assigned to each of the adders, each of the adders being connected to the bit shifting elements that are connected via the analog-to-digital converters (FIG. 4 shows the output of an ADC may be output to a shifter preceding an adder) to the bit sections included in the weight ranges assigned to the adder, the computer program, when executed by a processor (e.g., FIG. 2 may show up to as many as M “bit sections” of at least one column, each “included” in the weight ranges, and each “assigned” to an adder (DPE containing bit sections of weights connected to ADC connected to an adder)), causing the processor to perform the following steps:
A) assigning an adder of the adders to each first weight vector of the first weight vectors, and assigning the weight ranges that are assigned to the adder to the weight vector to which the adder is assigned (FIG. 4 shows an output of a column (“bit section”) may be selected by a MUX to be connected to an ADC and an adder following, which can be said to be “assigning” the weights of that bit section to the adder);
B) storing bits of the binary weight elements of the first weight vectors, for each of the first weight vector, the bits of the binary weight elements of the weight vector being stored in the memory cells (¶[0035] teaches programming weight matrix elements into memory cells) that are contained in each case in a column of a bit section of a weight range that is assigned to the weight vector (¶[0012] teaches “The input voltage from each row line of the crossbar is weighted by the conductance of the resistive memory cells in each column line and accumulated as the current output from each column line”), each of the bits of a weight element of the binary weight elements being stored in a row (¶[0035-0036] teach weights are stored in a matrix at intersections of rows and columns), bits of various weight elements of the weight vector that have the same value and that are stored in the same weight range being stored in the same bit section of this weight range, and when a bit is stored in a memory cell, the memory cell being placed in the first memory state when the bit has the value 0, and the memory cell being placed in the second memory state when the bit has the value 1 (¶[0061-0062] teach the lowest conductance state maps to the smallest bit value and the highest conductance state maps to the largest bit value, which may shifted/scaled as desired);
C) activating the columns of memory cells in which bits of the weight elements of the first weight vectors have been stored (e.g., ¶[0017] teaches “The interaction of the first set of input voltages with each crossbar array may each result in the delivery of a set of output currents 125 from each column line of the corresponding crossbar array”);
D) for at least one of the input vectors:
b) for the bits of the input elements of the input vector having the same value, in each case:
i) applying voltages corresponding to the bits to the row lines, voltages corresponding to the bits of various input elements being applied to various row lines, a voltage of 0 V being applied when the particular bit has the value 0, and a voltage having the predetermined voltage value being applied when the particular bit has the value 1 (FIG. 4, 440, the voltages applied to the row lines are determined by the DAC Array, and a DAC may be configured to output 0V when the digital input is zero and a non-zero output when the digital input is 1);
ii) determining binary values by the analog-to-digital converters (FIG. 4, 440, ADC);
iii) shifting the binary values by the bit shifting units in order to obtain shifted binary values, the number of bits by which the binary value is to be shifted being predefined for each bit shifting unit (FIG. 4 shows a left-shift-by-2 shifter preceding an adder, with “2” being “predefined”), the predefined number of bits being determined as a sum of the value of the bits of the input elements, corresponding to which voltages are applied, and of the value of the bits of the weight elements that are stored in the bit section to which the bit shifting unit is connected via the analog-to-digital converter;
iv) adding the shifted binary values by the adders (e.g., FIG. 4 shows an adder following a left-shift-by-2 shifter).
Muralimanohar ‘923 does not teach setting summed binary values of the adders to zero and reading out the summed binary values as first binary scalar products.
Halutz teaches a matrix multiplication apparatus which sets summed binary values of the adders to zero (Col. 8, l. 65 – Col. 9, l. 1 teaches “At the beginning of a cycle of multiplication of a new pair of input matrices…a multiplexer 64 inputs zero to adder 62”).
Halutz further teaches reading out a multiplication result (Col. 11, ll. 29-36).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Halutz into the method of Muralimanohar ‘923 to include inputting zero into an adder at the beginning of a new multiplication cycle. The ordinary artisan would have been motivated to modify Muralimanohar in the above manner for the purpose of initializing an accumulator in a multiply-accumulate operation (Halutz Col. 8, l. 65 – Col. 9, l. 4).
Conclusion
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827
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