Email Communication
Applicant is encouraged to authorize the Examiner to communicate via email by filing form PTO/SB/439 either via USPS, Central Fax, or EFS-Web. See MPEP 502.01, 502.02, 502.03.
DETAILED ACTION
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114.
Applicant's submission filed on 10/07/2025 has been entered.
Response to Amendment
Applicant’s amendment to Claim 6 has overcome claim objection previously set forth in final office action dated 06/10/2025, therefore, the objection has been withdrawn.
Applicant’s amendment to Claim 1 has overcome 35 U.S.C. 112(b) rejection previously set forth in final office action dated 06/10/2025, therefore, the rejection has been withdrawn.
The Applicant originally submitted Claims 1-13 in the application. In the previous response, the Applicant amended Claims 1-4 and 6-13 and cancelled Claim 5. In the present response, the Applicant amended Claims 1 and 6. Accordingly, Claims 1-4 and 6-13 are currently pending in the application.
Response to Arguments
Applicant’s Arguments/Remarks filled 10/07/2025, with respect to rejection of Claim 1, under 35 U.S.C. § 103 have been fully considered and are persuasive, therefore, the rejection has been withdrawn. However, upon further search and consideration, a new grounds of rejection has been set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6 are rejected under 35 U.S.C. § 103 as being unpatentable over Fan et al (US 2006/0180821) in view of Hathaway et al (US 2020/0203245).
Regarding Claim 1, Fan (In Figs 5-6) discloses support (180) for an electronic die (120) comprising:
a first printed circuit board (112), comprising
a first conductive region (184), intended to receive the die (120), wherein the first conductive region (184) forms a first metallization level (184) located on a first surface of and forming part of the first printed circuit board (112), (Fig 6);
a second conductive region (183), intended to receive a thermal connector (160), (¶ 30, II. 4-7), wherein the second conductive region (183) forms a second metallization level (183) located on a second surface of and forming part of the first printed circuit board (112), opposite to the first surface (Fig 6); and
one or a plurality of third conductive regions (190), wherein each third conductive region (190) is: interposed between the first region (184) and the second region (183); formed in a third distinct metallization level (190) within the first printed circuit board (112), located between the first and the second surfaces of the first printed circuit board (112), (Fig 6), and
wherein: the first conductive region (184) being connected to the second conductive region (183) by at least one through conductive via (180), located vertically in line with the first conductive region (184), the via (180) further connecting the third conductive regions (190) to one another (¶ 42, II. 9-11), (Fig 6), however Fan does not disclose wherein the die is adapted to operating at cryogenic temperatures.
Instead, Hathaway (In Fig 1) teaches wherein the die (24,30) is adapted to operating at cryogenic temperatures (¶ 19, II. 1-7).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Fan with Hathaway with the dies being adapted to operating at cryogenic temperatures to benefit from cooling each thermal sink layer at a respective temperature to maintain its coupled ground plane at its respective operational temperature requirements (Hathaway, ¶ 7, II. 7-11).
Regarding Claim 2, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan (In Fig 6) further discloses wherein the via (180) is filled with a thermally-conductive material ( 182, ¶ 31, II. 7-15).
Regarding Claim 3, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan (In Figs 5-6) further discloses wherein the via (180) is hollow (181) and has lateral walls (182) coated with a thermally-conductive material (¶ 31, II. 7-15).
Regarding Claim 4, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan as modified does not disclose wherein the die is a die adapted to operating at cryogenic temperatures, preferably a die comprising superconductive circuits.
Instead, Hathaway (In Fig 1) teaches wherein the die (30) comprises superconductive circuits (¶ 15, II. 17-22).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Fan with Hathaway with the die being comprising superconductive circuits to benefit from cooling each thermal sink layer at a respective temperature to maintain its coupled ground plane at its respective operational temperature requirements (Hathaway, ¶ 7, II. 7-11).
Regarding Claim 6, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan (In Figs 5-6) further discloses wherein stacked metallization levels (183/184/190/190) are separated by an insulating layer (111, ¶ 24, II. 5-7).
Claim 7 is rejected under 35 U.S.C. § 103 as being unpatentable over Fan in view of Hathaway and further in view of Berlin et al (US 2006/0109632).
Regarding Claim 7, Fan in view of Hathaway discloses the limitations of Claim 6, however Fan as modified does not disclose wherein the first conductive region has a surface area of approximately 50 mm2.
However, while Berlin (In Fig 2) teaches the first conductive region (region of 32) having a surface area, however it has been held a mere change in the size of a component is generally recognized as being within the level of ordinary skill in the art . In re. Rose, 105 USPQ 237. (CCP A 1955).
It would have been an obvious matter of design choice to modify Fan with Hathaway and further with Berlin with the first conductive region having a surface area of 50 mm2, since such a modification would have involved a mere change in the size of a component, and change in size is generally recognized as being within the level of ordinary skill in the art, (In Gardnerv.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 111 (Fed. Cir. 1984)).
Claims 8-9 are rejected under 35 U.S.C. § 103 as being unpatentable over Fan in view of Hathaway further in view of Berlin and further in view of Li et al (US 2011/0001230) prior art.
Regarding Claim 8, Fan in view of Hathaway and further in view of Berlin discloses the limitations of Claim 7, however Fan as modified does not disclose wherein the first printed circuit board comprises approximately one hundred first elements for contacting the die.
Instead Li (In Fig 1) teaches wherein the first printed circuit board (PCB, ¶ 18, II. 1-13) comprises approximately one hundred first elements (solder pads, ¶ 18, II. 1-13) for contacting the die (die, ¶ 18, II. 1-13).
Li teaches the number of solder pads can be increased by reducing the pitch, thereby Li establishes that number of solder pads is a result-oriented variable.
See MPEP 2144.05, II. B, in In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify Fan with Hathaway further with Berlin and further with Li with the first printed circuit board comprising one hundred first elements, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller 105 USPQ 233 (CCPA 1955).
Regarding Claim 9, Fan in view of Hathaway further in view of Berlin and further in view of Li prior art discloses the limitations of Claim 8, however Fan as modified does not discloses wherein the first contacting elements are located on a same side of the first board, with respect to the first region.
Instead, Li (In Fig 1) teaches wherein the first contacting elements (solder pads, ¶ 18, II. 1-13) are located on a same side of the first printed circuit board (PCB, ¶ 18, II. 1-13), with respect to the first conductive region (region of 120).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify Fan with Hathaway further with Berlin and further with Li with the first contacting elements being located on the same side of the first printed circuit board with respect to the first conductive region to benefit from improving heat dissipation and electrical connection by increasing the package layer count or size, providing effective improved device reliability (Li, ¶ 19, II. 1-10).
Claim 10 is rejected under 35 U.S.C. § 103 as being unpatentable over Fan in view of Hathaway and further in view of Kim (US 6,214,645).
Regarding Claim 10, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan as modified does not disclose wherein the first printed circuit board, of a substantially rectangular shape, has a length of approximately 12 cm and a width.
However, where Kim (6a) teaches wherein the first printed circuit board (10), of a substantially rectangular shape (Fig 6a), however Kim is silent with respect to the first printed circuit board having a length of 12 cm and a width of 3cmm.
It would have been an obvious to modify Fan with Hathaway and further with Kim with the first printed circuit board being rectangular shape and having a length of 12 cm and a width of 3cmm, since such a modification would have involved a mere change.in the size of a component a change in size is generally recognized as being within the level of ordinary skill in the art .In re. Rose, 105 USPQ 237. (CCP A 1955).
Claims 11-12 are rejected under 35 U.S.C. § 103 as being unpatentable over Fan in view of Hathaway and further in view of Choi et al (US 2006/0197209).
Regarding Claim 11, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan as modified does not disclose wherein the support for an electronic die further comprising at least one second printed circuit board, stacked to the first board.
Instead, Choi (In Figs 1-2) teaches wherein the support (100) for an electronic die (110) further comprising at least one second printed circuit board (102), stacked to the first board (108), (Fig 1).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify Fan with Hathaway and further with Choi with the support for the electronic comprising one second printed circuit board stacked to the first board to benefit from providing compact stacking and thermal management for improving cost and efficiencies (Choi ¶ 6, II. 1-6).
Regarding Claim 12, Fan in view of Hathaway and further in view of Choi discloses the limitations of Claim 11, however Fan as modified does not disclose wherein each second printed circuit board comprises second contacting elements intended to be connected to third contacting elements of the die by conductive wires.
Instead, Choi (In Figs 1-2) further teaches wherein each second printed circuit board (102) comprises second contacting elements (206) intended to be connected to third contacting elements (202) of the die (110) by conductive wires (114), (Fig 2).
It would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify fan with Hathaway and further with Choi with second printed circuit board comprising second contacting elements intended to be connected to third contacting elements of the die by conductive wires to benefit from providing compact stacking and thermal management for improving cost and efficiencies (Choi ¶ 6, II. 1-6).
Claim 13 is rejected under 35 U.S.C. § 103 as being unpatentable over Fan in view of Hathaway and further in view of Braunisch (US 2006/0109632).
Regarding Claim 13, Fan in view of Hathaway discloses the limitations of Claim 1, however Fan as modified does not disclose a system, comprising: at least one electronic die, adapted to operating in a cryogenic environment.
Instead, Hathaway (In Fig 1) teaches a system (10), comprising: at least one electronic die (30), adapted to operating in a cryogenic environment (¶ 3, II. 5-7).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Fan with Hathaway with a system comprising one electronic die adapted to operate in a cryogenic environment to benefit from cooling each thermal sink layer at a respective temperature to maintain its coupled ground plane at its respective operational temperature requirements (Hathaway, ¶ 7, II. 7-11), however Fan as modified does not disclose wherein at least one cold source; and the thermal connector, connecting the support to the cold source.
Instead, Braunisch (In Fig 3) teaches wherein at least one cold source (304); and the thermal connector (302), connecting the support (300) to the cold source (304), (Fig 3).
It would have been obvious to an ordinary skilled person in the art before the effective filling date of the claimed invention to modify Fan with Hathaway and further with Braunisch with a cold source and the thermal connector connecting the support to the cold source to benefit from adequately dissipating the heat generated by the die, improving potential impact to performance and reliability of the computing system (Braunisch, ¶ 2, II. 6-12).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMIR JALALI whose telephone number is (303)297-4308. The examiner can normally be reached on Monday - Friday 8:30am - 5:00pm, Mountain Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash Gandhi can be reached on 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AMIR A JALALI/Primary Examiner, Art Unit 2835