DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Status of claim(s) to be treated in this office action:
Independent: 9, 14 and 18.
Pending: 9-21.
Canceled: 1-8.
New: 9-21.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-11 and 18-21 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ryu et al. (Thin-Body N-Face GaN Transistor Fabricated by Direct Wafer Bonding, IEEE ELECTRON DEVICE LETTERS, Vol. 32, No. 7, pages 895-897, 2011, hereinafter Ryu) in view of Brawley et al. (US 20140312424 A1, hereinafter Brawley).
Re: Independent Claim 9, as best as can be understood Ryu discloses a method of manufacturing a semiconductor laminate structure, the method comprising:
providing a first substrate (Si (100) a substrate in page 895, lines 1-2, abstract, Fig. 1) comprising a main surface formed as a (100) plane of Si (Fig. 1);
forming a nitride semiconductor layer (GaN epiwafer including GaN and AlGaN layers, page 895, lines 1-2, 23, abstract, Fig. 1) on a second substrate (Si (111) wafer in page 896, lines 13-14, Fig. 1) through crystal-growth of a nitride semiconductor (GaN material) containing Ga;
forming an adhesive layer (oxide SiO2 film on the surface of the GaN epiwafer, page 896, lines 28-29, Fig. 1) on the main surface of the first substrate or on a surface of the nitride semiconductor layer (GaN epiwafer).
bonding the first substrate (Si (100)) and the second substrate (Si (111)) to each other in a +c-axis direction (page 896, lines 28-30, Fig. 1) in a state in which the nitride semiconductor layer (GaN epiwafer) faces the first substrate (Si (100)); and
after the bonding, removing (page 896, lines 33-34, Fig. 1) the second substrate (Si (111)) from the nitride semiconductor layer (GaN epiwafer).
Ryu does not expressly disclose forming an adhesive layer comprising AIN.
However, in the same semiconductor device field of endeavor, Brawley discloses forming an adhesive layer (302-304 an AlN layer in [0057], Fig. 3) comprising AIN.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Brawley’s method forming an adhesive layer comprising AIN to the Ryu’s method to include an adhesive layer including closer properties to the substrate such as thermal expansion ([0005], Brawley).
Re: Claim 10, Ryu modified by Brawley discloses the method according to claim 9, wherein a main surface of the nitride semiconductor layer (GaN epiwafer, Ryu) has N polarity (N-face GaN in page 896, lines 28-30, Fig. 1, Ryu).
Re: Claim 11, Ryu modified by Brawley discloses the method according to claim 9,
Ryu modified by Brawley does not expressly disclose further comprising forming the adhesive layer on the main surface of the first substrate and on the surface of the nitride semiconductor layer.
However, in the same semiconductor device field of endeavor, Brawley discloses forming an adhesive layer (302-304 an AlN layer in [0057], Fig. 3) on the main surface of the first substrate (202 silicon substrate in [0055], Fig. 3-Annotated) and on a surface of a semiconductor layer (204 any type of substrate that includes at least a surface layer of silicon in [0056], Fig. 3-Annotated).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Brawley’s method forming an adhesive layer on the main surface of the first substrate and on a surface of a semiconductor layer to the Ryu’s method to include an adhesive layer including closer properties to the substrate such as thermal expansion ([0005], Brawley), resulting in an adhesive layer on the main surface of the first substrate and on a surface of the nitride semiconductor layer.
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Brawley’s Figure 3-Annotated.
Re: Independent Claim 18, as best as can be understood Ryu discloses a semiconductor laminate structure comprising:
a substrate (Si (100) a substrate in page 895, lines 1-2, abstract, Fig. 1) having a main surface that is a (100) plane of Si (Fig. 1);
an adhesive layer (oxide SiO2 film on the surface of the GaN epiwafer, page 896, lines 28-29, Fig. 1) on the substrate (Si (100)); and
a nitride semiconductor layer (GaN epiwafer including GaN and AlGaN layers, page 895, lines 1-2, abstract, Fig. 1) comprising a nitride semiconductor (GaN material) containing Ga on the adhesive layer (oxide).
Ryu does not expressly disclose forming an adhesive layer comprising AIN.
However, in the same semiconductor device field of endeavor, Brawley discloses forming an adhesive layer (302-304 an AlN layer in [0057], Fig. 3) comprising AIN.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Brawley’s method forming an adhesive layer comprising AIN to the Ryu’s method to include an adhesive layer including closer properties to the substrate such as thermal expansion ([0005], Brawley).
Re: Claim 19, Ryu modified by Brawley discloses the semiconductor laminate structure according to claim 18, wherein a main surface of the nitride semiconductor layer (GaN epiwafer, Ryu) has N polarity (N-face GaN in page 896, lines 28-30, Fig. 1, Ryu).
Re: Claim 20, Ryu modified by Brawley discloses the semiconductor laminate structure according to claim 18, wherein the nitride semiconductor layer (GaN epiwafer, Ryu) is bonded (Fig. 1, Ryu) to the adhesive layer (oxide, Ryu).
Re: Claim 21, Ryu modified by Brawley discloses the semiconductor laminate structure according to claim 18, wherein the adhesive layer (oxide, Ryu) is bonded (Fig. 1, Ryu) to the substrate (Si (100), Ryu).
Claim(s) 12-13 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ryu in view of Brawley and further in view of Yoshida (US 20190165130 A1, hereinafter Yoshida).
Re: Claim 12, Ryu modified by Brawley discloses a method of manufacturing a semiconductor device comprising the semiconductor laminate structure of claim 9, the method comprising: after removing (page 896, lines 33-34, Fig. 1, Ryu) the second substrate (Si (111), Ryu) and exposing (Fig. 1, Ryu) a second surface of the nitride semiconductor layer (GaN epiwafer, Ryu),
Ryu modified by Brawley does not expressly disclose forming a recess on the second surface of the nitride semiconductor layer; selectively regrowing n-type GaN in the recess to form an n-GaN layer; and forming an electrode in ohmic contact with the n-GaN layer.
However, in the same semiconductor device field of endeavor, Yoshida discloses forming a recess on the second surface of the nitride semiconductor layer (12-13-14 forming a nitride layer [0015-0017], Figs.4A-C); selectively regrowing n-type GaN (15-16 GaN material filling the recess in [0018]) in the recess to form an n-GaN layer (15-16); and forming an electrode in ohmic contact (source electrode 31 and the drain electrode 32 are formed in [0019]) with the n-GaN layer (15-16).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Yoshida’s method forming a recess on the second surface of the nitride semiconductor layer; selectively regrowing n-type GaN in the recess to form an n-GaN layer; and forming an electrode in ohmic contact with the n-GaN layer to the method of Ryu and Brawley to form a HEMT device ([0013], Yoshida).
Re: Claim 13, Ryu modified by Brawley/ Yoshida discloses the method according to claim 12, wherein the second surface of the nitride semiconductor layer (GaN epiwafer, Ryu) has N polarity (N-face GaN in page 896, lines 28-30, Fig. 1, Ryu).
Claim(s) 14-17 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ryu in view of Brawley and further in view of D'Evelyn et al. (US 20120017825 A1, hereinafter D'Evelyn).
Re: Independent Claim 14, as best as can be understood Ryu discloses a method of manufacturing a semiconductor device, the method comprising:
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Ryu’s Figure 1-Annotated.
providing a first substrate (Si (100) a substrate in page 895, lines 1-2, abstract, Fig. 1) comprising a main surface formed as a (100) plane of Si (Fig. 1);
forming a nitride semiconductor layer (GaN epiwafer including GaN and AlGaN layers, page 895, lines 1-2, abstract, Fig. 1) on a second substrate (Si (111) wafer in page 896, lines 13-14, Fig. 1), wherein forming the nitride semiconductor layer (GaN epiwafer) comprises:
forming a buffer layer (GaN-B layer, Fig. 1-Annotated) on the second substrate (Si (111)) through crystal-growth of a first nitride semiconductor containing (GaN material) Ga in a +c-axis direction (Fig. 1-Annotated);
forming an etching stop layer (10-nm AlGaN layer, page 896, line 16, Fig. 1-Annotated) on the buffer layer (GaN-B) through crystal-growth of a nitride semiconductor containing Al (ALGaN material) and having a thermal decomposition temperature higher than that of GaN (10-nm AlGaN layer has higher thermal decomposition temperature than of GaN) in the +c-axis direction (Fig. 1-Annotated); and
forming an element formation layer (GaN-F layer, page 896, line 15, Fig. 1-Annotated) on the etching stop layer (10-nm AlGaN) through crystal-growth of a second nitride semiconductor (GaN material) in the +c-axis direction (Fig. 1-Annotated);
forming an adhesive layer (oxide SiO2 film on the surface of the GaN epiwafer, page 896, lines 28-29, Fig. 1) on the main surface of the first substrate or on a surface of the nitride semiconductor layer (GaN epiwafer);
bonding the first substrate (Si (100)) and the nitride semiconductor layer (GaN epiwafer) to each other in the +c- axis direction (page 896, lines 28-30, Fig. 1) using the adhesive layer (oxide);
after the bonding, removing (page 896, lines 33-34, Fig. 1) the second substrate (Si (111)) from the nitride semiconductor layer (GaN epiwafer); and
after the removing, selectively to remove (after the selective etch, the 10-nm AlGaN etch-stop is exposed, page 896, lines 39-43, Fig. 1) the buffer layer (GaN-B) and to expose the etching stop layer (10-nm AlGaN).
Ryu does not expressly disclose forming an adhesive layer comprising AIN, selectively thermally decomposing the buffer layer with respect to the etching stop layer by heating in a hydrogen atmosphere containing ammonia to remove the buffer layer and to expose the etching stop layer.
However, in the same semiconductor device field of endeavor, Brawley discloses forming an adhesive layer (302-304 an AlN layer in [0057], Fig. 3) comprising AIN.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Brawley’s method forming an adhesive layer comprising AIN to the Ryu’s method to include an adhesive layer including closer properties to the substrate such as thermal expansion ([0005], Brawley).
Ryu modified by Brawley does not expressly disclose selectively thermally decomposing the buffer layer with respect to the etching stop layer by heating in a hydrogen atmosphere containing ammonia to remove the buffer layer and to expose the etching stop layer.
However, in the same semiconductor device field of endeavor, D'Evelyn discloses thermally decomposing the buffer layer (GaN layer in [0087]) by heating (thermally desorbed by heating in [0087]) in a hydrogen atmosphere containing ammonia (hydrogen-containing ambient, such as ammonia in [0087]) to remove the buffer layer (GaN layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the D'Evelyn’s method forming thermally decomposing the buffer layer by heating in a hydrogen atmosphere containing ammonia to remove the buffer layer to the method of Ryu and Brawley to facilitate the etching process using a regular reactor ([0087], D'Evelyn), resulting in, after the removing, selectively thermally decomposing the buffer layer with respect to the etching stop layer by heating in a hydrogen atmosphere containing ammonia to remove the buffer layer and to expose the etching stop layer.
Re: Claim 15, Ryu modified by Brawley/D'Evelyn discloses the method according to claim 14, further comprising after thermally decomposing (D'Evelyn [0087] applied to Ryu) the buffer layer (GaN-B, Ryu), forming an electrode (source and drain region in Fig. 3, Ryu) on the element formation layer (GaN-F, Ryu).
Re: Claim 16, Ryu modified by Brawley/D'Evelyn discloses the method according to claim 14, wherein a main surface of the nitride semiconductor layer (GaN epiwafer, Ryu) has N polarity (N-face GaN in page 896, lines 28-30, Fig. 1, Ryu).
Re: Claim 17, Ryu modified by Brawley/ D'Evelyn discloses the method according to claim 14, wherein the buffer layer (GaN-B, Ryu) comprises GaN and the etching stop layer (10-nm AlGaN, Ryu) comprises AlGaN.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kaplun (US 20190326162 A1) teaches “GALLIUM NITRIDE SEMICONDUCTOR STRUCTURE AND PROCESS FOR FABRICATING THEREOF”. This document is related to a semiconductor substrate structure includes a silicon carbide wafer substrate, an active gallium nitride layer and a layer of microcrystalline diamond layer disposed between the SiC wafer substrate and the GaN active layer.
Radway (US 20170301772 A1) teaches “GaN DEVICES FABRICATED VIA WAFER BONDING”. This document is related to a method of fabrication of GaN device including a GaN layer on a first substrate such as a silicon substrate, The assembly of the first substrate and the GaN layer is then bonded to a second substrate such as a carbide substrate or an AlN substrate, the first substrate is etched away to expose a GaN surface for further processing, such as electrode formation.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANDRA MILENA RODRIGUEZ VILLANUEVA whose telephone number is (571)272-1936. The examiner can normally be reached Monday to Friday 7:00am-5:00pm (EST).
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/AJAY OJHA/Supervisory Patent Examiner, Art Unit 2898 11/3/2025