DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160329421 (Shibata et al) in view of US 20160118491 (Okita et al).
Concerning claim 1, Shibata discloses a nitride semiconductor device comprising (Fig. 1): a substrate (12); and a first nitride semiconductor layer (2) ([0063], note that the first nitride semiconductor layer is GaN), a second nitride semiconductor layer (5) ([0063], note that the second nitride semiconductor layer is AlGaN), and a third nitride semiconductor layer (7) ([0063], note that the third nitride semiconductor layer is AlGaN) that are disposed above the substrate in stated order (Fig. 1) and. . ., wherein the first nitride semiconductor layer includes a recess (8, Fig. 1, note that the gate opening is interpreted as the recess), the second nitride semiconductor layer has a band gap larger than a band gap of the first nitride semiconductor layer (note that the first nitride semiconductor layer is disclosed as being GaN and the second nitride semiconductor layer is disclosed as being AlGaN it is well-known that AlGaN is a higher band gap material than GaN and therefore this limitation is met) and is disposed in a region other than the recess (Fig. 1, note that layer 5 is formed outside the gate opening 8), the third nitride semiconductor layer has a band gap larger than the band gap of the first nitride semiconductor layer (note that the first nitride semiconductor layer is disclosed as being GaN and the third nitride semiconductor layer is disclosed as being AlGaN it is noted that AlGaN is a higher band gap material than GaN and therefore this limitation is met) and covers the first nitride semiconductor layer and the second nitride semiconductor layer including an inner wall of the recess (Fig. 1), and a contact angle (180- θ) at which a side wall of the recess and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet ([0149]).
Shibata does not disclose the first, second, and third nitride semiconductor layers are partially in direct contact with one another or that the contact angle exclusively ranges from 140° to less than 180°. However, Shibata discloses that it is preferable that θ ≦45 degrees in order to obtain a greater Gx which also correlates to a larger contact angle at which a side wall of the recess and an interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet (with angles lower than 40 yielding angles within the claimed range). Shibata discloses that when the formula Gx>Gy is satisfied it is possible to lengthen the distance between inclined carrier region formed facing side wall of gate opening and first base layer, thereby suppressing a lowering of the sheet carrier density in inclined carrier region. As a result, it is possible for the resistance of two-dimensional electron gas layer to be reduced and for the on-resistance of the field effect transistor to be reduced. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). See MPEP 2144.05 II A. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to perform routine experimentation in the angle range of θ ≦45 degree as disclosed by Shibata in order to arrive at a contact angle range of 140° to less than 180° in order to reduce the resistance of two-dimensional electron gas layer and for the on-resistance of the field effect transistor to be reduced as a result.
Additionally, Okita discloses a nitride semiconductor device configuration with a first nitride semiconductor layer (102) that includes a recess (Fig. 6), a second nitride semiconductor layer (103) located outside the recess, and third semiconductor layer (106) stacked in the stated order and are partially in direct physical contact with one another (Fig. 6, [0006], and [0063], it is noted that one of the materials for the first nitride semiconductor layer is GaN which the examiner is relying on for this rejection, one of the materials for the second nitride semiconductor layer is AlGaN which the examiner is relying on for this rejection, and one of the materials for the third nitride semiconductor layer is AlGaN. It is disclosed in [0006] that first nitride semiconductor layer 3 (GaN, etc.) to be a channel layer is formed further above buffer layer 2, and second nitride semiconductor layer 4 (AlGaN, etc.) serving as a barrier layer having a band gap larger than a band gap of first nitride semiconductor layer 3 and therefore the limitation the second nitride semiconductor layer has a band gap larger than a band gap of the first nitride semiconductor layer is met). Okita discloses this configuration with the group III nitride semiconductor, a hetero structure such as AlGaN/GaN layers can be readily formed, and a high-concentration electron channel (two-dimensional electron gas which is referred to as 2DEG below) is generated in the GaN layer near an interface of the AlGaN/GaN layers due to piezoelectric charges generated from a difference in lattice constant between the AlGaN and the GaN layers, and a difference in bandgap between the AlGaN and the GaN layers provides a device capable of large-current operation and a high-speed operation and as a result, the group III nitride semiconductor can be expected to be used in an electron device such as a power field effect transistor (FET) and a diode ([0005]). It would have been obvious to one of ordinary skill to modify the configuration of Shibata such that the first, second, and third nitride semiconductor layers are partially in direct contact with one another to utilize the hetero structure of the AlGaN/GaN layers to provide a device capable of large-current operation and a high-speed operation as disclosed by Okita.
Continuing to claim 2, Shibata in view of Okita discloses wherein the contact angle at which the side wall of the recess and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet and a contact angle at which an other side wall of the recess on an opposite side and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet both range from 140° to less than 180° (Shibata Fig. 1 and [0149] it is noted that the contact angles are identical on both sides of the recess).
Considering claim 3, Shibata in view of Okita discloses wherein an average of the contact angle at which the side wall of the recess and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet and a contact angle at which an other side wall of the recess on an opposite side and the interface between the first nitride semiconductor layer and the second nitride semiconductor layer meet ranges from 145° to less than 180° (Shibata Fig. 1 and [0149] it is noted that the contact angles are identical on both sides of the recess).
Referring to claim 4, Shibata in view of Okita discloses the contact angle is larger than a taper angle at which a side wall of the second nitride semiconductor layer facing the recess and an upper surface of the second nitride semiconductor layer meet (Shibata [0127]).
Regarding claim 5, Shibata in view of Okita discloses a taper angle at which a side wall of the second nitride semiconductor layer facing the recess and an upper surface of the second nitride semiconductor layer meet ranges from 120° to less than 180° (Shibata [0127]).
Pertaining to claim 6, Shibata in view of Okita discloses a difference between the contact angle and a taper angle at which a side wall of the second nitride semiconductor layer facing the recess and an upper surface of the second nitride semiconductor layer meet (Shibata [0127]).
Shibata in view of Okita does not disclose the difference is within a range of ±20º. However, Shibata θ and discloses when the opening width of gate opening of the field effect transistor in the second exemplary embodiment is Xa and the width of the bottom portion of gate opening is Xb, Xa=6.4 μm and the Xb=5 μm. When done, Gx=3 μm, and Gy=0.1 μm. The formula Gx>>Gy is satisfied and a shallow depression remains slightly in the surface of first regrowth layer and the second regrowth layer. Shibata discloses that by doing so, it is possible to lengthen the distance between inclined carrier region 9a formed facing side wall of gate opening and first base layer , thereby suppressing a lowering of the sheet carrier density in inclined carrier region. For the interface formed between first regrowth layer and the second regrowth layer, the angle with respect to the main surface of the surface that forms an incline with the main surface becomes less than θ which is the angle formed with the main surface of the side surface of gate opening . Accordingly, lowering of the density of two-dimensional electron gas layer , and, in particular, inclined carrier region, in which the interface formed between first regrowth layer and the second regrowth layer arises is suppressed. As a result, it is possible for the resistance of two-dimensional electron gas layer to be reduced and for the on-resistance of the field effect transistor to be reduced. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the perform routine experimentation in order to arrive at the difference between the contact angle and a taper angle at which a side wall of the second nitride semiconductor layer facing the recess and an upper surface of the second nitride semiconductor layer meet being within a range of ±20º as this result effective variable contributes to the lowering of the density of two-dimensional electron gas layer , and, in particular, inclined carrier region, in which the interface formed between first regrowth layer and the second regrowth layer arises is suppressed and the on-resistance of the field effect transistor to be reduced.
As to claim 7, Shibata in view of Okita discloses a gradient of a tangent to the side wall of the recess and a gradient of a tangent to a side wall of the second nitride semiconductor layer facing the recess are uniquely determined (Shibata [0127]).
Concerning claim 8, Shibata in view of Okita discloses wherein an angle formed between the side wall of the recess and a side wall of the second nitride semiconductor layer facing the recess is within a range of 180° ±30° (Shibata Fig. 1 and [0149]).
Continuing to claim 9, Shibata in view of Okita discloses wherein a film thickness of a part of the third nitride semiconductor layer along a side wall of the second nitride semiconductor layer is more than or equal to 50% of a film thickness of a part of the third nitride semiconductor layer along a bottom of the recess in a vertical direction (Shibata [0092]).
Considering claim 10, Shibata in view of Okita discloses wherein the third nitride semiconductor layer contains Al, and an Al composition in the third nitride semiconductor layer is less than or equal to 25% (Shibata [0063], [0069], and [0091]).
Referring to claim 11, Shibata in view of Okita discloses the third nitride semiconductor layer contains Al, and an Al composition in the third nitride semiconductor layer varies within a range of ±5% (Shibata [0069]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20160329421 (Shibata et al) in view of US 20160118491 (Okita et al) as applied to claim 1 above, and further in view of US 20210005730 (Mukai et al).
Regarding claim 12, Shibata in view of Okita discloses further comprising: a source electrode (Shibata11 left) and a drain electrode (Shibata11 right) spaced from the recess with the recess disposed therebetween (Shibata Fig. 1).
Shibata in view of Okita does not disclose wherein a contact angle adjacent to the drain electrode is larger than a contact angle adjacent to the source electrode. However, Mukai discloses a nitride semiconductor device configuration (Fig. 1A) in which the first electrode 51 with the first angle θ1 at the first electrode 51 side (the source electrode side) is less than 90 degrees (a reverse-tapered configuration). the tilt at the second electrode 52 (drain side electrode) side may be a forward taper. The second angle θ2 is greater than 90 degrees. A high threshold voltage is obtained because the current does not flow easily in a portion of the current path ([0036]). Shibata discloses that this configuration leads to a normally-off characteristic being obtained easily and stably and a semiconductor device being provided in which the characteristics can be improved ([0034]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to form the contact angle adjacent the drain electrode larger than a contact angle adjacent to the source electrode as disclosed by Mukai in order to obtain a high threshold voltage and a semiconductor device with improved characteristics.
Response to Arguments
Applicant’s arguments, see page 6, filed 09/03/25, with respect to the rejection(s) of claim(s) 1-11 under 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of US 20160118491 (Okita et al).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VALERIE N NEWTON whose telephone number is (571)270-5015. The examiner can normally be reached M-F 8-5.
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/VALERIE N NEWTON/Examiner, Art Unit 2897 11/18/25
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897