DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4/4/2023 and 4/26/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 7-8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. US 2017/0170089 and Fan et al. US 2005/0133816.
Re claim 1, Donkers teaches a two-dimensional electron gas (2DEG) channel for a super-heterojunction structure (10, fig1, [37]), comprising:
at least one p-type layer (6, fig1, [43]);
Donkers does not explicitly show a n-type modulation doped layer; wherein the n-type modulation doped layer is adjacent the at least one p-type layer to generate a charge balanced super-heterojunction region.
Fan teaches a n-type modulation doped layer (n-type delta doping in AlGaN barrier layer 22, fig2, [28]); wherein the n-type modulation doped layer generate a charge balanced super-heterojunction region (delta doping increase the 2D electron density, [28]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers and Fan to add in delta doping in the top barrier layer AlGaN 12 in Donkers fig1. The motivation to do so is to increase the 2D electron density without sacrificing the mobility (Fan, [24]).
Donkers in view of Fan teaches a n-type modulation doped layer (Donkers, n-type delta doping in AlGaN barrier layer 12, fig1); wherein the n-type modulation doped layer is adjacent the at least one p-type layer (Donkers, p-type GaN 6, fig1, [43]) to generate a charge balanced super-heterojunction region (Donkers, 2DEG 8, fig1, [43]).
Re claim 2, Donkers modified above teaches the 2DEG channel of claim 1, wherein: the n-type modulation doped layer is formed by any one or combination of: n-type barrier layer doping (Donkers, n-type delta doping in AlGaN barrier layer 12, fig1); and n-type δ-doping in the barrier layer (Donkers, n-type delta doping in AlGaN barrier layer 12, fig1); and n-type doping at an interface between the barrier layer and the at least one p-type layer; and n-type δ-doping at an interface between the barrier layer and the at least one p- type layer.
Re claim 5, Donkers modified above teaches a diode, comprising: at least one 2DEG channel of claim 1 (Donkers, horizontal Schottky diode with gate contact corresponds to Schottky anode and drain contact corresponds to ohmic cathode, fig1, [38]).
Re claim 7, Donkers modified above teaches a transistor (Donkers, fig1), comprising: at least one diode having the 2DEG channel of claim 1 (Donkers, horizontal diode with gate contact corresponds to anode and drain contact corresponds to cathode, fig1, [38]).
Re claim 8, Donkers teaches a diode (Schottky diode formed between 20 and 15, fig 1, [38]), comprising:
a super-heterojunction structure (12, 6, fig1, [36];) having at least one two-dimensional electron gas (2DEG) channel (2DEG 8, fig1, [43]);
the at least one 2DEG channel (2DEG 8, fig1, [43]), comprising:
at least one p-type layer (6, fig1, [43]); and
an anode (20, fig1, [37, 38]); and
a cathode (15, fig1, [37, 38]).
Donkers does not explicitly show a n-type modulation doped layer; wherein the n-type modulation doped layer is adjacent the at least one p-type layer to generate a charge balanced super-heterojunction region.
Fan teaches a n-type modulation doped layer (n-type delta doping in AlGaN barrier layer 22, fig2, [28]); wherein the n-type modulation doped layer generate a charge balanced super-heterojunction region (delta doping increase the 2D electron density, [28]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers and Fan to add in delta doping in the top barrier layer AlGaN 12 in Donkers fig1. The motivation to do so is to increase the 2D electron density without sacrificing the mobility (Fan, [24]).
Donkers in view of Fan teaches a n-type modulation doped layer (Donkers, n-type delta doping in AlGaN barrier layer 12, fig1); wherein the n-type modulation doped layer is adjacent the at least one p-type layer (Donkers, p-type GaN 6, fig1, [43]) to generate a charge balanced super-heterojunction region (Donkers, 2DEG 8, fig1, [43]).
Re claim 19, Donkers modified above teaches a transistor, comprising: a least one diode of claim 8 (Donkers, 10 with n-type delta doping in AlGaN barrier layer 12, fig1).
Claim(s) 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. US 2017/0170089, Fan et al. US 2005/0133816 and Wathuthanthri et al. US 2021/0028295.
Re claim 6, Donkers does not explicitly show a diode, comprising: a plurality of 2DEG channels of claim 1.
Wathuthanthri teaches stacking plurality of two-material heterostructures with addition of appropriate doping layers to maintain 2DEG channels to achieve greater current flow with low on resistance (fig2, [3,35]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers, Fan and Wathuthanthri to form a gate all around structure and stack plurality of two-material heterostructures with addition of appropriate doping layers under the gate. The motivation to do so is to achieve greater current flow with low on resistance (Wathuthanthri, [3,35]).
Re claim 18, Donkers does not explicitly show the diode of claim 8, comprising: a plurality of 2DEG channels.
Wathuthanthri teaches stacking plurality of two-material heterostructures with addition of appropriate doping layers to maintain 2DEG channels to achieve greater current flow with low on resistance (fig2, [3,35]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers, Fan and Wathuthanthri to form a gate all around structure and stack plurality of two-material heterostructures with addition of appropriate doping layers under the gate. The motivation to do so is to achieve greater current flow with low on resistance (Wathuthanthri, [3,35]).
Claim(s) 9-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. US 2017/0170089, Fan et al. US 2005/0133816 and Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011
Re claim 9, Donkers does not explicitly show the diode of claim 8, wherein: the anode is configured as a Schottky contact and a p-ohmic contact.
Nakajima teaches the anode is configured as a Schottky contact (G with Schottky contact, fig1) and a p-ohmic contact (B makes ohmic contact with P-GaN, fig1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers, Fan, and Nakajima to replace Donkers 20 and 21 with G in contact with AlGaN layer, B, P-GaN and GaN layer added over Donkers 12 AlGaN as in Nakajima fig1. The motivation to do so is to discharge with both 2DHG and 2DEG during the turn-off period and enhance the breakdown capability of the device (Nakajima, II device structure and behavior).
Re claim 10, Donkers modified above teaches the diode of claim 9, wherein: the Schottky contact forms a Schottky contact between the anode and the at least one 2DEG channel (Nakajima, Schottky contact between B and 2DEG, fig1).
Re claim 11, Donkers modified above teaches the diode of claim 9, wherein: the p-ohmic contact forms an ohmic contact between an p-ohmic metal (Nakajima, B, fig1) and the at least one p-type layer (Nakajima, P-GaN, fig1).
Re claim 13, Donkers modified above teaches the diode of claim 9, wherein: the Schottky contact and the p-ohmic contact are electrically connected (Nakajima, G in contact with B, fig1).
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. US 2017/0170089, Fan et al. US 2005/0133816, Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011 and Yu et la. US 2013/0126892.
Re claim 12, Donkers does not explicitly show the diode of claim 9, wherein: a p+ layer formed between a p-ohmic metal and the at least one p-type layer.
Yu teaches adding a P+ layer between the metal and P-GaN layer to reduce contact resistance (fig4A, [36]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers modified above and Yu to add in a P+ layer between the base metal and P-GaN. The motivation to do so is to reduce contact resistance (Yu, [36]).
Claim(s) 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. US 2017/0170089, Fan et al. US 2005/0133816 and Terano et al. US 2013/0134443.
Re claim 14, Donkers does not explicitly show the diode of claim 8, wherein: the cathode is configured as a n-ohmic contact .
Terano teaches forming Cathode electrode (8, fig2, [96]) above n-type layer (12, fig2, [95]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers modified above and Terano to add in a n-type layer under ohmic contact metal layer 14/15 of Donkers in fig1. The motivation to do so is to reduce contact resistance (Terano, [95]).
Re claim 15, Donkers modified above teaches the diode of claim 14, wherein: the n-ohmic contact forms an ohmic contact between the cathode and the at least one 2DEG channel (Donkers, Si implanted in region between 14/15 and 6/12, fig1).
Claim(s) 20 is rejected under 35 U.S.C. 103 as being unpatentable over Donkers et al. US 2017/0170089, Fan et al. US 2005/0133816, Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011 and Terano et al. US 2013/0134443.
Re claim 20, Donkers does not explicitly show the diode of claim 8, comprising: a p-n junction comprising a p-type region and a n-type region; the anode in electrical connection with the p-type region; the cathode in electrical connection with the n-type region; and the anode is configured as a p-ohmic contact.
Terano teaches forming Cathode electrode (8, fig2, [96]) above n-type layer (12, fig2, [95]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers modified above and Terano to add in a n-type layer under ohmic contact metal layer 14/15 of Donkers in fig1. The motivation to do so is to reduce contact resistance (Terano, [95]).
Nakajima teaches the anode is configured as a Schottky contact (G with Schottky contact, fig1) and a p-ohmic contact (B makes ohmic contact with P-GaN, fig1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Donkers, Fan, and Nakajima to replace Donkers 20 and 21 with G in contact with AlGaN layer, B, P-GaN and GaN layer added over Donkers 12 AlGaN as in Nakajima fig1. The motivation to do so is to discharge with both 2DHG and 2DEG during the turn-off period and enhance the breakdown capability of the device (Nakajima, II device structure and behavior).
Donkers modified above teaches a p-n junction comprising a p-type region (Nakajima, p-GaN directly under base B, fig1) and a n-type region (Nakajima, Si implanted in region between S/D and GaN/AlGaN stack, fig1); the anode in electrical connection with the p-type region (B form ohmic contact with p-GaN Nakajima fig1 and G form Schottky contact with carbon doped GaN channel layer 6 of Donkers in fig1); the cathode in electrical connection with the n-type region (n-type layer formed under ohmic contact metal layer 14/15 of Donkers in fig1); and the anode is configured as a p-ohmic contact (Nakajima, B form ohmic contact with p-GaN, fig1).
Claim(s) 1 and 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. US 2021/0082911 and Fan et al. US 2005/0133816.
Re claim 1, Chiu teaches a two-dimensional electron gas (2DEG) channel for a super-heterojunction structure (120, fig6, [33]), comprising:
at least one p-type layer (108, fig6, [23]);
Chiu does not explicitly show a n-type modulation doped layer; wherein the n-type modulation doped layer is adjacent the at least one p-type layer to generate a charge balanced super-heterojunction region.
Fan teaches a n-type modulation doped layer (Si backside doping in GaN Channel layer 14, fig6, [24]); wherein the n-type modulation doped layer generate a charge balanced super-heterojunction region (Si backside doping increase the 2D electron density, [24]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Chiu and Fan to add in delta doping in the top barrier layer AlGaN 112 and backside Si doping in GaN channel layer 110 on side of 108a of Chiu fig6 . The motivation to do so is to increase the 2D electron density without sacrificing the mobility (Fan, [24]).
Chiu in view of Fan teaches a n-type modulation doped layer (Chiu, Si backside doping in GaN Channel layer 110 at side 108a, fig6); wherein the n-type modulation doped layer is adjacent the at least one p-type layer (Chiu, Mg doped 108, fig6, [23]) to generate a charge balanced super-heterojunction region (Chiu, 2DEG, fig6).
Re claim 3, Chiu modified above teaches the 2DEG channel of claim 1, wherein: the at least one p-type layer comprises at least two p-type layers (Chiu, 108 as AlGaN/GaN super lattice stack doped with Mg, fig6, [23]); a first p-type layer comprises GaAs, GaN (Chiu, 108 as AlGaN/GaN super lattice stack doped with Mg, fig6, [23]), or GaOx; a second p-type layer comprises AlGaAs, AlGaN (Chiu, 108 as AlGaN/GaN super lattice stack doped with Mg, fig6, [23]), or AlGaOx.
Re claim 4, Chiu modified above teaches the 2DEG channel of claim 1, wherein: p-type dopant for the p-type layer comprises any one or combination of Mg (Chiu, 108 as AlGaN/GaN super lattice stack doped with Mg, fig6, [23]), Li, Na, K,Be, Zn Ca, and Be.
Claim(s) 21-24, 26, 28 and 31 are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. US 2018/0145163 and Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011.
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Re claim 21,Teo teaches a diode (Schottky diode between Schottky anode G1 and Ohmic cathode D1, fig1B), comprising:
a super-heterojunction structure having a charge balance region, the charge balance region comprising:
a passivation layer (18, fig1B, [41]);
an unintentionally doped (UID) spacer layer (17, fig1B, [36]);
an UID barrier layer (15, fig1B, [35]) adjacent the UID spacer layer;
a n-type modulation doped layer (16, fig1B, [35]) between the UID spacer layer and the UID barrier layer;
an UID channel layer (14, fig1B, [34]) adjacent the UID barrier layer; and
a buffer layer (12, fig1B, [32]) adjacent the UID channel layer;
an anode (Schottky electrode G1, fig1B, [40]) and;
a cathode (ohmic contact D1, fig1B, [40]).
Teo does not explicitly show the charge balance region comprising: a p-type layer adjacent the passivation layer; an unintentionally doped (UID) spacer layer adjacent the p-type layer.
Nakajima teaches a p-type layer (p-GaN, fig1); an unintentionally doped (UID) spacer layer (undoped GaN, fig1) adjacent the p-type layer.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Teo and Nakajima to replace T shaped G1 with G in contact with AlGaN layer, B, P-GaN and GaN layer added over AlGaN 17. The motivation to do so is to discharge with both 2DHG and 2DEG during the turn-off period and enhance the breakdown capability of the device (Nakajima, II device structure and behavior).
Teo in view of Nakajima teaches a passivation layer (Teo, 18, fig1B); a p-type layer (Nakajima, p-GaN) adjacent the passivation layer; an unintentionally doped (UID) spacer layer (undoped GaN and UID 17, see figure above) adjacent the p-type layer.
Re claim 22,Teo modified above teaches the diode of claim 21, wherein: the anode is configured as a Schottky contact (G form Schottky contact with UID 17, see figure above) and a p-ohmic contact (B form ohmic contact with P-GaN, see figure above).
Re claim 23, Teo modified above teaches the diode of claim 22, wherein: the Schottky contact forms a Schottky contact (G form Schottky contact with UID 17, see figure above) between the anode (G/B, see figure above) and at least one two- dimensional electron gas channel (2DEG, see figure above).
Re claim 24, Teo modified above teaches the diode of claim 22, wherein: the p-ohmic contact forms an ohmic contact between a p-ohmic metal (B as Ni/Au, see figure above) and the at least one p-type layer (P-GaN, see figure above).
Re claim 26, Teo modified above teaches the diode of claim 22, wherein: the Schottky contact (G, see figure above) and the p-ohmic contact (B, see figure above) are electrically connected.
Re claim 28, Teo modified above teaches the diode of claim 27, wherein: the n-ohmic contact forms a ohmic contact (see figure above) between the cathode (B, see figure above) and at least one two- dimensional electron gas channel (2DEG, see figure above).
Re claim 31, Teo modified above teaches a transistor (see figure above), comprising: at least one diode of claim 21 (Teo, horizontal diode with gate contact corresponds to anode and drain contact corresponds to cathode, see figure above).
Claim(s) 25 is rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. US 2018/0145163 and Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011 and Yu et la. US 2013/0126892.
Re claim 25, Teo does not explicitly show the diode of claim 22, wherein: a p+ layer formed between a p-ohmic metal and the at least one p-type layer.
Yu teaches adding a P+ layer between the metal and P-GaN layer to reduce contact resistance (fig4A, [36]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Teo modified above and Yu to add in a P+ layer between the base metal and P-GaN. The motivation to do so is to reduce contact resistance (Yu, [36]).
Claim(s) 27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. US 2018/0145163 and Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011 and Terano et al. US 2013/0134443.
Re claim 27, Teo does not explicitly show the diode of claim 21, wherein: the cathode is configured as a n-ohmic contact.
Terano teaches forming Cathode electrode (8, fig2, [96]) above n-type layer (12, fig2, [95]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Teo modified above and Terano to add in a n-type layer under ohmic contact metal layer. The motivation to do so is to reduce contact resistance (Terano, [95]).
Re claim 30, Teo does not explicitly show the diode of claim 21, comprising: a p-n junction comprising a p-type region and a n-type region; the anode in electrical connection with the p-type region; the cathode in electrical connection with the n-type region; and the anode is configured as a p-ohmic contact.
Terano teaches forming Cathode electrode (8, fig2, [96]) above n-type layer (12, fig2, [95]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Teo modified above and Terano to add in a n-type layer under ohmic contact metal layer. The motivation to do so is to reduce contact resistance (Terano, [95]).
Teo modified above teaches a p-n junction comprising a p-type region (Nakajima, p-GaN directly under base B, see figure above) and a n-type region (Nakajima, Si implanted in region between S/D and GaN/AlGaN stack, see figure above); the anode in electrical connection with the p-type region (B form ohmic contact with p-GaN and G form Schottky contact, see figure above); the cathode in electrical connection with the n-type region (n-type layer formed under ohmic contact metal layer S/D, see figure above); and the anode is configured as a p-ohmic contact (Nakajima, B form ohmic contact with p-GaN, fig1).
Claim(s) 29 is rejected under 35 U.S.C. 103 as being unpatentable over Teo et al. US 2018/0145163 and Nakajima et al. “GaN-Based Super Heterojunction Field Effect Transistors Using the Polarization Junction Concept” IEEE ELECTRON DEVICE LETTERS, VOL. 32, NO. 4 APRIL 2011 and Wathuthanthri et al. US 2021/0028295.
Re claim 29, Teo does not explicitly show the diode of claim 21, comprising: a plurality of 2DEG channels.
Wathuthanthri teaches stacking plurality of two-material heterostructures with addition of appropriate doping layers to maintain 2DEG channels to achieve greater current flow with low on resistance (fig2, [3,35]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Teo modified above and Wathuthanthri to stack plurality of two-material heterostructures with addition of appropriate doping layers. The motivation to do so is to achieve greater current flow with low on resistance (Wathuthanthri, [3,35]).
Allowable Subject Matter
Claims 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim.
The following is an examiner’s statement of reasons for allowance: currently claim 16-17 include allowable matter because the closest prior art does not appear to disclose, alone or in combination, the limitations related to a notch configured to reduce or eliminate hole conduction between the anode and cathode.
Specifically, the limitations are material to the inventive concept of the application in hand to reduce PN diode leakage by eliminating hole conduction near the cathode.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812