DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 15 and 21 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 15, as currently presented the claim recites “a pixel circuit that outputs a pixel circuit”, in line 2. It is unclear, however, how a pixel circuit can be output by a pixel circuit and the Review of specification, and in particular paragraph [0091] of the specification as published, suggests that the pixel circuit outputs a pixel signal. Accordingly, for purpose of compact prosecution, it will be assumed that a pixel circuit outputs a pixel signal.
With respect to claim 21, as currently presented the claim recites “a transistor” in line 2 and “the transistor” in line 3. The antecedent basis of the recited “the transistor” is unclear. Namely, it is not clear if “the transistor” is referring back to “a transistor” recited in line 2 or “a transistor” recited in claim 1 from which claim 21 depends. For purpose of compact prosecution, it will be assumed that “the transistor” is referring back to the transistor of the logic circuit of the third substrate.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 7-8, 10-17, 20 and 23-24 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Honjo (WO 2020/0121725, hereinafter “Honjo”, cited on IDS and relying on the provided English translation).
Regarding claim 1, Honjo teaches in Fig. 1-5, 20-22, 24-26 and 33-36 (Fig. 24 shown below) an imaging device (100, Fig. 24 and ¶[0078]), comprising:
a first substrate (200, Fig. 24 and ¶[0078]) including one or more sensor pixels (203, Fig. 24 and ¶[0080]) that each perform photoelectric conversion (¶[0080]); and
a second substrate (300, Fig. 24 and ¶[0078]) that is stacked on the first substrate and electrically coupled (Fig. 24) to the first substrate (200, Fig. 24), the second substrate including a transistor (e.g. 310, Fig. 24 and ¶[0106]) that operates in a full depletion mode (¶[0111]).
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Regarding claim 2 (1), Honjo teaches wherein the transistor has a three-dimensional structure (¶¶[0105]-[0111] and [0146]-[0160]).
Regarding claim 7 (1), Honjo teaches wherein the transistor has a gate-all-around (Fig. 33B and ¶[0152]).
Regarding claim 8 (1), Honjo teaches wherein the first substrate (200, Fig. 24) and the second substrate (300, Fig. 24) are electrically coupled through a gate of the transistor or a wiring line formed in a same layer as a layer of the gate (Fig. 24).
Regarding claim 10 (1), Honjo teaches wherein the second substrate (300, Fig. 24) has a first surface provided with a gate (313, Fig. 24) of the transistor (310, Fig. 24) and a second surface opposite to the first surface and the second substrate (300, Fig. 24) is joined to the first substrate with the first surface interposed in between (Fig. 24).
Regarding claim 11 (1), Honjo teaches wherein the second substrate (300, Fig. 24) has a first surface provided with a gate of the transistor (310, Fig. 24 and ¶[0085]) and a second surface opposite to the first surface and the second substrate (300, Fig. 24) is further provided with a multilayer wiring layer (e.g. D1-D3, Fig. 24 and ¶[0088]) on the second surface side (Fig. 24).
Regarding claim 12 (11), Honjo teaches wherein the multilayer wiring layer is provided with at least one of a power supply line, a ground line, a signal line (¶[0096]), a resistance element, a capacitance element, an inductor element, or a memory element.
Regarding claim 13 (11), Honjo teaches wherein the second substrate (300, Fig. 24) further includes a logic circuit block (e.g. 32, Fig. 23 and ¶[0076]),
a power supply line and a ground line are disposed in the multilayer wiring layer (¶[0131]), the power supply line and the ground line being included in the logic circuit block (i.e. lines D1-D3 are in the second substrate that includes logic circuit block, Fig. 24).
Regarding claim 14 (1), Honjo teaches wherein two or more layers each provided with the transistor (310, Fig. 24) are stacked in the second substrate (300, Fig. 24).
Regarding claim 15 (1), Honjo teaches wherein the second substrate (300, Fig. 24) includes a pixel circuit (Fig. 24 and ¶[0085]) that outputs a pixel circuit based on electric charge outputted from the sensor pixel, and the pixel circuit includes the transistor (¶[0085]).
Regarding claim 16 (1), Honjo teaches wherein the second substrate (300, Fig. 18) includes an analog circuit including the transistor (310, Figs. 20-21 and 24 and ¶¶¶[0065] and [0070]).
Regarding claim 17 (1), Honjo further teaches a third substrate (400, Fig. 24 and ¶[0091]) including a logic circuit (e.g. logic transistors Tr, Fig. 24 and ¶[0091]).
Regarding claim 20 (17), Honjo teaches wherein the logic circuit includes a memory section (e.g. 34D, Figs. 20-21 and ¶[0067]).
Regarding claim 23 (10), Honjo further teaches a third substrate (400, Fig. 24 and ¶[0091]) including a logic circuit (e.g. logic transistor Tr, Fig. 24 and ¶[0091]), wherein the third substrate is joined to the second surface of the second substrate by metal bonding (e.g. bonding between wirings of second and third substrates is considered metal to metal bonding, Fig. 24 and ¶[0090].
Regarding claim 24, Honjo teaches in Figs. 24 and 41 (Fig. 24 shown above) an electronic apparatus (Fig. 41 and ¶[0203]), comprising an imaging device (e.g. 12101, Fig. 41 and ¶[0204] and 100, Fig. 24 and ¶[0078]), including;
a first substrate (200, Fig. 24 and ¶[0078]) including one or more sensor pixels (203, Fig. 24 and ¶[0080]) that each perform photoelectric conversion (¶[0080]); and
a second substrate (300, Fig. 24 and ¶[0078]) that is stacked on the first substrate, the second substrate including a transistor (e.g. 310, Fig. 24 and ¶[0106]) that operates in a full depletion mode (¶[0111]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honjo as applied to claim 17 above.
Regarding claim 19 (17), teaching of Honjo was discussed above in the rejection of claim 17 and includes a third substrate (400, Fig. 24 and ¶[0091]) including a logic circuit (e.g. logic transistors Tr, Fig. 24 and ¶[0091]). While Honjo does not explicitly teach that the logic circuit includes a plurality of logic sections having different technology nodes, Honjo teaches, throughout the specification, that different components of the imaging device can be formed using different technology nodes (e.g. FD-SOI or GAA, ¶¶[0151]-[0152]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use different technology in the plurality of logic sections of the logic circuit disclosed by Honjo, as doing so would amount to nothing more than selecting appropriate technology node for a particular application and/or for meeting specific design requirements.
Regarding claim 21 (17), teaching of Honjo was discussed above in the rejection of claim 17 and includes a third substrate (400, Fig. 24 and ¶[0091]) including a logic circuit wherein the logic circuit includes a transistor (e.g. logic transistor TR, Fig. 24 and ¶[0091]). While Honjo does not explicitly teach using a lower power supply voltage for the transistor of the logic circuit than for the transistor, Honjo teaches that different power supply voltages are used in the imaging device (¶[0131]). Accordingly, selecting a power supply line from among the power supply lines disclosed by Honjo for the transistor of the logic circuit and the transistor would amount to nothing more than selecting appropriate power supply voltage for a given transistor in order to meet design/operational requirements for the transistor.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use lower power supply voltage for the transistor of the logic circuit than for the transistor as doing so would amount to nothing more than selecting appropriate power supply voltage for a given transistor in order to meet design/operational requirements for the transistor.
Claim(s) 1-3, 6-9, 14-18, 20, 22 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa et al. (TW 202036878, hereinafter “Yamakawa”, relying on the provided English translation) in view of Hirase et al. (US 2022/0208816, hereinafter “Hirase”).
Regarding claim 1, Yamakawa teaches in Fig. 18 (shown below) an imaging device (10A, Fig. 18 and ¶[0080]), comprising:
a first substrate (11A, Fig. 18 and ¶[0080]) including one or more sensor pixels (21, Fig. 18 and ¶[0080]) that each perform photoelectric conversion (¶[0028]); and
a second substrate (30, Fig. 18 and ¶[0080]) that is stacked on the first substrate and electrically coupled (Fig. 18) to the first substrate (11A, Fig. 18), the second substrate including a transistor (e.g. 24, Fig. 18 and ¶[0080]).
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Yamakawa, however, does not explicitly teach that the transistor operates in a full depletion mode. However, operating transistor disclosed by Yamakawa in a full depletion mode would have been obvious to one of ordinary skill in the art as evidenced by Hirase. Specifically, Hirase teaches that a transistor, such as that disclosed by Yamakawa, can be operated in a full depletion mode in order to lower threshold voltage of the transistor thereby raising the operating efficiency of the imagining device (¶[0275]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the transistor disclosed by Yamakawa in a full depletion mode, as disclosed by Hirase, in order to lower threshold voltage of the transistor thereby raising the operating efficiency of the imaging device.
Regarding claim 2 (1), the combined teaching of Yamakawa and Hirase discloses wherein the transistor has a three-dimensional structure (Yamakawa, ¶¶[0064]-[0066] and [0068]-[0069]).
Regarding claim 3 (1), the combined teaching of Yamakawa and Hirase discloses wherein the transistor has a Fin-FET structure in which the transistor includes a plurality of fins (Yamakawa, e.g. F1-F3, Figs. 19, 20A and ¶[0113]).
Regarding claim 6 (3), the combined teaching of Yamakawa and Hirase discloses wherein the plurality of fins is independent of each other (Yamakawa, Figs. 19 and 20A).
Regarding claim 7 (1), the combined teaching of Yamakawa and Hirase discloses wherein the transistor has a gate-all-around structure (Yamakawa, ¶[0068]).
Regarding claim 8 (1), the combined teaching of Yamakawa and Hirase discloses wherein the first substrate (Yamakawa, 11A, Fig. 18) and the second substrate (Yamakawa, 30, Fig. 18) are electrically coupled through a gate of the transistor (Yamakawa, 24G, Fig. 18) or a wiring line formed in a same layer as a layer of the gate.
Regarding claim 9 (1), the combined teaching of Yamakawa and Hirase discloses wherein the second substrate (Yamakawa, 30, Fig. 18) has a first surface (Yamakawa, e.g. top surface in Fig. 18) provided with a gate (Yamakawa, 24G, Fig. 18) of the transistor (Yamakawa, 24, Fig. 18) and a second surface opposite to the first surface and the second substrate (Yamakawa, 30, Fig. 18) is joined to the first substrate (Yamakawa, 11A, Fig. 18) with the second surface interposed in between (Yamakawa, Fig. 18).
Regarding claim 14 (1), the combined teaching of Yamakawa and Hirase discloses wherein two or more layers (Yamakawa, e.g. layers 30S and 30I, Figs. 18 and 20A) each provided with the transistor are stacked in the second substrate (Yamakawa, 30, Figs. 18 and 20A).
Regarding claim 15 (1), the combined teaching of Yamakawa and Hirase discloses wherein the second substrate (Yamakawa, 30, Fig. 18) includes a pixel circuit (Yamakawa, e.g. 24, 25, Fig. 18 and ¶¶[0112]) that outputs a pixel circuit based on electric charge outputted from the sensor pixel, and the pixel circuit includes the transistor (¶[0030]).
Regarding claim 16 (1), the combined teaching of Yamakawa and Hirase discloses wherein the second substrate (30, Fig. 18) includes an analog circuit including the transistor (Yamakawa, e.g. 13, Fig. 39 and ¶[0023]).
Regarding claim 17 (1), the combined teaching of Yamakawa and Hirase further discloses a third substrate (Yamakawa, 40, Figs. 18 and 39) including a logic circuit (Yamakawa, ¶[0080]).
Regarding claim 18 (17), the combined teaching of Yamakawa and Hirase discloses
wherein a circuit including the transistor of the second substrate (Yamakawa, 30, Fig. 18) and the logic circuit of the third substrate (Yamakawa, 40, Fig. 18) are each provided for each of the sensor pixels (Yamakawa, P, Figs. 18 and 39 and ¶[0082]).
Regarding claim 20 (17), the combined teaching of Yamakawa and Hirase discloses wherein the logic circuit includes a memory section (Yamakawa, ¶[0188]).
Regarding claim 22 (9), the combined teaching of Yamakawa and Hirase discloses further comprising a third substrate (Yamakawa, 40, Fig. 18) including a logic circuit (¶[0080]), wherein the third substrate is joined to the first surface of the second substrate by metal bonding (¶[0108]).
Regarding claim 24, Yamakawa teaches in Figs. 18 and 48 (Fig. 18 shown above) an electronic apparatus (Fig. 48 and ¶¶[0274]-[0276]), comprising an imaging device (e.g. 12101, Fig. 48), including;
a first substrate (11A, Fig. 18 and ¶[0080]) including one or more sensor pixels (21, Fig. 18 and ¶[0080]) that each perform photoelectric conversion (¶[0028]); and
a second substrate (30, Fig. 18 and ¶[0080]) that is stacked on the first substrate, the second substrate including a transistor (24, Fig. 18 and ¶[0080]).
Yamakawa, however, does not explicitly teach that the transistor operates in a full depletion mode. However, operating transistor disclosed by Yamakawa in a full depletion mode would have been obvious to one of ordinary skill in the art as evidenced by Hirase. Specifically, Hirase teaches that a transistor such as that disclosed by Yamakawa can be operated in a full depletion mode in order to lower threshold voltage of the transistor thereby raising the operating efficiency of the imagining device (¶[0275]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the transistor disclosed by Yamakawa in a full depletion mode, as disclosed by Hirase, in order to lower threshold voltage of the transistor thereby raising the operating efficiency of the imaging device.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa and Hirase as applied to claim 3 above, and further in view of Cho (US 2009/0108353, hereinafter “Cho”).
Regarding claim 4 (3), the combined teaching of Yamakawa and Hirase was discussed above in the rejection of claim 3 and includes wherein the transistor has a Fin-FET structure that includes a plurality of fins. While Yamakawa and Hirase do not explicitly teach that the plurality of fins is coupled to each other by a semiconductor layer having a thickness of 1 um or less, coupling the plurality of fins disclosed by Yamkawa and Hirase through a semiconductor layer would have been obvious to one of ordinary skill in the art as evidenced by Cho (Figs. 1-2 and ¶¶[0014]-[0018]), in order to increase total channel with of the transistor (¶¶[0010] and [0017]). Specifically, Cho teaches that Fin-FET structure, such as that disclosed by Yamakawa and Hirase, can be formed either by having plurality of fins independent of each other (Fig. 1) or coupled to each other by a semiconductor layer having a thickness of 1 µm or less (Fig. 2 and ¶[0018]) in order to form a device with desired characteristics.
Accordingly, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the plurality of fins to each other by a semiconductor layer having a thickness so 1 µm or less, as disclosed by Cho in order to form a device with desired characteristics.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa, Hirase and Cho as applied to claim 4 above, and further in view of Ammo (US 2014/0327059, hereinafter “Ammo”, cited on IDS).
Regarding claim 5 (4), the combined teaching of Yamakawa, Hirase and Cho was discussed above in the rejection of claim 4. Yamakawa, Hirase and Cho, however, do not explicitly teach that no ions is implanted into the semiconductor layer. Ammo, in a similar field of endeavor teaches that the semiconductor layer (Figs. 3-4), similar to that disclosed by Yamakawa, Hirase and Cho can be either implanted or intrinsic (i.e. not implanted) semiconductor (¶¶[0053]-[0054]) in order to meet specific design requirements for the Fin-FET transistor.
Accordingly, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the plurality of fins by a semiconductor layer into which no ions are implanted (i.e. intrinsic semiconductor layer) in order to meet specific design requirements for the Fin-FET transistor.
Relevant Prior Art
The following prior art is relevant to the invention but not relied upon in any of the rejections:
Joshi et al. (US 2008/0079704) teaches in Figs. 1-3 an imaging device (104, Fig. 1 and ¶[0041]), comprising a first substrate (102, Fig. 1 and ¶[0042]) including one or more sensor pixels (104, Fig. 1 and ¶[0041]) that each perform photoelectric conversion (¶¶[0004]-[0010]); and a second substrate (100, Fig. 1 and ¶[0040]) that is stacked on the first substrate and electrically coupled (106, Fig. 1 and ¶[0041]) to the first substrate, the second substrate including a transistor that operates in a full depletion mode (¶¶[0016] and [0051]-[00054]).
Conclusion
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/A.B.C/
Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893