DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendment filed on March 25, 2026 has been entered. Claim(s) 17, 22 and 23 has/have been canceled and claim(s) 25-27 has/have been added. Therefore, claim(s) 1-16, 18-21 and 24-27 are pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 7-8, 11-16, 20 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honjo (WO 2020/0121725, hereinafter “Honjo”, previously cited) in view of Horikoshi (WO 2020/137334, hereinafter “Horikoshi”, relying on the provided English translation) with Kitano (US 2015/0029374, hereinafter “Kitano”) relied for as evidentiary reference showing the elements disclosed by Honjo are considered part of a logic circuit block recited in claim 13.
Regarding claim 1, Honjo teaches in Fig. 1-5, 20-22, 24-26 and 33-36 (Fig. 24 shown below) an imaging device (100, Fig. 24 and ¶[0078]), comprising:
a logic circuit (Tr of 400, Fig. 24 and ¶[0144]);
a first substrate (200, Fig. 24 and ¶[0078]) including one or more sensor pixels (203, Fig. 24 and ¶[0080]) that each perform photoelectric conversion (¶[0080]); and
a second substrate (300, Fig. 24 and ¶[0078]) that is stacked on the first substrate and electrically coupled (Fig. 24) to the first substrate (200, Fig. 24), the second substrate including a transistor (e.g. 310, Fig. 24 and ¶[0106]) that operates in a full depletion mode (¶[0111]); and
a third substrate stacked on, and electrically couple to, the second substrate wherein the third substrate includes:
the logic circuit (Tr, Fig. 24 and ¶[0143]).
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Honjo, however, does not explicitly teach that the third substrate also includes a memory comprising dynamic random access memory (DRAM) and, as a result that the logic circuit is electrically couple to the memory.
Harikoshi, teaches in Fig. 1 and related text, that the third substrate, similar to that disclosed by Honjo, which includes a plurality of logic transistors may additionally include a DRAM memory (¶[0064]) in order to store information collected and processed by the imaging device.
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art to include, in the third substrate disclosed by Honjo, a memory comprising dynamic random access memory (DRAM), as disclosed by Harikoshi, in order to store information collected and processed by the imaging device.
Regarding claim 2 (1), the combined teaching of Honjo and Harikoshi discloses wherein the transistor has a three-dimensional structure (Honjo, ¶¶[0105]-[0111] and [0146]-[0160]).
Regarding claim 7 (1), the combined teaching of Honjo and Harikoshi discloses wherein the transistor has a gate-all-around (Honjo, Fig. 33B and ¶[0152]).
Regarding claim 8 (1), Honjo and Harikoshi discloses wherein the first substrate (Honjo, 200, Fig. 24) and the second substrate (Honjo, 300, Fig. 24) are electrically coupled through a gate of the transistor or a wiring line formed in a same layer as a layer of the gate (Honjo, Fig. 24).
Regarding claim 11 (1), the combined teaching of Honjo and Harikoshi discloses wherein the second substrate (Honjo, 300, Fig. 24) has a first surface provided with a gate of the transistor (Honjo, 310, Fig. 24 and ¶[0085]) and a second surface opposite to the first surface, and wherein the second substrate (300, Fig. 24) is further provided with a multilayer wiring layer (Honjo, e.g. D1-D3, Fig. 24 and ¶[0088]) on a side of the second surface (Honjo, Fig. 24).
Regarding claim 12 (11), the combined teaching of Honjo and Harikoshi discloses wherein the multilayer wiring layer is provided with at least one of a power supply line, a ground line, a signal line (Honjo, ¶[0096]), a resistance element, a capacitance element, an inductor element, or a memory element.
Regarding claim 13 (11), the combined teaching of Honjo and Harikoshi discloses wherein the second substrate (Honjo, 300, Fig. 24) further includes a logic circuit block (Honjo, ¶[0076]) that includes another logic circuit (i.e. where it is noted that transistors 310, 320 and selection transistor disclosed by Honjo (¶[0085]) are considered as being part of a logic circuit block as evidenced by Kitano, ¶¶[0107] and [0112]),
a power supply line and a ground line are disposed in the multilayer wiring layer (Honjo, ¶[0131]), the power supply line and the ground line being included in the logic circuit block (i.e. lines D1-D3 are in the second substrate that includes logic circuit block, Fig. 24).
Regarding claim 14 (1), the combined teaching of Honjo and Harikoshi discloses wherein two or more layers each provided with the transistor (Honjo, 310, Fig. 24) are stacked in the second substrate (Honjo, 300, Fig. 24).
Regarding claim 15 (1), the combined teaching of Honjo and Harikoshi discloses wherein the second substrate (Honjo, 300, Fig. 24) includes a pixel circuit (Honjo, Fig. 24 and ¶[0085]) that outputs a pixel signal based on electric charge outputted from the sensor pixel, and the pixel circuit includes the transistor (Honjo, ¶[0085]).
Regarding claim 16 (1), the combined teaching of Honjo and Harikoshi discloses wherein the second substrate (Honjo, 300, Fig. 18) includes an analog circuit including the transistor (Honjo, 310, Figs. 20-21 and 24 and ¶¶¶[0065] and [0070]).
Regarding claim 20 (1), the combined teaching of Honjo and Harikoshi discloses wherein the logic circuit includes a memory section (Harikoshi, e.g. non-volatile memory, ¶[0064]).
Regarding claim 24, Honjo teaches in Figs. 24 and 41 (Fig. 24 shown above) an electronic apparatus (Fig. 41 and ¶[0203]), comprising an imaging device (e.g. 12101, Fig. 41 and ¶[0204] and 100, Fig. 24 and ¶[0078]), including;
a logic circuit (Tr of 400, Fig. 24 and ¶[0144]);
a first substrate (200, Fig. 24 and ¶[0078]) including one or more sensor pixels (203, Fig. 24 and ¶[0080]) that each perform photoelectric conversion (¶[0080]);
a second substrate (300, Fig. 24 and ¶[0078]) that is stacked on the first substrate, the second substrate including a transistor (e.g. 310, Fig. 24 and ¶[0106]) that operates in a full depletion mode (¶[0111]); and
a third substrate stacked on, and electrically couple to, the second substrate wherein the third substrate includes:
the logic circuit (Tr, Fig. 24 and ¶[0143]).
Honjo, however, does not explicitly teach that the third substrate also includes a memory comprising at least one of dynamic random access memory (DRAM) and magnetoresistive random access memory (MRAM), and as a result that the logic circuit is electrically couple to the memory.
Harikoshi, teaches in Fig. 1 and related text, that the third substrate, similar to that disclosed by Honjo, which includes a plurality of logic transistors may additionally include a DRAM memory (¶[0064]) in order to store information collected and processed by the imaging device.
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art to include, in the third substrate disclosed by Honjo, a memory comprising dynamic random access memory (DRAM), as disclosed by Harikoshi, in order to store information collected and processed by the imaging device.
Claim(s) 19 and 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honjo and Harikoshi as applied to claim 1 above.
Regarding claim 19 (17), the combined teaching of Honjo and Harikoshi was discussed above in the rejection of claim 1 and includes a third substrate (400, Fig. 24 and ¶[0091]) including a logic circuit (e.g. logic transistors Tr, Fig. 24 and ¶[0091]). While Honjo and Harikoshi do not explicitly teach that the logic circuit includes a plurality of logic sections having different technology nodes, Honjo teaches, throughout the specification, that different components of the imaging device can be formed using different technology nodes (e.g. FD-SOI or GAA, ¶¶[0151]-[0152]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use different technology in the plurality of logic sections of the logic circuit disclosed by Honjo and Harikoshi, as doing so would amount to nothing more than selecting appropriate technology node for a particular application and/or for meeting specific design requirements.
Regarding claim 21 (1), the combined teaching of Honjo and Harikoshi was discussed above in the rejection of claim 1 and includes a third substrate (400, Fig. 24 and ¶[0091]) including a logic circuit wherein the logic circuit includes a transistor (e.g. logic transistor TR, Fig. 24 and ¶[0091]). While Honjo and Harikoshi do not explicitly teach using a lower power supply voltage for the transistor of the logic circuit than for the transistor of the second substrate, Honjo teaches that different power supply voltages are used in the imaging device (¶[0131]). Accordingly, selecting a power supply line from among the power supply lines disclosed by Honjo and Harikoshi for the transistor of the logic circuit and the transistor would amount to nothing more than selecting appropriate power supply voltage for a given transistor in order to meet design/operational requirements for the transistor.
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use lower power supply voltage for the transistor of the logic circuit than for the transistor as doing so would amount to nothing more than selecting appropriate power supply voltage for a given transistor in order to meet design/operational requirements for the transistor.
Claim(s) 25 is/are rejected under 35 U.S.C. 103 as being unpatentable Honjo and Harikoshi as applied to claim 1 above, and further in view of Lim et al. (US 2013/0141619, hereinafter “Lim”).
Regarding claim 25 (1), the combined teaching of Honjo and Harikoshi was discussed above and include wherein the memory comprises DRAM (Harikoshi, ¶[0064]). While Honjo and Harikoshi do not explicitly teach that the memory is a MRAM memory, using MRAM in place of DRAM as disclosed by Harikoshi would have been obvious to one of ordinary skill in the art as the two types of memory where art recognized equivalent memory device types for use in image sensors, as evidenced by Lim (¶[0130]).
Thus, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute MRAM for DRAM in the imaging device disclosed by Honjo and Harikoshi as the two memories were art recognized equivalents.
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable Honjo and Harikoshi as applied to claim 1 above, and further in view of Yamakawa et al. (WO, hereinafter “Yamakawa”, previously cited) with Kitano (US 2015/0029374, hereinafter “Kitano”) relied for as evidentiary reference showing the elements disclosed by Honjo are considered another logic circuit.
Regarding claim 26 (1), the combined teaching of Honjo and Harikoshi discloses wherein the second substrate includes another logic circuit (Honjo, Fig. 24 shows another logic circuit (310, 320 and selection transistor) disclosed by Honjo (¶[0085]) are considered as being part of a logic circuit block as evidenced by Kitano, ¶¶[0107] and [0112])), electrically couple to the memory (Honjo, i.e. third substrate 400, Fig. 24 as modified by Harikoshi, coupled by D3, 402, Fig. 24).
While Honjo and Harikoshi do not explicitly teach that the second substrate and the memory of the third substrate are coupled using metal bonding, using metal bonding, to connect the second substrate and the third substrate that includes the memory disclosed by Honjo and Harikoshi would have been within capabilities of one of ordinary skill in the art as evidenced by Yamakawa. Specifically, Yamakawa discloses that bonding similar to that disclosed by Honjo (D3 and 402, Fig. 24) involves metal bonding (Yamakawa 33, 43, Fig. 18 and ¶[0105] and [0108]).
Thus, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results and, as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invitation to use metal bonding, as disclosed by Yamakawa, to connect the second substrate and the third substrate that includes the memory disclosed by Honjo and Harikoshi in order to connect two substrates together so as to form a fully functional imaging device.
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honjo (WO 2020/0121725, hereinafter “Honjo”, previously cited) in view of Yokoyama et al. (WO 2017/038403, hereinafter “Yokoyama”, relying on the provided English translation) and Dabiri et al. (US 2012/0014487, hereinafter “Dabiri”).
Regarding claim 27, Honjo teaches in Fig. 1-5, 20-22, 24-26 and 33-36 (Fig. 24 shown above) an imaging device (100, Fig. 24 and ¶[0078]), comprising:
a first substrate (200, Fig. 24 and ¶[0078]) including one or more sensor pixels (203, Fig. 24 and ¶[0080]) that each perform photoelectric conversion (¶[0080]); and
a second substrate (300, Fig. 24 and ¶[0078]) that is stacked on the first substrate and electrically coupled (Fig. 24) to the first substrate (200, Fig. 24), the second substrate including a transistor (e.g. 310, Fig. 24 and ¶[0106]) that operates in a full depletion mode (¶[0111]); and
a third substrate (400, Fig. 24 and ¶[0131]) stacked on, and electrically coupled to, the second substrate,
Honjo, however, does not explicitly teach that the second substrate further includes latch memory for storing readout data corresponding to photoelectric conversion by the one or more sensor pixels.
To begin with Yokoyama, in a similar field of endeavor, teaches in Fig. 18 and related text that in an imaging device, similar to that disclosed by Honjo, the second substrate may include a memory device for storing readout data corresponding to photoelectric conversion by the one or more sensor pixels (¶[0076]), and Dabiri teaches that MTJ, DRAM and SRAM disclosed by Yokoyama and latch memory, as claimed, are art recognized equivalent memories for storing information (¶[0056]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include a latch memory device in the second substrate of Honjo, as disclosed by Yokoyama and Dabiri, as doing so would amount to nothing more than using an imaging device design and memory element known in the art for storing readout data corresponding to photoelectric conversion by the one or more sensor pixels.
Claim(s) 1-3, 6-11, 14-16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa et al. (TW 202036878, hereinafter “Yamakawa”, previously cited) in view of Hirase et al. (US 2022/0208816, hereinafter “Hirase”, previously cited) and Harikoshi (WO 2020/137334, hereinafter “Horikoshi”, relying on the provided English translation).
Regarding claim 1, Yamakawa teaches in Fig. 18 (shown below) an imaging device (10A, Fig. 18 and ¶[0080]), comprising:
a logic circuit (LC, Fig. 18 and ¶¶[0080] and [0111]);
a first substrate (11A, Fig. 18 and ¶[0080]) including one or more sensor pixels (21, Fig. 18 and ¶[0080]) that each perform photoelectric conversion (¶[0028]); and
a second substrate (30, Fig. 18 and ¶[0080]) that is stacked on the first substrate and electrically coupled (Fig. 18) to the first substrate (11A, Fig. 18), the second substrate including a transistor (e.g. 24, Fig. 18 and ¶[0080]); and
a third substrate (40, Fig. 18 and ¶[]) on, and electrically couple to, the second substrate, wherein the third substrate includes the logic circuit (LC, Fig. 18 and ¶[0111]).
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Yamakawa, however, does not explicitly teach that the transistor operates in a full depletion mode and that the third substrate includes a memory comprising dynamic random access memory (DRAM).
First, operating transistor disclosed by Yamakawa in a full depletion mode would have been obvious to one of ordinary skill in the art as evidenced by Hirase. Specifically, Hirase teaches that a transistor, such as that disclosed by Yamakawa, can be operated in a full depletion mode in order to lower threshold voltage of the transistor thereby raising the operating efficiency of the imagining device (¶[0275]).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to operate the transistor disclosed by Yamakawa in a full depletion mode, as disclosed by Hirase, in order to lower threshold voltage of the transistor thereby raising the operating efficiency of the imaging device.
Second, Harikoshi, teaches in Fig. 1 and related text, that the third substrate, similar to that disclosed by Yamakawa and Hirase, which includes a plurality of logic transistors may additionally include a DRAM memory (¶[0064]) in order to store information collected and processed by the imaging device.
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art to include, in the third substrate disclosed by Yamakawa and Hirase, a memory comprising dynamic random access memory (DRAM), as disclosed by Harikoshi, in order to store information collected and processed by the imaging device.
Regarding claim 2 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the transistor has a three-dimensional structure (Yamakawa, ¶¶[0064]-[0066] and [0068]-[0069]).
Regarding claim 3 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the transistor has a Fin-FET structure in which the transistor includes a plurality of fins (Yamakawa, e.g. F1-F3, Figs. 19, 20A and ¶[0113]).
Regarding claim 6 (3), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the plurality of fins is independent of each other (Yamakawa, Figs. 19 and 20A).
Regarding claim 7 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the transistor has a gate-all-around structure (Yamakawa, ¶[0068]).
Regarding claim 8 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the first substrate (Yamakawa, 11A, Fig. 18) and the second substrate (Yamakawa, 30, Fig. 18) are electrically coupled through a gate of the transistor (Yamakawa, 24G, Fig. 18) or a wiring line formed in a same layer as a layer of the gate.
Regarding claim 9 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the second substrate (Yamakawa, 30, Fig. 18) has a first surface (Yamakawa, e.g. top surface in Fig. 18) provided with a gate (Yamakawa, 24G, Fig. 18) of the transistor (Yamakawa, 24, Fig. 18) and a second surface opposite to the first surface and the second substrate (Yamakawa, 30, Fig. 18) is joined to the first substrate (Yamakawa, 11A, Fig. 18) with the first surface or the second surface interposed in between (Yamakawa, Fig. 18).
Regarding claim 10 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the second substrate (Yamakawa, 30, Fig. 18) has a first surface provided with a gate (Yamakawa, 24G, Fig. 18) of the transistor (Yamakawa, 24, Fig. 18) and a second surface opposite to the first surface (Yamakawa, i.e. surface of semiconductor layer 30S closest to 11A, Fig. 18), and wherein one of:
the second substrate (Yamakawa, 30, Fig. 18) is joined to the first substrate (Yamakawa, 11A, Fig. 18) is joined to the first substrate (Yamakawa, 11A, Fig. 18) with the second surface interposed in between (Yamakawa, Fig. 18) and the third substrate (Yamakawa, 40, Fig. 18) is joined to the first surface of the second substrate by metal bonding (Yamakawa 33, 43, Fig. 18 and ¶[0105] and [0108]).
Regarding claim 11 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the second substrate (Yamakawa, 30, Fig. 18) has a first surface provided with a gate (Yamakawa, 24G, Fig. 18 and ¶[0103]) of the transistor (Yamakawa, 24, Fig. 18 and ¶[0103]) and a second surface (Yamakawa, i.e. bottom of 30S in contact with 11A, Fig. 18) opposite to the first surface, and wherein the second substrate (Yamakawa 30, Fig. 18) is further provided with a multilayer wiring layer (Yamakawa, 31-33, Fig. 18 and ¶[0105]) on a side of the second surface (Yamakawa, Fig. 18).
Regarding claim 14 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein two or more layers (Yamakawa, e.g. layers 30S and 30I, Figs. 18 and 20A) each provided with the transistor are stacked in the second substrate (Yamakawa, 30, Figs. 18 and 20A).
Regarding claim 15 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the second substrate (Yamakawa, 30, Fig. 18) includes a pixel circuit (Yamakawa, e.g. 24, 25, Fig. 18 and ¶¶[0112]) that outputs a pixel signal based on electric charge outputted from the sensor pixel, and the pixel circuit includes the transistor (¶[0030]).
Regarding claim 16 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the second substrate (30, Fig. 18) includes an analog circuit including the transistor (Yamakawa, e.g. 13, Fig. 39 and ¶[0023]).
Regarding claim 18 (1), the combined teaching of Yamakawa, Hirase and Harikoshi discloses
wherein a circuit including the transistor of the second substrate (Yamakawa, 30, Fig. 18) and the logic circuit of the third substrate (Yamakawa, 40, Fig. 18) are each provided for each of the sensor pixels (Yamakawa, P, Figs. 18 and 39 and ¶[0082]).
Regarding claim 20 (17), the combined teaching of Yamakawa, Hirase and Harikoshi discloses wherein the logic circuit includes a memory section (Yamakawa, ¶[0188]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa, Hirase and Harikoshi as applied to claim 3 above, and further in view of Cho (US 2009/0108353, hereinafter “Cho”, previously cited).
Regarding claim 4 (3), the combined teaching of Yamakawa, Hirase and Harikoshi was discussed above in the rejection of claim 3 and includes wherein the transistor has a Fin-FET structure that includes a plurality of fins. While Yamakawa, Hirase and Harikoshi do not explicitly teach that the plurality of fins is coupled to each other by a semiconductor layer having a thickness of 1 um or less, coupling the plurality of fins disclosed by Yamakawa, Hirase and Harikoshi through a semiconductor layer would have been obvious to one of ordinary skill in the art as evidenced by Cho (Figs. 1-2 and ¶¶[0014]-[0018]), in order to increase total channel with of the transistor (¶¶[0010] and [0017]). Specifically, Cho teaches that Fin-FET structure, such as that disclosed by Yamakawa, Hirase and Harikoshi, can be formed either by having plurality of fins independent of each other (Fig. 1) or coupled to each other by a semiconductor layer having a thickness of 1 µm or less (Fig. 2 and ¶[0018]) in order to form a device with desired characteristics.
Accordingly, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the plurality of fins to each other by a semiconductor layer having a thickness so 1 µm or less, as disclosed by Cho in order to form a device with desired characteristics.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamakawa, Hirase, Harikoshi and Cho as applied to claim 4 above, and further in view of Ammo (US 2014/0327059, hereinafter “Ammo”, previously cited).
Regarding claim 5 (4), the combined teaching of Yamakawa, Hirase, Harikoshi and Cho was discussed above in the rejection of claim 4. Yamakawa, Hirase, Harikoshi and Cho, however, do not explicitly teach that no ions is implanted into the semiconductor layer. Ammo, in a similar field of endeavor teaches that the semiconductor layer (Figs. 3-4), similar to that disclosed by Yamakawa, Hirase, Harikoshi and Cho can be either implanted or intrinsic (i.e. not implanted) semiconductor (¶¶[0053]-[0054]) in order to meet specific design requirements for the Fin-FET transistor.
Accordingly, since the prior art teaches all of the claimed elements using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to couple the plurality of fins by a semiconductor layer into which no ions are implanted (i.e. intrinsic semiconductor layer) in order to meet specific design requirements for the Fin-FET transistor.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 24 and 27 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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