DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 08/06/2026 has been entered.
Response to Amendment
The amendment with respect to claim(s) 1, 16, and 18 filed on 10/2/2026 have been fully considered for examination based on their merits. The previously presented claim(s) [2-13, and 19-23 have been considered. Claim(s) 14, 15, and 17 are canceled.
Response to Arguments
Applicant’s arguments, see Remarks, pages 7-10, filed 07/07/2026, with respect to the rejection(s) of claim(s) 1-13, 16, and 18-23 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LEE.
Regarding Claim 1. The Applicant argues (see Remarks, page 9) that the cited art fails to disclose or suggest at least, “a solid-state imaging device, comprising: an element isolation insulation film surrounding each of the first and second pixels, wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view.” The Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior-art of LEE (Figures 3-4) teaches a solid-state imaging device, comprising: an element isolating layer, 150 may be disposed in the active pixel sensor array region, APS (see Figure 3) to define the active pixel, AP (see Figure 3) or the reference pixel, RP (see Figure 3) [0064]. The element isolating layer, 150 may be formed by patterning the substrate, 100 to form a deep trench, and then filling the deep trench with an insulative material [0065]. Figure 4 is a cross-sectional view illustrating an image sensor, wherein the element isolating layer, 150 has forward tapered shape or profile.
Regarding Claims 2-13, 16, 18-23: The independent Claim(s) 16, and 18, and dependent claims 1-13, and 19-23 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ryoto Yoshita et al, (hereinafter YOSHITA), WO 2018163732 A1, in view of Katsunori Hiramatsu, (hereinafter HIRAMATSU), WO 2019093150 A1, Sozo Yokokawa et al, (hereinafter YOKOKAWA), JP 2018195908 A, and Yun Ki Lee et al, (hereinafter LEE), US 20190259787 A1.
Regarding Claim 1, YOSHITA teaches in Figure 14, a solid-state imaging device (Fig. 14, 1B, [0060]), comprising:
a first pixel (annotated Figure 14, P, [0060-0061]);
a second pixel (annotated Figure 14, P, [0060-0061]) located in a first direction (annotated Figure 14 or L1 direction) of the first pixel,
wherein each of the first and second pixels includes a first transistor (Fig. 14, 21, second transfer transistor) and a second transistor (Fig. 14, 22, reset transistor), and
wherein the first and second transistors in the second pixel are disposed in the first direction with respect to the first and second transistors in the first pixel (annotated Figure 14).
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Though YOSHITA teaches a solid-state imaging device, comprising: wherein the first and second transistors are disposed in the first direction with respect to the first and second transistors in the first pixel, YOSHITA does not explicitly disclose a solid state imaging device comprising: the first and second transistors in the second pixel are disposed periodically in the first direction with respect to the first and second transistors in the first pixel.
HIRAMATSU teaches in Figures 2-4, a solid state imaging device (Fig. 2, 12, imaging device) comprising: wherein the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the second pixel (annotated Figure 4; 110, pixel) are disposed periodically in the first direction (annotated Figure 4) with respect to the first and second transistors in the first pixel (annotated Figure 4; 110, pixel).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YOSHITA to incorporate the teachings of HIRAMATSU such that a solid state imaging device comprising: wherein the first and second transistors in the second pixel are disposed periodically in the first direction with respect to the first and second transistors in the first pixel, so that the plan view of nine 3×3 pixels 110 arranged in the pixel array section 41 (FIG. 2) as viewed from the front side (the upper side in FIG. 3), and FIG. 5 is a circuit diagram for explaining the connection relationship of each transistor shown in FIG. 4 (HIRAMATSU, [0055]).
YOSHITA as modified by HIRAMATSU does not explicitly disclose a solid-state imaging device, comprising: an element isolation insulation film surrounding each of the first and second pixels, wherein the element isolation insulation film has either a forward tapered shape or a reverse tapered shape in a cross-sectional view.
YOKOKAWA teaches a solid-state imaging device (Figs. 7/11, 100a/100b, image sensor), comprising:
an element isolation insulation film (Fig. 37, 21214/21215, first/second insulating film) surrounding each of the first and second pixels (Fig. 37, 21200),
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by HIRAMATSU to incorporate the teachings of YOKOKAWA such that a solid state imaging device comprising: an element isolation insulation film surrounding each of the first and second pixels, so that the a trench-shaped element isolation portion, 232 extending from the incident surface of the semiconductor substrate, 103 is formed between adjacent pixels, 201a (YOKOKAWA, Figure 37).
YOSHITA as modified by HIRAMATSU, and YOKOKAWA does not explicitly disclose a solid state imaging device comprising: wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view.
LEE teaches a solid state imaging device (Fig. 4, 1, image sensor) comprising: wherein the element isolation insulation film (Fig. 4, 150, element isolating layer) has a forward tapered shape in a cross-sectional view (annotated Figure 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by HIRAMATSU, and YOKOKAWA to incorporate the teachings of LEE such that a solid state imaging device comprising: wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view, so that a first element isolating layer, 150 may surround the active pixel, AP or the reference pixel, RP and be extended from the lower surface to the upper surface of the substrate, 100 to form a deep trench, to manufacture the image sensor with improved reliability (LEE, [0005], [0070]).
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Regarding Claim 2, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 1.
YOSHITA further teaches in Figure 14, the solid-state imaging device (Fig. 14, 1B, [0060]) according to claim 1, further comprising:
a third pixel located in a second direction (annotated Figure 14 or L2 direction) of the first pixel; and
a fourth pixel located in the second direction (annotated Figure 14 or L2 direction) of the second pixel,
wherein each of the first and second pixels includes a first transistor (Fig. 14, 21, second transfer transistor) and a second transistor (Fig. 14, 22, reset transistor), and
wherein the first and second transistors in the fourth pixel are disposed in the first direction with respect to the first and second transistors in the third pixel (annotated Figure 14).
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HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device) according to claim 1, further comprising: the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistor in the fourth pixel (annotated Figure 4; 110, pixel) are disposed periodically in the first direction (annotated Figure 4) with respect to the first and second transistors in the third pixel (annotated Figure 4; 110, pixel).
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Regarding Claim 3, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 2.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the third pixel (annotated Figure 4; 110, pixel) are disposed symmetrically in the second direction (annotated Figure 4) with respect to the first and second transistors in the first pixel (annotated Figure 4; 110, pixel), and/or
wherein the first (Fig. 4, 190, transfer transistor) and second transistors Fig. 4, 194, selection transistor) in the fourth pixel (annotated Figure 4; 110, pixel) are disposed symmetrically in the second direction (annotated Figure 4) with respect to the first and second transistors in the second pixel (annotated Figure 4; 110, pixel).
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Regarding Claim 4, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 2.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the third pixel are disposed periodically in the second direction (annotated Figure 4) with respect to the first and second transistors in the first pixel (annotated Figure 4; 110, pixel), and/or
wherein the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the fourth pixel are disposed periodically in the second direction (annotated Figure 4) with respect to the first and second transistors in the second pixel (annotated Figure 4; 110, pixel).
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Regarding Claim 5, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 1.
YOSHITA further teaches in Figures 18A-18B, the solid-state imaging device (Fig. 14, 1B, [0060]),
wherein each of the first (annotated Figure 18A) and second (annotated Figure 18A) pixels includes a photoelectric conversion unit (Fig. 18B, 10, semiconductor substrate) provided in a substrate (Figs. 18A/18B, 15, photoelectric conversion unit), and includes the first (Fig. 18A, 21/25, first/second transfer transistor) and second transistors (Fig. 18A, 22, reset transistor) under the substrate.
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Regarding Claim 6, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 5.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein the photoelectric conversion unit (Fig. 3, 119, PD) includes a first semiconductor region (Fig. 3, 120, n-type semiconductor region) and a second semiconductor region (Fig. 3, 116/141, p-type semiconductor region) surrounding the first semiconductor region ([0039]), and
wherein the first and second semiconductor regions in the second pixel (annotated Figure 4; 110, pixel) are disposed periodically in the first direction (annotated Figure 4) with respect to the first and second semiconductor regions in the first pixel (annotated Figure 4; Figs. 3, structure and feature are repeating in Figure 4, a plan view of nine 3x3 pixels, 110 arranged in the pixel array section, 41 (Fig. 2), as viewed from the front side (the upper side in Fig. 3), [0055]).
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Regarding Claim 7, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 5.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device) according to claim 5,
wherein each of the first (annotated Figure 4; 110, pixel) and second (annotated Figure 4; 110, pixel) pixels includes a floating diffusion portion (Fig. 4, 191, FD) in the substrate (Fig. 3, 118), and
wherein the floating diffusion portion in the second pixel is disposed periodically in the first direction with respect to the floating diffusion portion in the first pixel (annotated Figure 4).
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Regarding Claim 12, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 1.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein the first transistor (annotated Figure 5) is a transfer transistor (Figs. 4-5, 190, transfer transistor (gate)).
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Regarding Claim 13, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 12.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein the second transistor (annotated Figure 5) is a pixel transistor (Fig. 5, 192-resent transistor, 193-amplification transistor, 194-selection transistor) other than the transfer transistor or a dummy transistor that is a dummy of the pixel transistor (Note: According to https://imagesensor-info.com/en/331 (accessed on 09/27/2025), the three transistors that make up the pixel transistor, that are a reset transistor, a row selection transistor and an amplification transistor).
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Claim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOSHITA, in view of HIRAMATSU, YOKOKAWA, and LEE as applied to claim(s) 1-7, and 12-13 above, and further in view of Jung Nam et al, (hereinafter NAM), US 20060132633 A1, and Hirohisa Otsuki et al, (hereinafter OTSUKI), JP 2012199301 A.
Regarding Claim 8, YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 5.
YOSHITA further teaches in Figures 18A-18B, the solid-state imaging device (Fig. 14, 1B, [0060]) further comprising a first wiring layer (Fig. 18B, 20, wiring layer) provided under the substrate (Fig. 18B, 10) and including a plurality of first wirings (the wiring layer, 20 has a circuit for driving each pixel, P, [0032]),
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device) further comprising a first wiring layer (Fig. 8, 150, wiring layer or multi-layer wiring layer) provided under the substrate (Fig. 8, 161) and including a plurality of first wirings (Fig. 8, 151, wirings multiple times, [0043]),
wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel (annotated Figures 8-9, wiring layer, 151 is formed so as to be electrically connected to each element, [0043]).
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YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE does not explicitly show or disclose, the solid-state imaging device, further comprising a first wiring layer provided under the substrate and including a plurality of first wirings,
wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel.
NAM teaches the solid-state imaging device (Figures 5-10, semiconductor CMOS active pixel image sensor device, [0024]), further comprising a first wiring layer provided under the substrate and including a plurality of first wirings (Fig. 4, [0014-0017]),
wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel (annotated Figure 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by HIRAMATSU, YOKOKAWA, and LEE to incorporate the teachings of NAM such that the solid state imaging device further comprising a first wiring layer provided under the substrate and including a plurality of first wirings, wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel, so that the first pattern of wiring lines includes electrical interconnections between readout elements in the unit pixels, wherein the first wiring layer is an optical blocking layer to block incident light in each unit pixel to maintain substantially the same sensitivity for each light receiving element of the pixel array, 40 (NAM, [0014]).
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YOSHITA as modified by HIRAMATSU, YOKOKAWA, LEE and NAM does not explicitly show or disclose, the solid-state imaging device further comprising a first wiring layer provided under the substrate and including a plurality of first wirings,
wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel.
OTSUKI teaches in Figures 3-5, the solid-state imaging device (Fig. 5, 101) further comprising a first wiring layer (Fig. 5, 105a, first wiring layer) provided under the substrate (Fig. 5, 103) and including a plurality of first wirings (annotated Figure 5, 105a, first wiring layer includes two wirings; [0022]),
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wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel (annotated Figure 5, 105a, first wiring layer includes two wirings; here, two transfer control signal lines T1 and T2, two transfer control signal lines T3 and T4, and two lines, a first power supply line, VDD1 and a reset signal line Rx extending in a row direction, between pixels adjacent to each other in a column direction, [0022]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have as modified by YOSHITA, HIRAMATSU, YOKOKAWA, LEE and NAM to incorporate the teachings of OTSUKI such that the solid state imaging device further comprising a first wiring layer provided under the substrate and including a plurality of first wirings, wherein the first wirings in the second pixel are disposed periodically in the first direction with respect to the first wirings in the first pixel, so that the wiring layer, 105 has wirings arranged therein that electrically connect the peripheral circuits and each pixel, and has two lay3ers, a first wiring layer, 105a, and a second wiring layer, 105b (OTSUKI, [0027]).
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Regarding Claim 9, YOSHITA as modified by HIRAMATSU, YOKOKAWA, LEE, NAM and OTSUKI teaches the solid-state imaging device according to claim 8.
NAM further teaches the solid-state imaging device (Figures 5-10, semiconductor CMOS active pixel image sensor device, [0024]) according to claim 8,
wherein each of the first and second pixels includes the plurality of first wirings extending to one side in the first direction or second direction (annotated Figures 4 and 8A-8C).
OTSUKI further teaches in Figures 3-5, the solid-state imaging device (Fig. 5, 101), wherein each of the first and second pixels (annotated Figures 3 and 4) includes the plurality of first wirings extending to one side in the first direction or second direction (annotated Figures 3-5 above, first wiring layer includes two wirings; here, two transfer control signal lines T1 and T2, two transfer control signal lines T3 and T4, and two lines, a first power supply line, VDD1 and a reset signal line Rx extending in a row direction, between pixels adjacent to each other in a column direction, [0022]).
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Regarding Claim 10, YOSHITA as modified by HIRAMATSU, YOKOKAWA, LEE, NAM and OTSUKI teaches the solid-state imaging device according to claim 8.
NAM further teaches the solid-state imaging device (Figures 5-10, semiconductor CMOS active pixel image sensor device, [0024]) further comprising a second wiring layer ([0015]) provided under the first wiring layer ([0014]) and including a plurality of second wirings (the second wiring layer includes a second pattern of wiring lines include voltage supply lines, [0015]),
wherein the second wirings in the second pixel are disposed periodically in the first direction with respect to the second wirings in the first pixel (annotated Figure 4, 8A-8C above).
OTSUKI further teaches in Figures 3-5, the solid-state imaging device (Fig. 5, 101), further comprising a second wiring layer (Fig. 5, 105b, second wiring layer) provided under (inverted Figure 5 resembles, 105b provided under 105a as annotated in Figure 5) the first wiring layer ([0014]) and including a plurality of second wirings (two wirings extending in the column direction, which is the first direction, between pixels adjacent in the row direction, which is second direction, two signal line SIG and the ground line VSS, the signal line SIG and the first line, power supply lines, VDD3, [0022]),
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wherein the second wirings in the second pixel are disposed periodically in the first direction with respect to the second wirings in the first pixel (annotated Figures 3 and 4 above with respect to periodically disposed power lines, signal lines etc. with respect to pixels).
Regarding Claim 11, HIRAMATSU, YOKOKAWA, LEE, NAM and OTSUKI teaches the solid-state imaging device according to claim 10.
OTSUKI further teaches in Figures 3-5, the solid-state imaging device (Fig. 5, 101),
wherein each of the first and second pixels (annotated Figures 3 and 4) includes the plurality of first wirings extending to one side in the first direction (annotated Figure 3, wiring elements, T1, T2,T3, T4, VDD1, Rx, [0021-0022]) or second direction and the plurality of second wirings extending to the other side in the first direction or second direction (annotated Figure 3, wiring elements, SIG, VSS, VDD3, [0021-0022]).
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Claim(s) 16, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOSHITA, in view of YOKOKAWA and LEE as applied to claim(s) 1-7, and 12-13 above.
Regarding Claim 16, YOSHITA teaches in Figure 14, a solid-state imaging device (Fig. 14, 1B, [0060]), comprising:
a first pixel (annotated Figure 14, P, [0060-0061]);
a second pixel (annotated Figure 14, P, [0060-0061]) located in a first direction (annotated Figure 14 or L1 direction) of the first pixel,
wherein each of the first and second pixels includes a first transistor (Fig. 14, 21, second transfer transistor) and a second transistor (Fig. 14, 22, reset transistor).
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YOSHITA does not explicitly disclose a solid-state imaging device, comprising: an element isolation insulation film surrounding each of the first and second pixels.
YOKOKAWA teaches a solid-state imaging device (Figs. 7/11, 100a/100b, image sensor), comprising:
an element isolation insulation film (Fig. 37, 21214/21215, first/second insulating film) surrounding each of the first and second pixels (Fig. 37, 21200)/
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YOSHITA to incorporate the teachings of YOKOKAWA such that a solid state imaging device comprising: an element isolation insulation film surrounding each of the first and second pixels, so that the a trench-shaped element isolation portion, 232 extending from the incident surface of the semiconductor substrate, 103 is formed between adjacent pixels, 201a (YOKOKAWA, Figure 37).
YOSHITA as modified by YOKOKAWA does not explicitly disclose a solid state imaging device comprising: wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view.
LEE teaches a solid state imaging device (Fig. 4, 1, image sensor) comprising: wherein the element isolation insulation film (Fig. 4, 150, element isolating layer) has a forward tapered shape in a cross-sectional view (annotated Figure 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by YOKOKAWA to incorporate the teachings of LEE such that a solid state imaging device comprising: wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view, so that a first element isolating layer, 150 may surround the active pixel, AP or the reference pixel, RP and be extended from the lower surface to the upper surface of the substrate, 100 to form a deep trench, to manufacture the image sensor with improved reliability (LEE, [0005], [0070]).
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Regarding Claim 18, YOSHITA teaches in Figure 14, a solid-state imaging device (Fig. 14, 1B, [0060]), comprising:
a first pixel (annotated Figure 14, P, [0060-0061]);
a second pixel (annotated Figure 14, P, [0060-0061]) located adjacent to the first pixel in a first direction (annotated Figure 14 or L1 direction);
a third pixel located (annotated Figure 14 or L2 direction) adjacent to the first pixel in a second direction;
a fourth pixel located adjacent (annotated Figure 14 or L2 direction) to the second pixel in the second direction;
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a first element isolation insulation film (Figs. 17-18B, 16, first light shielding film) provided in each of the first to fourth pixels (annotated Figures 18A-18B; 16, first light shielding film); and
a second element isolation insulation film surrounding each of the first to fourth pixels (annotated Figures 18A-18B; 17, second light shielding film).
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YOSHITA does not explicitly disclose a solid-state imaging device, comprising: wherein at least one of the first element isolation insulation film or the second element isolation insulation film has a forward tapered shape in a cross-sectional view.
YOKOKAWA teaches a solid-state imaging device (Figs. 7/11, 100a/100b, image sensor), comprising:
wherein at least one of the first element isolation insulation film or the second element isolation insulation film (Fig. 37, 21214/21215, first/second insulating film) has a forward tapered shape in a cross-sectional view (Fig. 37, [0246]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified YOSHITA to incorporate the teachings of YOKOKAWA such that a solid state imaging device comprising: wherein at least one of the first element isolation insulation film or the second element isolation insulation film has a forward tapered shape in a cross-sectional view, so that the tapered shape grove (21211) thus decreases the opening diameter in the depth direction of the substrate, (21221) for an image sensor comprises a structural color filter that utilizes the interference of electromagnetic waves on the incident surface of light, and a reflecting portion that reflects electromagnetic waves between adjacent structural color filers (YOKOKAWA, [0246], [0010]).
Though YOKOKAWA teaches a solid state imaging device comprising, where int the element isolation insulating film has a reverse tapered shape, YOSHITA as modified by and YOKOKAWA does not explicitly disclose or suggest, a solid state imaging device comprising: wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view.
LEE teaches a solid state imaging device (Fig. 4, 1, image sensor) comprising: wherein the element isolation insulation film (Fig. 4, 150, element isolating layer) has a forward tapered shape in a cross-sectional view (annotated Figure 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by YOKOKAWA to incorporate the teachings of LEE such that a solid state imaging device comprising: wherein the element isolation insulation film has a forward tapered shape in a cross-sectional view, so that a first element isolating layer, 150 may surround the active pixel, AP or the reference pixel, RP and be extended from the lower surface to the upper surface of the substrate, 100 to form a deep trench, to manufacture the image sensor with improved reliability (LEE, [0005], [0070]).
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Claim(s) 19-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over YOSHITA, in view of YOKOKAWA and LEE as applied to claim(s) 16, and 18 above, and further in view of HIRAMATSU, as applied to claim(s) 1-7, and 12-13 above.
Regarding Claim 19 YOSHITA as modified by YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 18.
YOSHITA further teaches in Figure 14, the solid-state imaging device (Fig. 14, 1B, [0060]),
wherein the first element isolation insulation film (Fig. 18A, 16, first light shielding film) is disposed between the first transistor (annotated Figure 18A, 25, first transfer transistor) and the second transistor (annotated Figure 18A, 22~24/21, second transfer transistor/reset transistor/select transistor/amplification transistor),
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YOSHITA does not explicitly disclose the solid-state imaging device according to wherein each of the first to fourth pixels includes a first transistor and a second transistor, wherein the first transistors in the first to fourth pixels are disposed periodically in the first and second directions, and wherein the second transistors in the first to fourth pixels include gate electrodes having two or more types of areas in plan view.
HIRAMATSU teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein each of the first to fourth pixels (annotated Figure 4) includes a first transistor (annotated Figures 5; Figs. 4-5, 190, transfer transistor (gate)) and a second transistor (annotated Figures 4-5; Fig. 5, 192-reset transistor, 193-amplification transistor, 194-selection transistor),
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wherein the first transistors in the first to fourth pixels are disposed periodically in the first and second directions (annotated Figure 4), and
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wherein the second transistors in the first to fourth pixels include gate electrodes having two or more types of areas in plan view (annotated Figure 4).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by YOKOKAWA, and LEE to incorporate the teachings of HIRAMATSU such that the solid-state imaging device according to wherein each of the first to fourth pixels includes a first transistor and a second transistor, wherein the first transistors in the first to fourth pixels are disposed periodically in the first and second directions, and wherein the second transistors in the first to fourth pixels include gate electrodes having two or more types of areas in plan view, so that the aforementioned configuration promotes an increase in device formation area in each pixel and discharge the static electricity charged in a pixel to the outside of the pixel (HIRAMATSU, Figure 4, [0003], [0077]).
Regarding Claim 20, YOSHITA as modified by YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 18.
YOSHITA further teaches in Figure 14, a solid-state imaging device (Fig. 14, 1B, [0060]),
wherein the first element isolation insulation film (Fig. 18A, 16, first light shielding film) is disposed between the first transistor (annotated Figure 18A, 25, first transfer transistor) and the second transistor (annotated Figure 18A, 22~24/21, second transfer transistor/reset transistor/select transistor/amplification transistor).
YOSHITA does not explicitly disclose the solid-state imaging device according to wherein each of the first to fourth pixels includes a first transistor and a second transistor, wherein the first transistors in the first to fourth pixels are disposed periodically in the first and second directions, and wherein the second transistors in the first to fourth pixels are disposed periodically in the first and the second directions.
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HIRAMATSU teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein each of the first to fourth pixels (annotated Figure 4) includes a first transistor (annotated Figures 5; Figs. 4-5, 190, transfer transistor (gate)) and a second transistor (annotated Figures 4-5; Fig. 5, 192-reset transistor, 193-amplification transistor, 194-selection transistor),
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1055
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wherein the first transistors in the first to fourth pixels are disposed periodically in the first and second directions (annotated Figure 4), and
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wherein the second transistors in the first to fourth pixels are disposed periodically in the first and the second directions.
wherein the second transistors in the first to fourth pixels are disposed periodically in the first and second directions (annotated Figure 4).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by YOKOKAWA, and LEE to incorporate the teachings of HIRAMATSU such that the solid-state imaging device according to wherein each of the first to fourth pixels includes a first transistor and a second transistor, wherein the first transistors in the first to fourth pixels are disposed periodically in the first and second directions, and wherein the second transistors in the first to fourth pixels include gate electrodes having two or more types of areas in plan view, so that the aforementioned configuration promotes an increase in device formation area in each pixel and discharge the static electricity charged in a pixel to the outside of the pixel (HIRAMATSU, Figure 4, [0003], [0077]).
Regarding Claim 21, YOSHITA as modified by YOKOKAWA, and LEE teaches the solid-state imaging device according to claim 16.
YOSHITA further teaches in Figure 14, the solid-state imaging device (Fig. 14, 1B, [0060]), further comprising:
a third pixel located in a second direction (annotated Figure 14 or L2 direction) of the first pixel; and
a fourth pixel located in the second direction (annotated Figure 14 or L2 direction) of the second pixel,
wherein each of the first and second pixels includes a first transistor (Fig. 14, 21, second transfer transistor) and a second transistor (Fig. 14, 22, reset transistor), and
wherein the first and second transistors in the fourth pixel are disposed in the first direction with respect to the first and second transistors in the third pixel (annotated Figure 14).
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YOSHITA, as modified by YOKOKAWA, and LEE does not explicitly disclose, the solid state imaging device, further comprising: the first and second transistor in the fourth pixel are disposed periodically in the first direction with respect to the first and second transistors in the third pixel.
HIRAMATSU teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device) according to claim 1, further comprising: the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistor in the fourth pixel (annotated Figure 4; 110, pixel) are disposed periodically in the first direction (annotated Figure 4) with respect to the first and second transistors in the third pixel (annotated Figure 4; 110, pixel).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have YOSHITA as modified by YOKOKAWA, and LEE to incorporate the teachings of HIRAMATSU such that the solid state imaging device further comprising: the first and second transistor in the fourth pixel are disposed periodically in the first direction with respect to the first and second transistors in the third pixel, so that the aforementioned configuration promotes an increase in device formation area in each pixel and discharge the static electricity charged in a pixel to the outside of the pixel (HIRAMATSU, Figure 4, [0003], [0077]).
Regarding Claim 22, YOSHITA as modified by YOKOKAWA, LEE and HIRAMATSU teaches the solid-state imaging device according to claim 21.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the third pixel (annotated Figure 4; 110, pixel) are disposed symmetrically in the second direction (annotated Figure 4) with respect to the first and second transistors in the first pixel (annotated Figure 4; 110, pixel), and/or
wherein the first (Fig. 4, 190, transfer transistor) and second transistors Fig. 4, 194, selection transistor) in the fourth pixel (annotated Figure 4; 110, pixel) are disposed symmetrically in the second direction (annotated Figure 4) with respect to the first and second transistors in the second pixel (annotated Figure 4; 110, pixel).
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Regarding Claim 23, YOSHITA as modified by YOKOKAWA, LEE and HIRAMATSU teaches the solid-state imaging device according to claim 21.
HIRAMATSU further teaches in Figures 2-4, the solid state imaging device (Fig. 2, 12, imaging device),
wherein first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the third pixel are disposed periodically in the second direction (annotated Figure 4) with respect to the first and second transistors in the first pixel (annotated Figure 4; 110, pixel), and/or
wherein the first (Fig. 4, 190, transfer transistor) and second (Fig. 4, 194, selection transistor) transistors in the fourth pixel are disposed periodically in the second direction (annotated Figure 4) with respect to the first and second transistors in the second pixel (annotated Figure 4; 110, pixel).
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Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20160276381 A1 – Figure 3B
STATEMENT OF RELEVANCE – A cross-sectional view of an image sensor, 200A, wherein a device isolation trench, 230T has a forward tapered shape.
US 201200111821 A1 – Figure 2
STATEMENT OF RELEVANCE – A cross-sectional view of an image sensor, provided with a deep pixel isolation section, DTI that isolates the pixel areas UP1 and UP2 from each other, and has forward tapered shape.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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