DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/1/2026 has been entered.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the previously mailed PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Honjo et al. (WO 2020121725 A1).
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[Claim 1] Honjo et al. discloses a imaging device (Honjo et al. -Title & Abstract) comprising:
a first semiconductor layer 200 including, for each pixel, a photoelectric conversion section and a floating diffusion section (e.g. – FD 221 ) that accumulates signal charge generated in the photoelectric conversion section (203) [Honjo et la. Fig. 25];
a second semiconductor layer 300 stacked on the first semiconductor layer and having a first surface provided with a pixel transistor 310, the pixel transistor having a three-dimensional structure (Honjo et al. figs. 26-27 & 32 demonstrate the transistors of substrate 300 are Finfets) and reading the signal charge from the floating diffusion section (Fig. 25/32- This statement of intended use/operation does not provide any further structural distinction. It is further noted, per the circuit diagrams in figs 4-5 of Honjo, the transistors at the level would be expected operate as described.) ; and
a through-wiring line 221c that directly couples the floating diffusion section and a gate electrode of the pixel transistor to each other (Fig. 25 & 32- As shown in fig. 25 [and 32 Note: for fig. 32 the substrate/finfet may face the opposite direction.] and described by Honjo the transistors of the second substrate are directly connected to the floating diffusion FD region of the first substrate. The vertical conductive path constitutes through-wiring.), wherein only a portion (e.g. bottom surface of through wire 221c which interfaces with the “accumulation section.”) of the through-wiring is in contact with the floating diffusion section when the through-wiring is directly coupled to the floating diffusion section (Fig. 25 & 32- Through-wiring 221c is directly coupled to the floating diffusion section/substrate.).
Regarding the limitation that “only a portion of the through-wiring is vertically superposed over the floating diffusion section”, Honjo discloses a through-wiring line (221c) directly coupled to and vertically superposed over a floating diffusion section (221). While Honjo illustrates the wiring as generally centered, it would have been obvious to a PHOSITA to vary the lateral position or footprint of the through-wiring, such that only a portion is superposed. Shifting the contact to partially overlap the diffusion region is a routine design choice for maximizing routing density within tight design rules. Furthermore, partial superposition is an inherent result of standard lithographic alignment tolerances and overlay shifts. Maintaining functionality while allowing for partial superposition is a predictable solution to manufacturing variability.
A PHOSITA would recognize that utilizing partial superposition is a predictable solution for managing manufacturing variability and preventing electrical shorts to adjacent structures, evidenced by standard industry practices like gate hard caps and spacers, designed specifically to protect device integrity from such variations when a contact is laterally shifted. Thus, the claimed spatial relationship is merely a predictable application of known engineering principles.
The claimed overlap area represents the optimization of a result-effective variable to balance yield and performance, as suggested by Honjo and general technical knowledge. Because this represents a finite, known solution to a design challenge, pursuing it constitutes ordinary skill rather than innovation, aligning with the principles in KSR Int'l Co. v. Teleflex Inc
[Claim 2] Honjo et al. discloses a imaging device according to claim 1, wherein the pixel transistor has a fin- type structure (Honjo et al. figs. 26-27 & 32-33 demonstrate the transistors of substrate 300 are Finfets)[Claim 3] The imaging device according to claim 1, wherein the second semiconductor layer 301 further has a second surface opposed to the first semiconductor layer, on a side opposite to the first surface, and the gate electrode 313 penetrates through the first surface and the second surface of the second semiconductor layer (Honjo et al. figs. 26-27 demonstrate the transistors of substrate 300 are Finfets)
[Claim 4] Honjo et al. discloses a imaging device according to claim 3, wherein an end portion of a penetrating part, which penetrates the second semiconductor layer, of the gate electrode 313 protrudes from the second surface of the second semiconductor layer (Honjo et al. figs. 26-27 & 32 demonstrate the transistors of substrate 300 are Finfets)
[Claim 5] Honjo et al. discloses a imaging device according to claim 4, wherein the through-wiring line couples the floating diffusion section and the end portion of the gate electrode protruding from the second surface of the second semiconductor layer to each other (Honjo et al. figs. 25, 26-27 & 32 demonstrate the transistors of substrate 300 are Finfets)
[Claim 6] Honjo et al. discloses a imaging device according to claim 3, wherein the through-wiring line 221 is in contact with a side surface of the gate electrode penetrating the second semiconductor layer (Honjo et al. figs. 25, 26-27 & 32).
[Claim 7] Honjo et al. discloses a imaging device according to claim 6, wherein the through-wiring line 221 is further in contact with a portion of a top surface of the gate electrode (Honjo et al. figs. 25, 26-27, 32 & 33).
[Claim 8] Honjo et al. discloses a imaging device according to claim 3, wherein the pixel transistor includes a plurality of fins (Honjo et al. figs. 25, 26-27 & 32), and a first width of the through-wiring line penetrating between the plurality of fins is narrower than a second width of the through-wiring line extending above the gate electrode (Honjo et al. fig.& 32 – Note: The horizontal segment in the width direction may be considered thicker than the vertical segment width direction as shown in fig. 32. Furthermore, a POSITA, designing the interconnects for a stacked semiconductor device with fins, would be expected to routinely adjust the width of a wiring line to fit the available space and minimize electrical resistance. It would be an obvious engineering choice to make the wire narrower to fit between the fins, where space is limited, and then widen it over the gate electrode to increase the cross-sectional area and reduce resistance).
[Claim 9] Honjo et al. discloses a imaging device according to claim 1, wherein the pixel transistor has a gate- all-round structure (Fig. 33).
[Claim 10] Honjo et al. discloses a imaging device according to claim 9, wherein the pixel transistor includes a semiconductor layer 311 provided on a side of the first surface of the second semiconductor layer 301 and extending in a direction substantially parallel to a planar direction of the second semiconductor layer, the gate electrode 313 covering a top surface and an undersurface of a portion of the semiconductor layer and a pair of side surfaces, a first insulating film 314 provided between the semiconductor layer and the gate electrode and covering the top surface and the pair of side surfaces of the semiconductor layer, and a second insulating film 360 covering the undersurface of the semiconductor layer, and the second insulating film is provided to be wider than a third width in a direction orthogonal to an extending direction of the semiconductor layer (Honjo et al. figs. 25, & 33 – As best understood from the broad and ambiguous claim language, this is best under stood to be describing the GAA embodiment).
[Claim 11] Honjo et al. discloses a imaging device according to claim 10, wherein an extending part, of the second insulating film, extending outward beyond the third width of the semiconductor layer is formed below the second insulating film covering the undersurface of the semiconductor layer (Honjo et al. figs. 25, & 33 – As best understood from the broad and ambiguous claim language, this is best under stood to be describing the GAA embodiment).
[Claim 12] Honjo et al. discloses a imaging device according to claim 10, wherein the gate electrode has araised part that is wider than the through-wiring line, on a side of a surface opposed to the first semiconductor layer (Honjo et al. figs. 25, & 33 – As best understood from the broad and ambiguous claim language, this is best under stood to be describing the GAA embodiment. Additionally, a POSITA would find it obvious to widen the contact area between the through-wiring line and the gate electrode. This is a standard and predictable technique for reducing contact resistance, improving signal integrity, and increasing manufacturing tolerance. In the absence of unexpected results and or benefit, the relative dimensions would be considered obvious design choice [ MPEP § 2144.04.].).
[Claim 13] Honjo et al. discloses a imaging device according to claim 12, wherein the width of the raised part is wider than a wiring diameter of the through-wiring line (Honjo et al. figs. 25, & 33 – As best understood from the broad and ambiguous claim language, this is best under stood to be describing the GAA embodiment. Additionally, a POSITA would find it obvious to widen the contact area between the through-wiring line and the gate electrode. This is a standard and predictable technique for reducing contact resistance, improving signal integrity, and increasing manufacturing tolerance.).
[Claim 14] Honjo et al. discloses a imaging device according to claim 10, wherein the pixel transistor includes a semiconductor layer 311 provided on the side of the first surface of the second semiconductor layer 301 and extending in the direction substantially parallel to the planar direction of the second semiconductor layer, the gate electrode 313 covering a top surface and an undersurface of a portion of the semiconductor layer and a pair of side surfaces, a third insulating film 314 provided between the semiconductor layer and the gate electrode and covering the top surface, the undersurface, and the pair of side surfaces of the semiconductor layer, and a fourth insulating film provided spaced apart at a predetermined interval below the semiconductor layer (Honjo et al. figs. 25, & 33 – As best understood from the broad and ambiguous claim language, this is best under stood to be describing the GAA embodiment).
[Claim 15] Honjo et al. discloses a imaging device according to claim 14, wherein the fourth insulating film is provided to be wider than the third width of the semiconductor layer (portions of 314 are wider than other portions of 314 as shown in fig. 33. Further note that a POSITA would recognize that varying the width is a routine design option depending on the manufacturing process and desired electrical isolation. In the absence of unexpected results and or benefit, the relative width would be considered obvious design choice [ MPEP § 2144.04.].).
[Claim 16] Honjo et al. discloses a imaging device according to claim 14, wherein the fourth insulating film is provided to be narrower than the third width of the semiconductor layer (Honjo Fig. 33 - Further note that a POSITA would recognize that varying the width is a routine design option depending on the manufacturing process and desired electrical isolation. In the absence of unexpected results and or benefit, the relative width would be considered obvious design choice [ MPEP § 2144.04.].).
[Claim 17] Honjo et al. discloses a imaging device according to claim 15, wherein the gate electrode has a raised part that is wider than the fourth insulating film, on a side of a surface opposed to the first semiconductor layer (Honjo et al. figs. 25, 26-27, 32 & 33 - Additionally, a POSITA would find it obvious to widen the contact area between the through-wiring line and the gate electrode. This is a standard and predictable technique for reducing contact resistance, improving signal integrity, and increasing manufacturing tolerance. In the absence of unexpected results and or benefit, the relative dimensions would be considered obvious design choice [ MPEP § 2144.04.].)..
[Claim 18] Honjo et al. discloses a imaging device according to claim 17, wherein the width of the raised part is wider than a wiring diameter of the through-wiring line (Honjo et al. figs. 25, 26-27, 32 & 33 - Additionally, a POSITA would find it obvious to widen the contact area between the through-wiring line and the gate electrode. This is a standard and predictable technique for reducing contact resistance, improving signal integrity, and increasing manufacturing tolerance. In the absence of unexpected results and or benefit, the relative dimensions would be considered obvious design choice [ MPEP § 2144.04.].)..
[Claim 19] Honjo et al. discloses a imaging device according to claim 10, wherein the pixel transistor includes a source region and a drain region at both ends of the semiconductor layer 311 provided on the side of the first surface of the second semiconductor layer 301 and extending in the direction substantially parallel to the planar direction of the second semiconductor layer, and a sacrificial layer (the statement of function does not provide any clear structural distinction.) is further provided that has side surfaces substantially same as the side surfaces of the semiconductor layer, immediately below the semiconductor layer in the source region and the drain region (Honjo et al. figs. 25, 26-27, 32 & 33).
[Claim 20] Honjo et al. discloses a imaging device according to claim 19, wherein the semiconductor layer has a substantially uniform width with respect to the extending direction (Honjo et al. figs. 25, 26-27, 32 & 33).
[Claim 21] Honjo et al. discloses a imaging device according to claim 1, wherein an amplification transistor, a reset transistor, a selection transistor, and an FD conversion gain switching transistor are provided, as the pixel transistor (Honjo et al. figs. 4-5).
[Claim 22] Honjo et al. discloses a imaging device according to claim 21, wherein the amplification transistor, the reset transistor, the selection transistor, and the FD conversion gain switching transistor each have the three-dimensional structure (Honjo et al. figs. 4-5, 25, 26-27, 32 & 33).
[Claim 23] Honjo et al. discloses a imaging device according to claim 22, wherein a gate electrode of at least the amplification transistor, among the amplification transistor, the reset transistor, the selection transistor, and the FD conversion gain switching transistor, penetrates through the first surface and a second surface of the second semiconductor layer, the second surface being opposed to the first semiconductor layer, on a side opposite to the first surface (Honjo et al. figs. 4-5, 25, 26-27, 32 & 33 ).
[Claim 24] Honjo et al. discloses a imaging device according to claim 21, wherein the amplification transistor has the three-dimensional structure, and the reset transistor, the selection transistor, and the FD conversion gain switching transistor each have a planar structure (Honjo et al. figs. 4-5, 25, 26-27, 32 & 33).
[Claim 25] Honjo et al. discloses a light-receiving element comprising: a first semiconductor layer including a photoelectric conversion section and a floating diffusion section that accumulates signal charge generated in the photoelectric conversion section; a second semiconductor layer stacked on the first semiconductor layer and having a first surface provided with a transistor, the transistor having a three-dimensional structure and reading the signal charge from the floating diffusion section; and a through-wiring line that directly couples the floating diffusion section and a gate electrode of the transistor to each other (Honjo et al. figs. 4-5, 25, 26-27, 32 & 33) , wherein only a portion (e.g. bottom surface of through wire 221c which interfaces with the “accumulation section.”) of the through-wiring is in contact with the floating diffusion section when the through-wiring is directly coupled to the floating diffusion section (Fig. 25 & 32- Through-wiring 221c is directly coupled to the floating diffusion section/substrate.).
Regarding the limitation that “only a portion of the through-wiring is vertically superposed over the floating diffusion section”, Honjo discloses a through-wiring line (221c) directly coupled to and vertically superposed over a floating diffusion section (221). While Honjo illustrates the wiring as generally centered, it would have been obvious to a PHOSITA to vary the lateral position or footprint of the through-wiring, such that only a portion is superposed. Shifting the contact to partially overlap the diffusion region is a routine design choice for maximizing routing density within tight design rules. Furthermore, partial superposition is an inherent result of standard lithographic alignment tolerances and overlay shifts. Maintaining functionality while allowing for partial superposition is a predictable solution to manufacturing variability.
A PHOSITA would recognize that utilizing partial superposition is a predictable solution for managing manufacturing variability and preventing electrical shorts to adjacent structures, evidenced by standard industry practices like gate hard caps and spacers, designed specifically to protect device integrity from such variations when a contact is laterally shifted. Thus, the claimed spatial relationship is merely a predictable application of known engineering principles.
The claimed overlap area represents the optimization of a result-effective variable to balance yield and performance, as suggested by Honjo and general technical knowledge. Because this represents a finite, known solution to a design challenge, pursuing it constitutes ordinary skill rather than innovation, aligning with the principles in KSR Int'l Co. v. Teleflex Inc
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
5/8/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
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