Prosecution Insights
Last updated: May 29, 2026
Application No. 18/249,353

IMAGING ELEMENT AND IMAGING DEVICE HAVING A POLYGONAL TRANSFER GATE OPENING

Non-Final OA §103
Filed
Apr 17, 2023
Priority
Oct 28, 2020 — JP 2020-180833 +1 more
Examiner
ANDREWS, FELIX BRYAN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Semiconductor Solutions Corporation
OA Round
2 (Non-Final)
83%
Grant Probability
Favorable
2-3
OA Rounds
2m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
44 granted / 53 resolved
+15.0% vs TC avg
Moderate +13% lift
Without
With
+13.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
9 currently pending
Career history
68
Total Applications
across all art units

Statute-Specific Performance

§103
91.6%
+51.6% vs TC avg
§102
5.0%
-35.0% vs TC avg
§112
2.5%
-37.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 53 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 10/07/2025 have been fully considered but they are not persuasive. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1, 2, 4-6, & 9 are rejected under 35 U.S.C. 103 as being unpatentable over Takemoto (US 2018/0301492), Enomoto (US 2012/0217602), & Ootsuka et al. (US 2013/0082165) [Hereinafter Ootsuka]. Regarding claim 1, Takemoto teaches A solid-state imaging device, comprising: a substrate [fig. 7, first layer 101, para 86]; a plurality of photoelectric conversion units [fig. 7/10, photoelectric conversion elements 110, para 86] formed on a light incident surface side of the substrate (fig. 7, 101a; wherein “on” is inclusive of the photoelectric conversion elements on any side of the substrate), wherein the photoelectric conversion units (fig. 7/10, 110) are divided into a plurality of photoelectric conversion groups [fig. 2, pixels PIX, para 58] that each contain more than one of the photoelectric conversion units (fig. 2, photoelectric elements 110); a microlens array [fig. 2, microlens array 300 para 58] including a plurality of microlenses (fig. 2, 300)) formed on one surface side (top side) of the substrate (fig. 7/10, 101), wherein one microlens (fig. 2, microlens 300) in the plurality of microlenses (fig. 2, micro lens array of 300 in matrix form) is provided for each of the photoelectric conversion groups (fig. 2, PIX), and wherein each microlens in the plurality of microlenses extends across at least portions of each photoelectric conversion unit (fig. 2, 110) of a corresponding for a photoelectric conversion unit group (fig. 2, PIX); and a trench portion is formed in the substrate(fig. 7, 101) to surround each of the photoelectric conversion units [fig. 7, para 44, “In order to prevent electric charge generated by the light L1 incident on the first light transmission layer 120 from moving to the photoelectric conversion elements 110, element isolation may be formed between the photoelectric conversion elements 110 and the first light transmission layer 120. For example, a shallow trench isolation (STI) or a deep trench isolation (DTI) may be used as the element isolation.”] Takemoto fails to explicitly disclose and a trench portion which has a lattice shape While Takemoto notates a trench portion formed in the substrate to surround each of the photoelectric conversion units [fig. 7, para 44]. However, Enomoto teaches a trench portion which has a lattice shape [fig. 3, pixel separation portion 301, para 98, “the pixel separation portion 301 is formed in a lattice shape so as to be interposed between the plurality of pixels P, and the photodiode 21 is formed in the region of the pixel P which is divided by the pixel separation portion 101pb.”] Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise pixel separation having a lattice shape to reduce crosstalk and unwanted leakage of light or signals between adjacent pixels improving image quality and performance. Takemoto/Enomoto fails to explicitly disclose wherein each microlens in the plurality of microlenses includes two or more lens layers having different refractive indexes, and wherein a lens layer closest to the light incident surface side of the substrate out of the two or more lens layers has a lower refractive index than a lens layer farthest from the light incident surface side of the substrate. However, Ootsuka teaches wherein each microlens in the plurality of microlenses includes two or more lens layers [fig. 5A, first & second lens layers 31/33, para 99] having different refractive indexes [para 110], and wherein a lens layer (fig. 5A, 31) closest to the light incident surface side (fig. 5A, 31) of the substrate out of the two or more lens layers (fig. 5A, 31/33) has a lower refractive index than a lens layer farthest (fig. 5A, 33) from the light incident surface side of the substrate [para 110, “the second lens layer 33 is made of a material (1) having a refractive index comparable with the refractive index c of the first lens layer 31 or a material (2) having a refractive index higher than the refractive index c of the first lens layer 31.”] Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the microlens to comprise two or more lens layers wherein the refractive index closer to the substrate has a lower refractive index to direct light more effectively improving light collection efficiency as to bend light towards the normal thereby improving light collection efficiency and reducing crosstalk. Regarding claim 2, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 1, further comprising a first antireflection film [Ootsuka, fig. 5A, para 111-112] formed on an outermost surface of the microlens[Ootsuka, fig. 5A,]. Regarding claim 4, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 1, wherein out of the two or more lens layers(31), an outer peripheral portion of a lens layer (Ootsuka, fig. 5A, 31) on a side of the substrate is covered with a remaining lens layer (Ootsuka, fig. 5A, 33). Regarding claim 5, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 4, wherein the remaining lens layer (Ootsuka, fig. 5B, 33) covers a front surface excluding a top portion of the lens layer (Ootsuka, fig. 5B, 31) on the side of the substrate (Ootsuka, fig. 5B; wherein layer 33 covers a front surface on the side of the substrate that is not a top portion of the lens layer (31)). Regarding claim 6, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 4, wherein outer peripheral portions of the microlenses, which are adjacent, are in contact with each other (Ootsuka, fig. 5A; wherein all lens layers are in contact with each other and adjacent). Regarding claim 9, Takemoto teaches An electronic apparatus comprising a solid state imaging device [fig. 7, solid state imaging device 14, para 103], wherein the solid-state imaging device includes: a substrate [fig. 7, first layer 101, para 86]; a plurality of photoelectric conversion units [fig. 7/10, photoelectric conversion elements 110, para 86] formed on a light incident surface side of the substrate (fig. 7, 101a; wherein “on” is inclusive of the photoelectric conversion elements on any side of the substrate), wherein the photoelectric conversion units (fig. 7/10, 110) are divided into a plurality of photoelectric conversion groups [fig. 2, pixels PIX, para 58] that each contain more than one of the photoelectric conversion units (fig. 2, photoelectric elements 110); a microlens array [fig. 2, microlens array 300 para 58] including a plurality of microlenses (fig. 2, 300)) formed on one surface side (top side) of the substrate (fig. 7/10, 101), wherein one microlens (fig. 2, microlens 300) in the plurality of microlenses (fig. 2, micro lens array of 300 in matrix form) is provided for each of the photoelectric conversion groups (fig. 2, PIX), and wherein each microlens in the plurality of microlenses extends across at least portions of each photoelectric conversion unit (fig. 2, 110) of a corresponding for a photoelectric conversion unit group (fig. 2, PIX); and a trench portion is formed in the substrate(fig. 7, 101) to surround each of the photoelectric conversion units [fig. 7, para 44, “In order to prevent electric charge generated by the light L1 incident on the first light transmission layer 120 from moving to the photoelectric conversion elements 110, element isolation may be formed between the photoelectric conversion elements 110 and the first light transmission layer 120. For example, a shallow trench isolation (STI) or a deep trench isolation (DTI) may be used as the element isolation.”] Takemoto fails to explicitly disclose and a trench portion which has a lattice shape While Takemoto notates a trench portion formed in the substrate to surround each of the photoelectric conversion units [fig. 7, para 44]. However, Enomoto teaches a trench portion which has a lattice shape [fig. 3, pixel separation portion 301, para 98, “the pixel separation portion 301 is formed in a lattice shape so as to be interposed between the plurality of pixels P, and the photodiode 21 is formed in the region of the pixel P which is divided by the pixel separation portion 101pb.”] Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise pixel separation having a lattice shape to reduce crosstalk and unwanted leakage of light or signals between adjacent pixels improving image quality and performance. Takemoto/Enomoto fails to explicitly disclose wherein each microlens in the plurality of microlenses includes two or more lens layers having different refractive indexes, and wherein a lens layer closest to the light incident surface side of the substrate out of the two or more lens layers has a lower refractive index than a lens layer farthest from the light incident surface side of the substrate. However, Ootsuka teaches wherein each microlens in the plurality of microlenses includes two or more lens layers [fig. 5A, first & second lens layers 31/33, para 99] having different refractive indexes [para 110], and wherein a lens layer closest to the light incident surface side (fig. 5A, 31) of the substrate out of the two or more lens layers (fig. 5A, 31/33) has a lower refractive index than a lens layer farthest from the light incident surface side of the substrate [para 110, “the second lens layer 33 is made of a material (1) having a refractive index comparable with the refractive index c of the first lens layer 31 or a material (2) having a refractive index higher than the refractive index c of the first lens layer 31.”] Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the microlens to comprise two or more lens layers wherein the refractive index closer to the substrate has a lower refractive index to direct light more effectively improving light collection efficiency as to bend light towards the normal thereby improving light collection efficiency and reducing crosstalk. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Takemoto, Enomoto, & Ootsuka as applied to claims 1, 2, 4-6, & 9 above & further in view of Lee et al. (US 2016/0056195) Regarding claim 3, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 1. Takemoto/Enomoto/Ootsuka fails to explicitly disclose a second antireflection film formed between two adjacent lens layers out of the two or more lens layers. However, Lee teaches a second antireflection film [fig. 4C, antireflection film 284, para 48] formed between two adjacent lens layers [fig. 4C, pixel lens 240, para 30; which comprises lens layers 241 & 242] Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for each lens layer to comprise an anti-reflection film to enhance image quality by reducing glare and reflections for shaper and clearer imaging with better contrast. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Takemoto, Enomoto, & Ootsuka as applied to claims 1, 2, 4-6, & 9 above & further in view of Van Ostrand et al. (US 2007/0172171) [Hereinafter Van Ostrand]. Regarding claim 7, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 1. While Ootsuka teaches wherein the microlens has a conical shape [para 152] whose top portion is parallel to a light incident surface of the substrate (101) [fig. 5A]. Takemoto/Enomoto/Ootsuka fails to explicitly disclose wherein the microlens has a frustum shape However, Van Ostrand teaches various exemplary shapes for a microlens [para 39] stating, “FIG. 16 illustrates several exemplary shapes of the compound microlens 1400. The microlens 1400 can have any desired shape known to the art of non-imaging optics, such as pyramidal frustum 1601, conical frustum 1602, compound parabolic 1603, compound elliptical, polyobject or any conic section revolved to form a solid.” Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the micro lens to comprise an exemplary frustum shape for improved light focusing and concentration to enhance light efficiency and mitigate diffraction effects that can limit sensitivity in small pixels enhancing overall performance of the device. Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Takemoto, Enomoto, & Ootsuka as applied to claims 1, 2, 4-6, & 9 above & further in view of Motoki (JP2012038768A) Regarding claim 8, Takemoto/Enomoto/Ootsuka teaches The solid-state imaging device according to claim 1, further comprising a color filter layer [Ootsuka, fig. 7, filter layer 600, para 104] including a plurality of color filters [Ootsuka, fig. 7, color filter 610, para 105] formed between the microlens array (fig. 7, 300) and the substrate (fig. 7, 101) for the photoelectric conversion unit group (fig. 7, plurality of layer 110), While Ootsuka discloses in fig. 7 wherein the color filter layer (600) comprising a plurality of color filters (610) spaced apart by a distance. Takemoto/Enomoto/Ootsuka fails to explicitly disclose wherein the color filter layer includes a partition wall formed between the color filters. However, Motoki teaches an analogous device [fig. 2, para 23] wherein “A color filter 20 is formed above each PD 21 via an insulating layer (not shown), and a partition wall 24 is formed between the plurality of color filters 20 to prevent color mixing.” Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention for the device to comprise a partition wall formed between the color filters to prevent color mixing as taught by Motoki. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FELIX B ANDREWS whose telephone number is (703)756-1074. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FELIX B ANDREWS/Examiner, Art Unit 2812 /William B Partridge/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Apr 17, 2023
Application Filed
Jul 09, 2025
Non-Final Rejection mailed — §103
Oct 07, 2025
Response Filed
Nov 13, 2025
Final Rejection mailed — §103
Dec 09, 2025
Interview Requested
Dec 23, 2025
Examiner Interview (Telephonic)
Jan 09, 2026
Response after Non-Final Action
Apr 06, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642128
THREE-DIMENSIONAL (3D) NAND COMPONENT WITH CONTROL CIRCUITRY ACROSS MULTIPLE WAFERS
5y 0m to grant Granted May 26, 2026
Patent 12641776
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
2y 9m to grant Granted May 26, 2026
Patent 12635255
SUBSTRATE-LESS DIODE, BIPOLAR AND FEEDTHROUGH INTEGRATED CIRCUIT STRUCTURES
4y 11m to grant Granted May 19, 2026
Patent 12635241
Fork Sheet with Reduced Coupling Effect
4y 5m to grant Granted May 19, 2026
Patent 12635271
METHOD FOR MAKING IMAGE SENSOR DEVICES INCLUDING A SUPERLATTICE
3y 1m to grant Granted May 19, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
83%
Grant Probability
96%
With Interview (+13.4%)
3y 4m (~2m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 53 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month