DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/20/2023 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 1-3 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over TSUYUTANI, Kazutoshi (US 20200203278 A1) “TSUYUTANI et al.” in view of ASAI, Motoo (US 20120186867 A1) “ASAI et al.”
Regarding Independent Claim 1, TSUYUTANI et al. Fig. 1 discloses A electronic component embedded substrate (“IC-embedded substrate 100” ¶ [0024]) comprising:
first and second insulating layers (112 & 113) (“the insulating layers 112 and 113” ¶ [0025]);
an electronic component 300 (“a semiconductor IC 300” ¶ [0027]) embedded between an upper surface of a first insulating layer 112 and an upper surface of a second insulating layer 113;
a first conductor layer L3 (“conductor layer L3” ¶ [0030]) provided on a lower surface of the first insulating layer 112;
a second conductor layer L2 (“conductor layer L2” ¶ [0029]) provided on the upper surface of the second insulating layer 113;
a third insulating layer 114 (“the insulating layer 114” ¶ [0025]) covering the second conductor layer L2;
a third conductor layer L1 (“the conductor layer L1 formed on the surface of the insulating layer 114” ¶ [0026]) provided on a surface of the third insulating layer 114;
a first via conductor filling a first via 253 (“a plurality of via conductors 253” ¶ [0030]) penetrating the first and second insulating layers 112 & 113 and connecting the first and second conductor layers L3 & L2 (“The conductor layer L3 includes a wiring pattern 231. A part of the wiring pattern 231 is connected to the wiring pattern 222 of the conductor layer L2 through a plurality of via conductors 253 penetrating the insulating layers 112 and 113.” ¶ [0030]); and
a second via conductor filling a second via 252 (“a via conductor 252 penetrating the insulating layer 114” ¶ [0029]) penetrating the third insulating layer 114 and connecting the second and third conductor layers L2 & L1,
wherein the second via 252 is smaller in length (Fig. 1 shows 252 is smaller in length in the vertical direction) in a depth direction thereof than the first via 253,
However, TSUYUTANI et al. does not disclose, wherein the second via is positioned at such a position as to overlap the first via, and
wherein an inner wall of the second via is larger in surface roughness than an inner wall of the first via.
In the similar field of endeavor of via structure, ASAI et al. Figs. 18 and 19C discloses, wherein the second via 248 (“an opening 248 serving as a via hole” ¶ [0243]) is positioned at such a position as to overlap (Fig. 19 (C) shows 248 is overlapping 236) the first via 236 (“through holes 236” ¶ [0229]), and
wherein an inner wall of the second via 248 is larger in surface roughness (“each opening 248 for the via hole was roughened (FIG. 19 (C))” ¶ [0263]) than an inner wall of the first via 236.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the vias of TSUYUTANI et al. using the overlapping vias with a separate roughness for each via of ASAI et al. in order to a fact that a high degree of integration can be realized (ASAI et al. ¶ [0231]) and improve the adhesiveness (ASAI et al. ¶ [0174]).
Regarding Claim 2, TSUYUTANI et al. as modified by ASAI et al. discloses the limitations of claim 1. TSUYUTANI et al. Fig. 1 further discloses,
wherein each of the first and second insulating layers (112 & 113) is made of a resin material not containing a core material (“the insulating layers 112 and 113 may each be made of a resin material not including a core material such as glass cloth.” ¶ [0025]), and
wherein the third insulating layer 114 is a core layer obtained by impregnating a core material with a resin material (“insulating layer 114 positioned in the lowermost layer may each be a core layer obtained by impregnating a core material such as glass fiber with a resin material such as epoxy” ¶ [0025]).
Regarding Claim 3, TSUYUTANI et al. as modified by ASAI et al. discloses the limitations of claim 2. TSUYUTANI et al. Fig. 1 further discloses,
wherein a thickness of the third insulating layer 114 is locally increased (“the section S1 may be increased as the position in the depth direction is reduced. Thus, the volume of each via 253a can be increased.” ¶ [0035]) at a part overlapping the first via conductor 253, and
wherein a part of the third insulating layer 114 that contacts an upper surface of the first via conductor 253 is constituted by a resin material not containing a core material (Fig. 1 shows 114 and 253 contacts 113 which is resin material not containing a core; “the insulating layers 112 and 113 may each be made of a resin material not including a core material such as glass cloth.” ¶ [0025]).
Regarding Claim 7, TSUYUTANI et al. as modified by ASAI et al. discloses the limitations of claim 1. TSUYUTANI et al. Fig. 1 further discloses,
wherein each of the first and second insulating layers (112 and 113) is made of a resin material not containing a core material (“the insulating layers 112 and 113 may each be made of a resin material not including a core material such as glass cloth.” ¶ [0025]).
Regarding Claim 8, TSUYUTANI et al. as modified by ASAI et al. discloses the limitations of claim 7. TSUYUTANI et al. Fig. 1 further discloses, wherein the first and second insulating layers are made of the same resin material (“the insulating layers 112 and 113 may each be made of a resin material not including a core material such as glass cloth.” ¶ [0025]).
Claim 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over TSUYUTANI, Kazutoshi (US 20200203278 A1) “TSUYUTANI et al.” in view of ASAI, Motoo (US 20120186867 A1) “ASAI et al.” further in view of NODA, Kota (US 20100307809 A1) “NODA et al.”
Regarding Claim 4, TSUYUTANI et al. as modified by ASAI et al. discloses the limitations of claim 1. TSUYUTANI Fig. 1 further discloses, wherein a lower section of the first via 253 that is positioned on a side close to the lower surface of the first insulating layer 112 has a first section (The portion of the via 253 in 113 closer to layer 112 in Fig. 1) and a second section (The portion of the via 253 in 112 in Fig. 1) positioned closer to the lower surface of the first insulating layer 112 than the first section.
However, TSUYUTANI et al. does not disclose, wherein an upper section of the first via that is positioned on a side close to the upper surface of the second insulating layer has a shape reduced in diameter in the depth direction, and
wherein a lower section of the first via that is positioned on a side close to the lower surface of the first insulating layer has a first section increased in diameter in the depth direction and a second section positioned closer to the lower surface of the first insulating layer than the first section and reduced in diameter in the depth direction.
In the similar field of endeavor of via structure, NODA et al. Figs. 4A-4B discloses wherein an upper section of the first via (“penetrating hole (H4)” ¶ [0050]) that is positioned on a side close to the upper surface of the second insulating layer 12 (“12 is made of an insulative substrate” ¶ [0053]) has a shape reduced in diameter in the depth direction (Figs.4A-4B show diameter of H4 is reducing from the upper surface of 112), and
wherein a lower section of the first via (“penetrating hole (H4) that is positioned on a side close to the lower surface of the first insulating layer has a first section increased in diameter in the depth direction (Figs.4A-4B show diameter of H4 is increasing from the middle point of H4) and a second section positioned closer to the lower surface of the first insulating layer than the first section and reduced in diameter in the depth direction (Figs.4A-4B show diameter of H4 is reducing while contacting lower surface of 112 in the vertical direction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the vias of TSUYUTANI et al. as modified by ASAI et al. using the hour glass shape vias of NODA et al. in order to achieve low resistance and high connection reliability (NODA et al. ¶ [0083]).
Regarding Claim 5, TSUYUTANI et al. as modified by ASAI et al. and NODA et al. discloses the limitations of claim 4. TSUYUTANI Fig. 1 further discloses, wherein at least a part of the first section is provided (The portion of the via 253 in 113 closer to layer 112 in Fig. 1) in the second insulating layer 113, and at least a part of the second section is provided (The portion of the via 253 in 112 in Fig. 1) in the first insulating layer 112.
Regarding Claim 6, TSUYUTANI et al. as modified by ASAI et al. and NODA et al. discloses the limitations of claim 5. TSUYUTANI Fig. 1 further discloses, wherein a boundary between the first and second sections coincides with a boundary between the first and second insulating layers (Fig 1. Shows the boundary between the first and second sections coincides with a boundary between the first and second insulating layers (112 & 113)).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893