DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to Applicant’s amendment filed on November 20, 2025. Claims 1 and 5-6 have been amended. Claims 9-20 have been added. Claim 4 has been canceled. Currently claims 1-3 and 5-20 are pending.
Response to Arguments
Applicant’s arguments with respect to amended claim 1 has been considered and persuasive. Therefore, the rejection has been withdrawn and claims 1-3 and 5-10 indicated allowable.
Applicant’s arguments with respect to claims 11 have been considered but are moot due to the newly added limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claim 11-12 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over TSUYUTANI, Kazutoshi (US 20200203278 A1) “TSUYUTANI et al.” in view of Inagaki, Yasushi (US 20130286615 A1) “Inagaki et al.”
Regarding Independent Claim 11, TSUYUTANI et al. Fig. 1 discloses an electronic component embedded substrate comprising:
first and second insulating layers (“insulating layers 111 to 114” ¶ [0025]) stacked to each other such that an upper surface of the first insulating layer faces a lower surface of the second insulating layer (Fig. 1 shows the insulating layers 112 and 113 stacked to each other such that an upper surface of the first insulating layer faces a lower surface of the second insulating layer);
an electronic component 300 (“a semiconductor IC 300” ¶ [0027]) embedded in the first insulating layer 113;
a first conductor layer L3 (“conductor layer L3” ¶ [0030]) provided so as to be exposed on a lower surface of the first insulating layer 113;
a second conductor layer L2 (“conductor layer L2” ¶ [0029]) provided so as to be exposed on the upper surface of the first insulating layer 113;
a third conductor layer L1 (“the conductor layer L1 formed on the surface of the insulating layer 114” ¶ [0026]) provided so as to be exposed on an upper surface of the second insulating layer 114;
a first via conductor (“a plurality of via conductors 253” ¶ [0030]) having a filled-via structure and penetrating the first insulating layer so as to connect the first and second conductor layers (Fig. 1 shows first via conductor (“a plurality of via conductors 253” ¶ [0030]) having a filled-via structure and penetrating the first insulating layer so as to connect the first and second conductor layers); and
a second via conductor penetrating the second insulating layer 252 (“a via conductor 252 penetrating the insulating layer 114” ¶ [0029]) so as to connect the second and third conductor layers (Fig. 1 shows second via conductor penetrating the second insulating layer 252 (“a via conductor 252 penetrating the insulating layer 114” ¶ [0029]) so as to connect the second and third conductor layers),
wherein the second via conductor contacts with the upper surface of the first via conductor (Fig. 1 shows second via conductor 252 contacts with the upper surface of the first via conductor 253).
wherein the first via conductor 253 has a recessed upper surface such that the upper surface of the first via conductor is concavely curved so as to become flatter towards a center thereof, thereby a thickness of the second insulating layer is locally increased at a part overlapping the first via conductor (Fig. 1 shows first via conductor 253 is concavely curved from the side of insulator 114 and flatter in the center and second insulating layer 114 has increased depth at the recessed via 253).
However, TSUYUTANI et al. does not explicitly disclose, wherein the first via conductor has a recessed upper surface such that the upper surface of the first via conductor is concavely curved so as to become flatter towards a center thereof, thereby a thickness of the second insulating layer is locally increased at a part overlapping the first via conductor.
In the similar field of endeavor of via structure, “Inagaki et al.” Fig. 7 discloses wherein the first via conductor (“via holes 60” ¶ [0166]) has a recessed upper surface (Fig. 7 shows via 60 has recessed upper surface) such that the upper surface of the first via conductor is concavely curved (Fig. 7 shows via 60 has recessed upper surface of the first via conductor is concavely curved) so as to become flatter towards a center thereof (Fig. 7 shows via 60 is flatter in the center), thereby a thickness of the second insulating layer 140 (“interlayer resin insulating layers 140 and 141” ¶ [0166]) is locally increased at a part overlapping the first via conductor (Fig. 7 shows a thickness of the second insulating layer is locally increased at a part overlapping the first via conductor).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the vias of TSUYUTANI et al. using the vias of Inagaki et al. in order to attain high reliability (Inagaki et al., ¶ [0173]).
Regarding claim 12, TSUYUTANI et al. using the vias of Inagaki et al. discloses the limitations of claim 11. However, TSUYUTANI et al. does not disclose wherein a depth of a recess of the upper surface of the first via conductor does not reach the first insulating layer.
In the similar field of endeavor of via structure, “Inagaki et al.” Fig. 7 discloses wherein a depth of a recess of the upper surface of the first via conductor does not reach the first insulating layer (Fig. 7 shows a depth of a recess of the upper surface of the first via conductor does not reach the first insulating layer 40).
Regarding claim 20, TSUYUTANI et al. as modified by Inagaki et al. discloses the limitations of claim 11, wherein the first insulating layer (“the insulating layers 112, and 113” ¶ [0025]) has a structure in which a plurality of insulating layers are stacked (112 and 133 are stacked).
Claim 13-17 are rejected under 35 U.S.C. 103 as being unpatentable over TSUYUTANI, Kazutoshi (US 20200203278 A1) “TSUYUTANI et al.” in view of Inagaki, Yasushi (US 20130286615 A1) “Inagaki et al.” further in view of ASAI, Motoo (US 20120186867 A1) “ASAI et al.”.
Regarding claim 13, TSUYUTANI et al. using the vias of Inagaki et al. discloses the limitations of claim 11. TSUYUTANI et al. further discloses, wherein the first insulating layer 113 has a first via 253 filled with the first via conductor (“a plurality of via conductors 253 penetrating the insulating layers 112 and 113” ¶ [0030]), wherein the second insulating layer 114 has a second via filled 252 with the second via conductor (“electroless plating and electrolytic plating are applied to form the via conductors 254, 251 and 252 inside the openings 111a, 114a and 114b” ¶ [0051]).
However, TSUYUTANI et al. does not disclose, wherein an inner wall of the second via is larger in surface roughness than an inner wall of the first via.
In the similar field of endeavor of via structure, ASAI et al. Figs. 18 and 19C discloses, wherein the second via 248 (“an opening 248 serving as a via hole” ¶ [0243]) is positioned at such a position as to overlap (Fig. 19 (C) shows 248 is overlapping 236) the first via 236 (“through holes 236” ¶ [0229]), and
wherein an inner wall of the second via 248 is larger in surface roughness (“each opening 248 for the via hole was roughened (FIG. 19 (C))” ¶ [0263]) than an inner wall of the first via 236.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the vias of TSUYUTANI et al. using the overlapping vias with a separate roughness for each via of ASAI et al. in order to a fact that a high degree of integration can be realized (ASAI et al. ¶ [0231]) and improve the adhesiveness (ASAI et al. ¶ [0174]).
Regarding claim 14, TSUYUTANI et al. as modified by Inagaki et al. and ASAI et al. discloses the limitations of claim 13. TSUYUTANI et al. further discloses, wherein the first insulating layer is made of a resin material not containing a core material, and wherein the second insulating layer is a core layer obtained by impregnating a core material with a resin material (“the insulating layer 111 positioned in the uppermost layer and the insulating layer 114 positioned in the lowermost layer may each be a core layer obtained by impregnating a core material such as glass fiber with a resin material such as epoxy.” ¶ [0025]).
Regarding claim 15, TSUYUTANI et al. as modified by Inagaki et al. and ASAI et al. discloses the limitations of claim 14, TSUYUTANI et al. further discloses, wherein a part of the core material is exposed on the inner wall of the second via (Fig. 1 shows a part of the core material is exposed on the inner wall of the second via).
Regarding claim 16, TSUYUTANI et al. as modified by Inagaki et al. and ASAI et al. discloses the limitations of claim 15, TSUYUTANI et al. further disclose wherein the second via conductor 253 includes an upper section filling the second via and a lower section contacting with the upper surface of the first via conductor (Fig 1 shows an upper section filling the second via 252 and a lower section contacting with the upper surface of the first via conductor 253).
Regarding claim 17, TSUYUTANI et al. as modified by Inagaki et al. and ASAI et al. discloses the limitations of claim 16, TSUYUTANI et al. further disclose wherein the upper section of the second via conductor 253 contacts with the part of the core material (Fig.1 shows the upper section of the second via conductor 253 contacts with the part of the core material).
Regarding claim 18, TSUYUTANI et al. as modified by Inagaki et al. and ASAI et al. discloses the limitations of claim 17, TSUYUTANI et al. further disclose wherein the lower section of the second via conductor does not contacts with the core material (Fig.1 shows the lower section of the second via conductor 253 does not contacts with the part of the core material).
Allowable Subject Matter
Claims 1-3 and 5-10 are allowed.
Claims 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
The reason for allowance of claim 1 are the prior art of record, TSUYUTANI, Kazutoshi (US 20200203278 A1) “TSUYUTANI et al.”, ASAI, Motoo (US 20120186867 A1) “ASAI et al.”, NODA, Kota (US 20100307809 A1) “NODA et al.” and Inagaki, Yasushi (US 20130286615 A1) “Inagaki et al.” alone or in combination, does not teach or fairly suggest, wherein the first via includes first, second, third, and fourth sections arranged in this order from the upper surface of the second insulating layer and the lower surface of the first insulating layer, wherein each of the first, second, and fourth sections of the first via has a shape reduced in diameter in the depth direction, wherein the third section of the first via has a shape increased in diameter in the depth direction, and wherein a reduction in the diameter of the first section of the first via per unit depth is larger than a reduction in the diameter of the second section of the first via per unit depth, in combination with other limitations of claim 1.
Claim 2-3 and 5-10, are indicated allowable based on its dependency on claim 1.
The reason for allowance of claim 19 are the prior art of record, TSUYUTANI, Kazutoshi (US 20200203278 A1) “TSUYUTANI et al.”, ASAI, Motoo (US 20120186867 A1) “ASAI et al.”, NODA, Kota (US 20100307809 A1) “NODA et al.” and Inagaki, Yasushi (US 20130286615 A1) “Inagaki et al.” alone or in combination, does not teach or fairly suggest, wherein the first via includes first, second, third, and fourth sections arranged in this order from the upper surface of the second insulating layer and the lower surface of the first insulating layer, wherein each of the first, second, and fourth sections of the first via has a shape reduced in diameter in the depth direction, wherein the third section of the first via has a shape increased in diameter in the depth direction, and wherein a reduction in the diameter of the first section of the first via per unit depth is larger than a reduction in the diameter of the second section of the first via per unit depth, in combination with other limitations of claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday -Friday 7:15 AM to 5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, YARA J. GREEN can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Prosecution Insights