DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/13/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 65 recites the limitation "the same row group" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 66 recites the limitation "different row groups" and “one reset adaptor part” in lines 2 and 7. There is insufficient antecedent basis for these limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 48-49, 63, 65, and 67 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (WO Publication 2019227943/Machine Translation Document 02/19/2026).
Regarding independent claims 48 and 67, Xu teaches a display panel (fig. 1A)/a display apparatus (machine translation, page 20 paragraph 3), comprising a display panel (fig. 1A), wherein the display panel comprises:
a substrate (200) comprising a plurality of sub-pixels (101);
an active semiconductor layer (fig. 17, 21) on the substrate;
a gate insulating layer (22) on a side of the active semiconductor layer facing away from the substrate;
a first conductive layer (fig. 3, 23) on a side of the gate insulating layer facing away from the substrate;
an interlayer dielectric layer (24) on a side of the first conductive layer facing away from the substrate;
a second conductive layer (25) on a side of the interlayer dielectric layer facing away from the substrate;
a first interlayer insulating layer (26) on a side of the second conductive layer facing away from the substrate;
a third conductive layer (27) on a side of the first interlayer insulating layer facing away from the substrate, wherein the third conductive layer comprises a plurality of first signal lines (fig. 6A, 12) that are spaced from each other;
a second interlayer insulating layer (fig. 3, 30) on a side of the third conductive layer facing away from the substrate; and
a fourth conductive layer (fig. 3, 29 and fig. 6A, 16) on a side of the second interlayer insulating layer facing away from the substrate (fig. 3, see also machine translation, page 10 paragraph 1), wherein the fourth conductive layer comprises a plurality of second signal lines (fig. 6A, 16) that are spaced from each other;
wherein an orthographic projection of the first signal line on the substrate intersect with an orthographic projection of the second signal line on the substrate (fig. 6A).
Regarding dependent claim 49, Xu teaches the display panel according to claim 48, wherein the first signal line is a data line (machine translation, page 9 paragraph 9), and the second signal line is a power line (page 14 paragraph 4, “the initialization signal line 16 provides the pixel unit 101 with a first power supply voltage ELVDD, a second power supply voltage ELVSS, an initialization signal Vint, and the like”).
Regarding dependent claim 63, Xu teaches the display panel according to claim 48, wherein in two adjacent sub-pixels, orthographic projections of pixel circuits on the substrate are arranged in a mirror symmetry manner (fig. 1A).
Regarding dependent claim 65, Xu teaches the display panel according to claim 48, wherein the same row group of sub-pixels share one power line (fig. 6A); and
orthographic projections of pixel circuits located in the same column and at two sides of the power line on the substrate are arranged symmetrically with respect to the orthographic projection of the power line on the substrate (fig. 6A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 50-52, 59-60, 64, and 66 are rejected under 35 U.S.C. 103 as being unpatentable over Xu.
Regarding dependent claim 50, Xu teaches the display panel according to claim 49, wherein the first conductive layer comprises a plurality of scanning lines (fig. 6A, 11) that are spaced from each other, and the scanning line has a same extension direction as the power line (fig. 6A, 11 and 16 both extend horizontally).
Xu does not explicitly teach the fourth conductive layer further comprises a plurality of reset lines that are spaced from each other, and the reset line has a same extension direction as the power line; and for a power line, a scanning line and a reset line corresponding to one row of pixel circuits, an orthographic projection of the scanning line on the substrate is located between an orthographic projection of the power line on the substrate and an orthographic projection of the reset line on the substrate.
However, Xu discloses the first conductive layer to comprise a plurality of reset lines (fig. 4A, 17) which extend in the same direction as power line 16 (fig. 6A), and an orthographic projection of the reset line is between an orthographic projection of the power line and an orthographic projection of the scanning line on the substrate (fig. 6A, 17 is between 11 and 16).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the scanning line to be part of the fourth conductive layer and for its orthographic projection to be between an orthographic projection of the power line and the reset line on the substrate in order to provide a reset control signal to the pixel circuit structure (machine translation, page 12 paragraph 2), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 51, Xu teaches the display panel according to claim 48, wherein the pixel circuit comprises a driving transistor (fig. 14, T1), a data writing transistor (T2), a reset transistor (T7), and a storage capacitor (Cst);
and a second electrode of the driving transistor is electrically connected with a light emitting element (T1 connected to 20 via T5);
a first conductive plate of the storage capacitor is electrically connected with a gate of the driving transistor (fig. 11);
a gate of the data writing transistor is electrically connected with the scanning line (fig. 11), a first electrode of the data writing transistor is electrically connected with the data line (fig. 11); and
a first electrode of the reset transistor is electrically connected with the reset line (fig. 11), and a second electrode of the reset transistor is electrically connected with the second electrode of the driving transistor (fig. 11, second electrode of T7 connected to 20).
Xu does not explicitly teach a first electrode of the driving transistor is electrically connected with the power line, and a second conductive plate of the storage capacitor is electrically connected with the second electrode of the driving transistor; and a second electrode of the data writing transistor is electrically connected with the gate of the driving transistor; and a gate of the reset transistor is electrically connected with the scanning line, however Xu discloses “other pixel circuits capable of compensating the driving transistor can be used… other setting manners that can be easily conceived by a person of ordinary skill in the art without making creative work fall within the protection scope of the present disclosure” (machine translation, page 16 paragraph 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the connections between the circuit components such that a first electrode of the driving transistor is electrically connected with the power line, a second conductive plate of the storage capacitor is electrically connected with the second electrode of the driving transistor, a second electrode of the data writing transistor is electrically connected with the gate of the driving transistor; and a gate of the reset transistor is electrically connected with the scanning line in order to compensate the driving transistor (machine translation, page 16 paragraph 4), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 52, Xu further teaches the display panel according to claim 51, wherein the active semiconductor layer comprises an active zone (fig. 15, T1a) of the driving transistor, the first conductive layer comprises the first conductive plate (Csb) of the storage capacitor, and the first conductive plate of the storage capacitor is reused as the gate of the driving transistor (machine translation, page 18 paragraph 7);
in the sub-pixel, an orthographic projection of the first conductive plate of the storage capacitor on the substrate has an overlapping region with an orthographic projection of a channel zone of the active zone of the driving transistor on the substrate (fig. 15, Csb overlaps T1a); and
in the sub-pixel, the channel zone of the active zone of the driving transistor comprises a first driving channel zone (see figure below) and a second driving channel zone (see figure below) connected with each other, wherein the first driving channel zone extends in a first direction (fig. 15, D2), the second driving channel zone extends in a third direction (D1), and an included angle β between the first direction and the third direction satisfies 0⁰<β≤90⁰ (see figure below).
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Regarding dependent claim 59, Xu further teaches the display panel according to claim 51, wherein one column of the sub-pixels correspond to one data line (fig. 6A); and
in the same sub-pixel, the data line is electrically connected with a conducting source zone of the active zone of the data writing transistor (T2s) through a fourth via hole (see figure below), wherein the fourth via hole runs through the first interlayer insulating layer, the interlayer dielectric layer and the gate insulating layer (machine translation, page 13 paragraph 3, T2s is electrically connected to data line 12 and T2s is on semiconductor layer 21 and 12 is in third conductive layer 27, thus fourth via hole must run through first interlayer insulating layer 26, interlayer dielectric layer 24, and gate insulating layer 22 for T2s to be electrically connected to 12), and an orthographic projection of the fourth via hole on the substrate is located at a side of the orthographic projection of the scanning line on the substrate facing away from the orthographic projection of the first conductive plate of the storage capacitor on the substrate (see figure below, orthographic projection of fourth via hole is located above orthographic projection of scanning line 11 facing away from orthographic projection of first
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conductive plate of the storage capacitor Csb).
Regarding dependent claim 60, Xu further teaches the display panel according to claim 59, further comprising at least one of following:
one power line corresponds to at least one row of the sub-pixels (fig. 6A); and
the third conductive layer further comprises a plurality of power adaptor parts (fig. 4C, 271) that are spaced from each other, wherein in the same sub-pixel, the power line is electrically connected with the power adaptor part through a fifth via hole (fig. 3, V12, 021 corresponds to power line 16); and
wherein the fifth via hole runs through the second interlayer insulating layer (fig. 3, V12 runs through 30); or
one reset line corresponds to at least one row of the sub-pixels; and
the third conductive layer further comprises a plurality of reset adaptor parts that are spaced from each other; and
in the same sub-pixel, the reset line is electrically connected with the reset adaptor part through a seventh via hole; and
the reset adaptor part is electrically connected with a conducting source zone of the active zone of the reset transistor through an eighth via hole;
wherein the seventh via hole runs through the second interlayer insulating layer, and the eighth via hole runs through the first interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer.
Xu does not explicitly teach the power adaptor part is electrically connected with a conducting source zone of the active zone of the driving transistor through a sixth via hole, and the sixth via hole runs through the first interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer, however, Xu’s figure 3 discloses the power adaptor part 271 connected to the first signal line 11 via sixth via hole V11.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the connections between the circuit components such that the sixth via hole penetrates through the first interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer in order to connect to a conducting source zone of the active zone of the driving transistor per the reason(s) stated in claim 51 above, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 64, Xu teaches the display panel according to claim 63, wherein two adjacent rows of sub-pixels form a row group (see figure below), and different row groups comprise different sub-pixels; and
two scanning lines corresponding to the row group have a row symmetry axis in a row direction (fig. 6A);
wherein two adjacent columns of sub-pixels in the same row group form a column group (see figure below), and different column groups comprise different sub-pixels; and
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two data lines corresponding to the column group have a column symmetry axis in a column direction (fig. 6A).
Xu does not explicitly teach and orthographic projections of pixel circuits in the sub-pixels of the same row group on the substrate are arranged in a mirror symmetry manner with respect to the row symmetry axis, and orthographic projections of pixel circuits in the same column group of sub-pixels on the substrate are arranged in a mirror symmetry manner with respect to the column symmetry axis, however, Xu discloses “other setting manners that can be easily conceived by a person of ordinary skill in the art without making creative work fall within the protection scope of the present disclosure” (machine translation, page 16 paragraph 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the pixel circuit such that such that the orthographic projections of pixel circuits in the sub-pixels of the same row group on the substrate are arranged in a mirror symmetry manner with respect to the row symmetry axis, and orthographic projections of pixel circuits in the same column group of sub-pixels on the substrate are arranged in a mirror symmetry manner with respect to the column symmetry axis in order to compensate the driving transistor (machine translation, page 16 paragraph 4), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding dependent claim 66, Xu teaches the display panel according to claim 48, orthographic projections of pixel circuits located in the same column and at two sides of the reset line on the substrate are arranged symmetrically with respect to the orthographic projection of the reset line on the substrate (fig. 6A).
Xu does not explicitly teach wherein two adjacent rows of sub-pixels located in different row groups share one reset line; and wherein for two rows of sub-pixels sharing the same reset line, two adjacent columns of sub-pixels in the two rows of sub-pixels share one reset adaptor part, however, Xu discloses “other setting manners that can be easily conceived by a person of ordinary skill in the art without making creative work fall within the protection scope of the present disclosure” (machine translation, page 16 paragraph 4).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to rearrange the pixel circuit such that such that the orthographic projections of pixel circuits in the sub-pixels of the same row group on the substrate are arranged in a mirror symmetry manner with respect to the row symmetry axis, and orthographic projections of pixel circuits in the same column group of sub-pixels on the substrate are arranged in a mirror symmetry manner with respect to the column symmetry axis in order to compensate the driving transistor (machine translation, page 16 paragraph 4), since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Claims 53-55 and 61-62 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Cheng et al. (CN Publication 111128080/Machine Translation Document 02/19/2026).
Regarding dependent claim 53, Xu teaches the display panel according to claim 52.
Xu does not teach wherein the active semiconductor layer further comprises an active zone of the reset transistor, wherein the active zone of the reset transistor extends in the first direction, and the active zone of the reset transistor is located at a side of the second driving channel zone of the driving transistor facing away from the first driving channel zone; and in a same sub-pixel, a conducting drain zone of the active zone of the reset transistor is connected with the second driving channel zone of the driving transistor.
Cheng teaches wherein the active semiconductor layer (fig. 2B, 102) further comprises an active zone of the reset transistor (paragraph 0084, see also figure below), wherein the active zone of the reset transistor extends in the first direction (fig. 2B), and the active zone of the reset transistor is located at a side of the second driving channel zone of the driving transistor facing away from the first driving channel zone (see figure below); and
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in a same sub-pixel, a conducting drain zone of the active zone of the reset transistor is connected with the second driving channel zone of the driving transistor (see figure below, T7d connected to second driving channel zone via T5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the active zone of the reset transistor of Cheng in order to “avoid the second direction on adjacent signal crosstalk between pixels” (Cheng machine translation, page 12 paragraph 3).
Regarding dependent claim 54, Cheng further teaches the display panel according to claim 53, wherein the active semiconductor layer further comprises an active zone of the data writing transistor (paragraph 0084, see also figure below), and the active zone of the data writing transistor is spaced from the active zone of the reset transistor and the active zone of the driving transistor respectively (fig. 2B), wherein the active zone of the data writing transistor extends in the first direction (fig. 2B); and
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in the same sub-pixel, an orthographic projection of the active zone of the data writing transistor in a second direction is located at a side of an orthographic projection of the second driving channel zone of the driving transistor in the second direction facing away from an orthographic projection of the active zone of the reset transistor in the second direction (fig. 2B, orthographic projection of T2a located on left side of second driving channel zone in second direction D2 facing away from an orthographic projection of T7a in second direction D2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the active zone of the data writing transistor of Cheng per the reason(s) listed in claim 53 above.
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Regarding dependent claim 55, Cheng further teaches the display panel according to claim 54, wherein in the same sub-pixel, a channel zone of the active zone of the data writing transistor and a channel zone of the active zone of the reset transistor are arranged in the second direction (see figure below, both arranged in second direction D2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the arrangement of the channel zones of the data wiring transistor and the reset transistor per the reason(s) stated in claim 53 above.
Regarding dependent claim 61, Xu teaches the display panel according to claim 51.
Xu does not teach wherein the fourth conductive layer further comprises a plurality of anode connecting parts that are spaced from each other; and the third conductive layer further comprises a plurality of anode adaptor parts that are spaced from each other, wherein one sub-pixels comprises one anode connecting part and one anode adaptor part; and in the same sub-pixel, the anode connecting part is electrically connected with a first end of the anode adaptor part through a ninth via hole; and a second end of the anode adaptor part is electrically connected with the second conductive plate of the storage capacitor through a tenth via hole; wherein the ninth via hole runs through the second interlayer insulating layer, and the tenth via hole runs through the first interlayer insulating layer.
Cheng teaches wherein the fourth conductive layer further comprises a plurality of anode connecting parts (fig. 2C, 234) that are spaced from each other; and
the third conductive layer further comprises a plurality of anode adaptor parts (233) that are spaced from each other, wherein one sub-pixels comprises one anode connecting part and one anode adaptor part (fig. 2C); and
in the same sub-pixel, the anode connecting part is electrically connected with a first end of the anode adaptor part through a ninth via hole (307); and
a second end of the anode adaptor part is electrically connected with the second conductive plate of the storage capacitor through a tenth via hole (405, second end of anode adaptor part is electrically connected to T5d but can be rearranged to connect to the second conductive plate Ca per MPEP 2144.04);
wherein the ninth via hole runs through the second interlayer insulating layer (106), and the tenth via hole runs through the first interlayer insulating layer (105).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the anode parts of Cheng in order to improve flatness of the light emitting layer (Cheng machine translation, page 15 paragraph 7).
Regarding dependent claim 62, Cheng further teaches the display panel according to claim 61, wherein in a same column of the sub-pixels, anode connecting parts are arranged in the first direction and are not arranged on a same straight line; and
in a same row of the sub-pixels, anode connecting parts are arranged in the second direction and are not arranged on the same straight line; or
wherein in a same column of the sub-pixels, anode adaptor parts are arranged on a same straight line in the first direction (fig. 2A); and
in a same row of the sub-pixels, anode adaptor parts are arranged on a same straight line in the second direction (fig. 2A).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the arrangement of the anode parts of Cheng per the reason(s) stated in claim 61 above.
Claims 56-58 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Park et al. (US Publication 20200266260).
Regarding dependent claim 56, Xu teaches the display panel according to claim 50.
Xu does not teach wherein the second conductive layer comprises a data adaptor part in each sub-pixel; the first conductive plate of the storage capacitor comprises a first conductive plate body part and a first conductive plate protrusion part electrically connected with each other; and in the same sub-pixel, a first end of the data adaptor part is electrically connected with a conducting drain zone of the active zone of the data writing transistor through a first via hole, and a second end of the data adaptor part is electrically connected with the first conductive plate protrusion part through a second via hole, wherein the first via hole runs through the gate insulating layer and the interlayer dielectric layer, and the second via hole runs through the interlayer dielectric layer.
Park teaches wherein the second conductive layer comprises a data adaptor part (fig. 10, 155b) in each sub-pixel;
the first conductive plate of the storage capacitor (155) comprises a first conductive plate body part (see figure below) and a first conductive plate protrusion part (see figure below) electrically connected with each other; and
in the same sub-pixel, a first end of the data adaptor part is electrically connected with a conducting drain zone of the active zone of the data writing transistor (135b) through a first via hole (54b), and a second end of the data adaptor part is electrically connected with the first conductive plate protrusion part through a second via hole (54a), wherein the first via hole runs through the gate insulating layer (fig. 11, 121) and the interlayer dielectric layer (122), and the second via hole runs through the interlayer dielectric layer (fig. 11, paragraphs 0137 and 0140, 155b on same layer as 156a, thus via holes can be configured such that 54b runs through 121 and 122 and 54a runs
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through 122 per MPEP 2144.04).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the data adaptor part of Park in order to connect the driving gate electrode to the train region (Park paragraph 0140).
Regarding dependent claim 57, Park further teaches the display panel according to claim 56, wherein the second conductive layer further comprises the second conductive plate (fig. 10, 157a) of the storage capacitor, wherein the second conductive plate of the storage capacitor comprises a second conductive plate body part (see figure below) and a second conductive plate protrusion part (see figure below)
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electrically connected with each other; and
in the same sub-pixel, the second conductive plate protrusion part is electrically connected with the conducting drain zone of the active zone of the reset transistor (135c) through a third via hole (52b), wherein the third via hole runs through the interlayer dielectric layer and the gate insulating layer (fig. 11, 152a corresponds to second conductive plate protrusion part, see also paragraphs 0137 and 0142).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the second conductive plate parts of Park per the reason(s) stated in claim 56 above.
Regarding dependent claim 58, Park further teaches the display panel according to claim 57, wherein in the same sub-pixel, an orthographic projection of the first conductive plate body part on the substrate has an overlapping region with an orthographic projection of the second conductive plate body part on the substrate (fig. 10);
wherein the second conductive plate of the storage capacitor further comprises:
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a second conductive plate compensation part (see figure below) electrically connected with the second conductive plate body part and the second conductive plate protrusion part respectively, wherein the second conductive plate compensation part is located at a corner formed by the second conductive plate body part and the second conductive plate protrusion part (see figure below); and
in the same sub-pixel, an orthographic projection of the second conductive plate compensation part on the substrate has an overlapping region with the orthographic projection of the first conductive plate body part on the substrate (fig. 10).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the display panel of Xu and the plate compensation part of Park per the reason(s) stated in claim 56 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRACE Y CHA whose telephone number is (703)756-5393. The examiner can normally be reached Monday - Thursday 8:00 am - 5:00 pm and every other Friday 8:00 am - 4:00 pm.
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/GRACE CHA/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897