DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/28/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of species 4, Fig. 4; Claims 1-3, 5, 7-13 & 15-20 read on the elected species in the reply filed on 12/12/2025 is acknowledged.
Claims 4, 6 & 14 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/12/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 5, 8-9, 12-13, 15-18 & 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chung (US 7,907,011 B2).
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Regarding claim 1 & 17, Chung (Fig.5) discloses an amplifier or a method comprising:
a first input transistor (transistors MP1) electrically connected to a first node (OUT2’);
a first folded cascode transistor (transistor MN6)) electrically connected between the first node (OUT2’) and a second node (node N4);
a first current source (transistor MN4) electrically connected to a third node (node N6);
a first current source transistor (transistor MN5) electrically connected between the third node (node N6) and the first node (node OUT2’);
a first output transistor (transistor MN9) configured to provide inverting amplification between the second node (node N4) and a fourth node (drain terminal of MN9 which connected to OUT terminal); and
a first frequency compensation capacitor (capacitor Cc) electrically connected between the fourth node and the third node (node N6).
Regarding claim 2, Chung discloses wherein the first current source transistor (transistor MN5) is configured to conduct a signal current flowing from the fourth node to the third node (node N6) through the first frequency compensation capacitor (capacitor Cc, Fig. 5).
Regarding claim 5, Chung discloses wherein the first input transistor (MP1, P-type) is p-type and the first current source transistor (MN5) and the first folded cascode (MN6, N-type) transistor are n-type (Col. 6, lines 45-49, N-type and P-type).
Regarding claim 8, Chung discloses wherein the fourth node corresponds to an output (OUT) of the amplifier.
Regarding claim 9, Chung discloses wherein the first input transistor (transistor MP1) includes a drain connected to the first node (OUT2’), the first folded cascode transistor (transistor MN6) includes a source connected to the first node (OUT2’) and a drain connected to the second node (node N4), the first current source transistor (transistor MN5) includes a drain connected to the first node (OUT2’) and a source connected to the third node (node N6), and the first output transistor (transistor MN9) includes a gate connected to the second node (node N4) and a drain connected to the fourth node (OUT).
Regarding claim 12, Chung discloses implemented in a rail-to-rail input amplifier first power supply line, see Col. and a second power supply line, Col. 7, lines 7-10).
Regarding claim 13, Chung discloses wherein the fourth node (OUT) corresponds to a single- ended output of the rail-to-rail input amplifier.
Regarding claim 15, Chung discloses wherein the first input transistor (MP1) is a p-type input transistor, the amplifier further comprising:
a first n-type input transistor (transistor MN1) electrically connected to a fifth node (OUT2);
a second folded cascode transistor (transistor MP6) electrically connected between the fifth node (OUT2) and a sixth node (node N2);
a second current source (transistor MP4) electrically connected to a seventh node (node N5);
a second current source transistor (transistor MP6) electrically connected between the seventh node (node N5) and the fifth node (OUT2);
a second output transistor (transistor MP9) configured to provide inverting amplification between the sixth node (node N2) and an eighth node (drain terminal of transistor MP9); and
a second frequency compensation capacitor (capacitor Cc) electrically connected between the eighth node and the seventh node (node N5).
Regarding claim 16, Chung discloses further comprising a second input transistor (transistor MN1) arranged with the first input transistor (transistor MP1) as a differential pair (it is note that transistor MP1 and MN1 having analogous arrangement as transistors Mp2 and MN2 of Fig. 4 of the application).
Regarding claim 18, Chung discloses further comprising conducting a signal current from the fourth node (drain terminal of transistor MN9) to the first node (node OUT2’) through the first frequency compensation capacitor (capacitor Cc) and the first current source transistor (transistor MN5).
Regarding claim 20, Chung (Fig. 5) discloses an amplifier comprising:
a first input transistor (transistor MP1) having an input (gate terminal) configured to receive an input signal and an output (drain terminal) electrically connected to a first node (OUT2’);
a first folded cascode transistor (transistor MN6) electrically connected between the first node (OUT2’) and a second node (node N4);
a first current source (transistor MN4) electrically connected to a third node (node 6);
a first current source transistor (transistor MN5) electrically connected between the third node (node N6)and the first node (OUT2’);
a first output transistor (transistor MN9) including an input (gate terminal) connected to the second node (node N4) and an output (drain terminal) connected to a fourth node (OUT); and
a first frequency compensation capacitor (capacitor Cc) electrically connected between the fourth node (OUT) and the third node (node N6).
Allowable Subject Matter
Claims 3, 7, 10-11 & 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843