Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The objection to the specification has been withdrawn in view of the amendments filed 08/03/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4 and 7 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Gocho et. Al. (WO 2020105713 A1 hereinafter Gocho however, the examiner will use US Pre-Grant Publication/patent application US 20210400224 A1 as a translation of the WO document stated above. Hence, the rejection will use the paragraphs/columns and lines of US 20210400224 A1 for rejection purposes.).
Regarding claim 1, Gocho teaches in Figs. 24 and 32 with associated text an imaging device comprising: a first semiconductor substrate 200 provided with a photoelectric conversion element 102 (Fig. 24, [0186]); a second semiconductor substrate 300 stacked on the first semiconductor substrate with an interlayer insulating film 240 interposed therebetween (Fig. 24, [0192]) and provided with a pixel circuit 104 that reads out charges generated in the photoelectric conversion element as a pixel signal (Fig. 24, [0200]); and a via (Csub) that penetrates the interlayer insulating film and electrically connects a first surface (upper surface) of the first semiconductor substrate facing the second semiconductor substrate and at least a part of a second surface MSb of the second semiconductor substrate facing the first surface (Fig. 32, [0202]), wherein the second semiconductor substrate includes a second well region 301 and a high-concentration region 302a formed on the second surface, the high-concentration region containing impurities at a concentration higher than that of the second well region ([0201]) and being disposed at a position corresponding to the via (Fig. 32, [0202]), and wherein an element isolation region (portion of 340 in etched portion of 300 to isolate transistors [0212]) is provided around the high-concentration region to electrically isolate the via from surrounding portions of the second semiconductor substrate (Figs. 24 and 32, [0212]).
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Regarding claim 2, Gocho teaches a first well region 204 provided in the first semiconductor substrate (Fig. 25, [0189]) and a second well region (301) located on a part of the second surface in the second semiconductor substrate (Fig. 32, [0201]) contain impurities having a same conductivity type ([0189] and [0201]).
Regarding claim 3, Gocho teaches the second well region includes a first region 302 and a second region 301, and the concentration of the impurity in the first region is higher than that in the second region (Fig. 25, [0201]).
Regarding claim 4, Gocho teaches the via is provided on the first region (Fig. 32).
Regarding claim 7, Gocho teaches the second semiconductor substrate has an insulating film region 340 on the second surface side (Figs. 24 and 32, .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Gocho as applied to claim 1 and further in view of Yamaguchi et. Al. (US 20170018591 A1 hereinafter Yamaguchi).
Regarding claim 21, Gocho teaches the imaging device according to claim 1.
Gocho does not specify a first pad unit provided on the first surface of the first semiconductor substrate and electrically connected to the via.
Yamaguchi discloses in Fig. 5 with associated text a first pad unit MSF (Fig. 5, [0089]) provided on a first surface of a first semiconductor substrate (SUB and PW) similar to that of Gocho and electrically connected to a via PG similar to that of Gocho (Fig. 5, [0091])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a first pad similar to that of Gocho in the device of Gocho because according to Yamaguchi a metal silicide film NSF is formed over the upper surface of the gate electrodes GET and GET, the surface of the floating diffusion region FD, and the surface of the source/drain region NSD by a SALICIDE (Self Aligned silicide) method ([0106]) such structures are very well known in the art to provide low contact resistance between connected conducting structures.
Response to Arguments
Applicant's arguments filed 08/03/2026 have been fully considered but they are not persuasive. Regarding the arguments on page 11-12, while examiner agrees the amendments overcome the particular embodiment in Fig. 25 of Gocho relied upon in the previous rejection the embodiment in Figs. 24 and 32 of Gocho teaches the new limitations as discussed in the rejection of claim 1 above particularly wherein the second semiconductor substrate includes a second well region 301 and a high-concentration region 302a formed on the second surface, the high-concentration region containing impurities at a concentration higher than that of the second well region ([0201]) and being disposed at a position corresponding to the via (Fig. 32, [0202]), and wherein an element isolation region (portion of 340 in etched portion of 300 to isolate transistors [0212]) is provided around the high-concentration region to electrically isolate the via from surrounding portions of the second semiconductor substrate (Figs. 24 and 32, [0212]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AARON J GRAY/Examiner, Art Unit 2897
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