DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/23/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 9, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP H08250709 A to Yamaguchi et al. (hereinafter Yamaguchi).
With respect to claim 1, Yamaguchi discloses a thyristor (e.g., gate turn-off thyristor) (Yamaguchi, Fig. 1, Abstract, pp. 7-9), comprising:
a first P-type semiconductor layer (104) (Yamaguchi, Fig. 1, p. 8);
a first N-type semiconductor layer (101) (Yamaguchi, Fig. 1, p. 7) disposed in contact with the first P-type semiconductor layer (104);
a second P-type semiconductor layer (102) (Yamaguchi, Fig. 1, p. 7) disposed in contact with the first N-type semiconductor layer (101) and is separated from the first P-type semiconductor layer (104);
a second N-type semiconductor layer (103) (Yamaguchi, Fig. 1, p. 7) disposed in direct contact with the second P-type semiconductor layer (102);
a third P-type semiconductor layer (102b) (Yamaguchi, Fig. 1, p. 8) disposed in contact with the second P-type semiconductor layer (102) and has an impurity concentration (e.g., p+) higher than that (e.g., p) of the second P- type semiconductor layer (102);
a gate electrode (110) (Yamaguchi, Fig. 1, p. 8) electrically connected (e.g., through the channel CH1) to the third P-type semiconductor layer (102b);
a cathode electrode (105) (Yamaguchi, Fig. 1, p. 8) electrically connected to the second N-type semiconductor layer (103), and
a fourth P-type semiconductor layer (102a) (Yamaguchi, Fig. 1, pp. 8-9) in direct contact with each of the second P-type semiconductor layer (102) and the second N-type semiconductor layer (103), is disposed below the cathode electrode (105), and has an impurity concentration (e.g., p+) higher than that (e.g., p) of the second P-type semiconductor layer (102),
wherein the fourth P-type semiconductor layer (102a) (Yamaguchi, Fig. 1, pp. 8-9) is disposed between the second N-type semiconductor layer (103) and the second P-type semiconductor layer (102),
wherein the third P-type semiconductor layer (102b) (Yamaguchi, Fig. 1, pp. 8-9) and the fourth P-type semiconductor layer (102a) are separated from each other by the second P-type semiconductor layer (102), and
the third P-type semiconductor layer (102b) (Yamaguchi, Fig. 1, pp. 8-9) and the second N-type semiconductor layer (103) are separated from each other by the second P-type semiconductor layer (102).
Note that limitations “a thyristor with desensitized gate sensitivity” are solely recited in preamble recitations in claim 1. When reading the preamble in the context of the entire claim, the recitation “with desensitized gate sensitivity” is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
In the instant case, (i) the body of the claim described a "structurally complete invention" without the preamble, and (ii) statements in prosecution history referring to "desensitized gate sensitivity" function of invention and specification did not constitute "clear reliance" on the preamble needed to make the preamble a limitation. Further, a prior art structure of Yamaguchi which discloses all the limitations of claim 1 and is capable of performing as a thyristor with desensitized gate sensitivity as recited in the preamble meets the claim.
Regarding claim 4, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi discloses the thyristor, wherein the fourth P-type semiconductor layer (102a) (Yamaguchi, Fig. 1, pp. 8-9) is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer (103) and a side portion of the second N-type semiconductor layer (103) on a gate electrode side (e.g., on a side of the gate electrode 110).
With respect to claim 9, Yamaguchi discloses a method of manufacturing a thyristor (e.g., gate turn-off thyristor) (Yamaguchi, Fig. 1, Abstract, pp. 8-9), comprising:
forming a first P-type semiconductor layer (104) (Yamaguchi, Fig. 1, p. 8) below a first N-type semiconductor layer (101) (Yamaguchi, Fig. 1, p. 7) and forming a second P-type semiconductor layer (102) on the first N-type semiconductor layer (101);
forming a third P-type semiconductor layer (102b) (Yamaguchi, Fig. 1, pp. 7-8) and a fourth P-type semiconductor layer (102a) on a surface side of the second P-type semiconductor layer (102);
forming a second N-type semiconductor layer (103) (Yamaguchi, Fig. 1, pp. 8-9) on the surface side of the second P-type semiconductor layer (102) so as to partially overlap the fourth P-type semiconductor layer (102a); and
forming a gate electrode (110) (Yamaguchi, Fig. 1, p. 8) on the third P-type semiconductor layer (102b) and forming a cathode electrode (105) (Yamaguchi, Fig. 1, p. 8) on the second N-type semiconductor layer (103),
wherein the second N-type semiconductor layer (103) is in direct contact with the second P-type semiconductor layer (102).
Note that limitations “a thyristor with desensitized gate sensitivity” are solely recited in preamble recitations in claim 1. When reading the preamble in the context of the entire claim, the recitation “with desensitized gate sensitivity” is not limiting because the body of the claim describes a complete invention and the language recited solely in the preamble does not provide any distinct definition of any of the claimed invention’s limitations. Thus, the preamble of the claim(s) is not considered a limitation and is of no significance to claim construction. See Pitney Bowes, Inc. v. Hewlett-Packard Co., 182 F.3d 1298, 1305, 51 USPQ2d 1161, 1165 (Fed. Cir. 1999). See MPEP § 2111.02.
In the instant case, (i) the body of the claim described a "structurally complete invention" without the preamble, and (ii) statements in prosecution history referring to "desensitized gate sensitivity" function of invention and specification did not constitute "clear reliance" on the preamble needed to make the preamble a limitation. Further, a prior art structure of Yamaguchi which discloses all the limitations of claim 1 and is capable of performing as a thyristor with desensitized gate sensitivity as recited in the preamble meets the claim.
Regarding claim 10, Yamaguchi discloses the method of manufacturing the thyristor according to claim 9. Further, Yamaguchi discloses the method, wherein the third P-type semiconductor layer (e.g., 102b) (Yamaguchi, Fig. 1, pp. 8-9) has an impurity concentration (e.g., p+) higher than that (e.g., p) of the second P- type semiconductor layer (102), the fourth P-type semiconductor layer (102a) is formed below the cathode electrode (105) and has an impurity concentration (e.g., p+) higher than that (e.g., p) of the second P-type semiconductor layer (102), the third P-type semiconductor layer (102b) and the fourth P-type semiconductor layer (102a) are separated from each other by the second P-type semiconductor layer (102), and the third P-type semiconductor layer (102b) and the second N-type semiconductor layer (103) are separated from each other by the second P-type semiconductor layer (102).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over JP H08250709 to Yamaguchi in view of Sumuto (JP 55-95363 A, with machine translation, pp. 1-2).
Regarding claim 2, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi does not specifically disclose that the fourth P-type semiconductor layer is disposed on a third P-type semiconductor layer side in plan view.
However, Sumuto teaches forming the ring-shaped P+ -type layer (8) (Sumuto, Fig. 2, pp. 1-2) on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), to increase gate sensitivity and to improve performance characteristic (e.g., dv/dt).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounds sides and a bottom portion of the second N-type semiconductor layer in a plan view to have the thyristor, wherein the fourth P-type semiconductor layer is disposed on a third P-type semiconductor layer side in plan view, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 3, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi discloses the thyristor, wherein a first PN junction is formed between the fourth P- type semiconductor layer (102a) (Yamaguchi, Fig. 1, pp. 7-9) and a part of a bottom portion of the second N-type semiconductor layer (102), a second PN junction is formed between the second P- type semiconductor layer (102) and a first bottom portion of the second N-type semiconductor layer (103) other than the part of the bottom portion, and the first PN junction is located closer to a gate electrode side than the second PN junction, but does not specifically disclose that the first PN junction is located closer to a gate electrode side than the second PN junction in plan view.
However, Sumuto teaches forming the ring-shaped P+ -type layer (8) (Sumuto, Fig. 2, pp. 1-2) on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that a first PN junction is formed between the ring-shaped P+ -type layer (e.g., 8, interpreted as the fourth P-type semiconductor layer, facing the gate 7) and a part of a bottom portion of the second N-type semiconductor layer (4), and a second PN junction is formed between the second P- type semiconductor layer (3) and a first bottom portion of the second N-type semiconductor layer (4) other than the part of the bottom portion, and the first PN junction is located closer to the gate electrode side (7) than the second PN junction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi,by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounding sides and a bottom portion of the second N-type semiconductor layer in a plan view to have the thyristor, wherein the first PN junction is located closer to a gate electrode side than the second PN junction in plan view, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 8, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi does not specifically disclose that a ratio of an area of the fourth P-type semiconductor layer in contact with the second N-type semiconductor layer to an area of the second N-type semiconductor layer in plan view is 10% or more and 99% or less.
However, Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising a second P- type semiconductor layer (3), a cathode electrode (6) on the second N-type semiconductor layer (e.g., N+ type emitter layer 4) and a gate electrode (7) on the second P- type semiconductor layer (3), wherein a ring-shaped P+ -type layer (8) is formed on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that a first PN junction is formed between the ring-shaped P+ -type layer (e.g., 8, interpreted as the fourth P-type semiconductor layer, facing the gate 7) and a part of a bottom portion of the second N-type semiconductor layer (4), and a second PN junction is formed between the second P- type semiconductor layer (3) and a first bottom portion of the second N-type semiconductor layer (4) other than the part of the bottom portion, and the first PN junction is located closer to the gate electrode side (7) than the second PN junction, to control gate sensitivity and to improve voltage change rate (dv/dt).
Thus, Sumuto recognizes that forming a ring-shaped P+ -type layer on sides and a portion of the bottom of the second N-type semiconductor layer impacts performance of the thyristor. Thus, forming a ring-shaped P+ -type layer on sides and a portion of the bottom of the second N-type semiconductor layer is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, forming a ring-shaped P+ -type layer on sides and a portion of the bottom of the second N-type semiconductor layer as Sumuto has identified the doping concentration as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific ratio of an area of the fourth P-type semiconductor layer in contact with the second N-type semiconductor layer to an area of the second N-type semiconductor layer in plan view, 10% or more and 99% or less, in order to provide desired gate sensitivity and improved voltage change rate (dv/dt) as taught by Sumuto (pp. 1-2) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, and optimizing the area of the ring-shaped P+ -type layer surrounding sides and a bottom portion of the second N-type semiconductor layer in a plan view to have the thyristor, wherein a ratio of an area of the fourth P-type semiconductor layer in contact with the second N-type semiconductor layer to an area of the second N-type semiconductor layer in plan view is 10% or more and 99% or less, in order to provide improved thyristor with controlled gate sensitivity and improved voltage change rate (dv/dt) (Sumuto, pp. 1-2).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over JP H08250709 to Yamaguchi in view of Tang et al. (CN 103219372, hereinafter Tang).
Regarding claim 5, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi discloses the thyristor, wherein a first PN junction is formed between the fourth P- type semiconductor layer (102a) (Yamaguchi, Fig. 1, pp. 7-9) and a part of a bottom portion of the second N-type semiconductor layer (102), a second PN junction is formed between the second P- type semiconductor layer (102) and a first bottom portion of the second N-type semiconductor layer (103) other than the part of the bottom portion, but dos not specifically disclose that a third PN junction is formed between the second P- type semiconductor layer and a second bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, and in plan view, the first PN junction is located closer to a gate electrode side than the second PN junction, and the third PN junction is located closer to the gate electrode side than the first PN junction, (2) an impurity concentration of the part of the bottom portion of the second N-type semiconductor layer is higher than that of each of the first and second bottom portions.
Regarding (1), Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising a second P- type semiconductor layer (3), a cathode electrode (6) on the second N-type semiconductor layer (e.g., N+ type emitter layer 4) and a gate electrode (7) on the second P- type semiconductor layer (3), wherein a ring-shaped P+ -type layer (8) is formed on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that a first PN junction is formed between the ring-shaped P+ -type layer (e.g., 8, interpreted as the fourth P-type semiconductor layer, facing the gate 7) and a part of a bottom portion of the second N-type semiconductor layer (4), and a second PN junction is formed between the second P- type semiconductor layer (3) and a first bottom portion of the second N-type semiconductor layer (4) other than the part of the bottom portion, and the first PN junction is located closer to the gate electrode side (7) than the second PN junction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi o by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounds sides and a bottom portion of the second N-type semiconductor layer in a plan view and includes the first PN junction and the third PN junction located on sides of the second N-type semiconductor layer adjacent to a gate electrode side to have the thyristor, wherein a third PN junction is formed between the second P- type semiconductor layer and a second bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, and in plan view, the first PN junction is located closer to a gate electrode side than the second PN junction, and the third PN junction is located closer to the gate electrode side than the first PN junction, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, pp. 1-2).
Regarding (2), Tang teaches forming a thyristor (Tang, Figs. 10-11, 13, 15, pp. 1-2, 8-9) comprising a cathode region (e.g., the N+ type emitter region 6, interpreted as the second N-type semiconductor layer) that is configured such that the N+ impurity is increased at the bottom-center portion of the N+ type emitter region (6) (Tang, Figs. 10-11, 13, 15, pp. 8-9) to increase the current density and to increase current conduction capability of the thyristor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi by forming the second N-type semiconductor layer with increased N+ impurity at the bottom-center portion as taught by Tang to have the thyristor, wherein an impurity concentration of the part of the bottom portion of the second N-type semiconductor layer is higher than that of each of the first and second bottom portions, in order to increase current conduction capability of the thyristor, and to improve the on-current and opening speed (Tang, Abstract, pp. 1-2, 8-9).
Regarding claim 7, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi does not specifically disclose that an impurity concentration of the second N-type semiconductor layer is higher in a portion in contact with the fourth P-type semiconductor layer than in a portion not in contact with the fourth P-type semiconductor layer.
However, Tang teaches forming a thyristor (Tang, Figs. 10-11, 13, 15, pp. 1-2, 8-9) comprising a cathode region (e.g., the N+ type emitter region 6, interpreted as the second N-type semiconductor layer) that is configured such that the N+ impurity is greater (Tang, Fig. 11, p. 8) in the upper portion of the cathode region in contact with the P+type region (e.g., the P+ region 5 is formed on sides and a part of a bottom portion of the N+ type emitter region 6) and further decreases in a portion in contact with the P-type region (4) that is not in contact with the P+ type region (5), to increase current conduction capability of the thyristor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi by forming the second N-type semiconductor layer having increased N+ impurity in contact with the P+ type region as taught by Tang to have the thyristor, wherein an impurity concentration of the second N-type semiconductor layer is higher in a portion in contact with the fourth P-type semiconductor layer than in a portion not in contact with the fourth P-type semiconductor layer, in order to increase current conduction capability of the thyristor, and to improve the on-current and opening speed (Tang, Abstract, pp. 1-2, 8-9).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over JP H08250709 to Yamaguchi in view of Shekar et al. (US Patent No. 5,319,222, hereinafter Shekar).
Regarding claim 6, Yamaguchi discloses the thyristor according to claim 1. Further, Yamaguchi discloses the thyristor, wherein the fourth P-type semiconductor layer (102a) (Yamaguchi, Fig. 1, pp. 7-9) is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer (103), but does not specifically disclose that the fourth P-type semiconductor layer disposed so as not to cover a side portion of the second N-type semiconductor layer on a gate electrode side.
However, Shekar teaches forming a thyristor (Shekar, Fig. 6, Col. 2, lines 49-66; Col. 3, lines 8-26; Col. 7, lines 61-68; Col. 8, lines 1-25) with improved performance characteristics, wherein the fourth P-type semiconductor layer (e.g., P+ type region 184’) is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer (N+ type region 190’) under the cathode electrode (196’) and so as not to cover a side portion of the second N-type semiconductor layer (190’) on the gate electrode side (e.g., a side facing the gate 208’ is not covered with the P+ type region 184’).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Yamaguchi by forming the fourth P-type semiconductor layer not covering a side of the second N-type semiconductor layer facing the gate electrode as taught by Shekar to have the thyristor, wherein the fourth P-type semiconductor layer is disposed so as not to cover a side portion of the second N-type semiconductor layer on a gate electrode side, in order to provide a thyristor with improved performance characteristics (Shekar, Fig. 6, Col. 2, lines 49-66; Col. 3, lines 8-26).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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