DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action is in response to the amendments filed on 01/20/2026.
Applicant’s amendments filed 01/20/2026 have been fully considered and reviewed by the examiner. The examiner notes the amendment of claims 1-6 and 8-9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,148,810 to Simonnet et al. (hereinafter Simonnet) in view of Sumuto (JP 55-95363 A, with machine translation, pp. 1-2).
With respect to claim 1, Simonnet discloses a thyristor (e.g., 32) (Simonnet, Figs. 2A-2B, Col. 3, lines 38-67; Col. 4, lines 1-67; Col. 5, lines 1-13), comprising:
a first P-type semiconductor layer (86/84) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-3);
a first N-type semiconductor layer (60) (Simonnet, Fig. 2B, Col. 4, lines 38-41) disposed in contact with the first P-type semiconductor layer (86/84);
a second P-type semiconductor layer (82) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-3) disposed in contact with the first N-type semiconductor layer (60) and is separated from the first P-type semiconductor layer (84/86);
a second N-type semiconductor layer (80) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-4) disposed in direct contact with the second P-type semiconductor layer (82);
a third P-type semiconductor layer (88) (Simonnet, Fig. 2B, Col. 5, lines 4-6) disposed in contact with the second P-type semiconductor layer (82) and has an impurity concentration higher than that of the second P- type semiconductor layer (82);
a gate electrode (90) (Simonnet, Fig. 2B, Col. 5, lines 4-6) electrically connected to the third P-type semiconductor layer (88);
a cathode electrode (78) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-4) electrically connected to the second N-type semiconductor layer (80), and
the third P-type semiconductor layer (88) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-4) and the second N- type semiconductor layer (80) are separated from each other by the second P-type semiconductor layer (82).
Further, Simonnet does not specifically disclose that a fourth P-type semiconductor layer in direct contact with each of the second P-type semiconductor layer and the second N-type semiconductor layer, is disposed below the cathode electrode, and has an impurity concentration higher than that of the second P-type semiconductor layer, wherein fourth P-type semiconductor layer is disposed between the second N-type semiconductor layer and the second P-type semiconductor layer, wherein the third P-type semiconductor layer and the fourth P-type semiconductor layer are separated from each other by the second P-type semiconductor layer.
However, Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising a second P- type semiconductor layer (3), a cathode electrode (6) on the second N-type semiconductor layer (e.g., N+ type emitter layer 4) and a gate electrode (7) on the second P- type semiconductor layer (3), wherein a ring-shaped P+ -type layer (8) is formed on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that the P+ -type layer (8) in direct contact with each of the second P-type semiconductor layer (3) and the second N-type semiconductor layer (4), is disposed below the cathode electrode (6), and has an impurity concentration (P+) higher than that of the second P-type semiconductor layer (P-type layer 3), wherein the P+ -type layer (8) is disposed between the second N-type semiconductor layer (4) and the second P-type semiconductor layer (3), wherein the gate 7 and the P+ -type layer (8) are separated from each other by the second P-type semiconductor layer (3), to provide a thyristor with improved performance characteristic (e.g., controlled gate sensitivity and voltage change rate dv/dt).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounding sides and a bottom portion of the second N-type semiconductor layer of Simonnet and separated from the third P-type semiconductor layer of Simonnet to have the thyristor, wherein a fourth P-type semiconductor layer in direct contact with each of the second P-type semiconductor layer and the second N-type semiconductor layer, is disposed below the cathode electrode, and has an impurity concentration higher than that of the second P-type semiconductor layer, wherein fourth P-type semiconductor layer is disposed between the second N-type semiconductor layer and the second P-type semiconductor layer, wherein the third P-type semiconductor layer and the fourth P-type semiconductor layer are separated from each other by the second P-type semiconductor layer, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 2, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet does not specifically disclose that the fourth P-type semiconductor layer is disposed on a third P-type semiconductor layer side in plan view.
However, Sumuto teaches forming the ring-shaped P+ -type layer (8) (Sumuto, Fig. 2, pp. 1-2) on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), to increase gate sensitivity and to improve performance characteristic (e.g., dv/dt).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounds sides and a bottom portion of the second N-type semiconductor layer of Simonnet in a plan view to have the thyristor, wherein the fourth P-type semiconductor layer is disposed on a third P-type semiconductor layer side in plan view, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 3, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet discloses the thyristor, wherein a PN junction is formed between the second P- type semiconductor layer (82) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-6) and a bottom portion of the second N-type semiconductor layer (80), but does not specifically disclose that a first PN junction is formed between the fourth P-type semiconductor layer and a part of a bottom portion of the second N-type semiconductor layer, a second PN junction is formed between the second P- type semiconductor layer and a first bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, and the first PN junction is located closer to a gate electrode side than the second PN junction in plan view.
However, Sumuto teaches forming the ring-shaped P+ -type layer (8) (Sumuto, Fig. 2, pp. 1-2) on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that a first PN junction is formed between the ring-shaped P+ -type layer (e.g., 8, interpreted as the fourth P-type semiconductor layer, facing the gate 7) and a part of a bottom portion of the second N-type semiconductor layer (4), and a second PN junction is formed between the second P- type semiconductor layer (3) and a first bottom portion of the second N-type semiconductor layer (4) other than the part of the bottom portion, and the first PN junction is located closer to the gate electrode side (7) than the second PN junction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounding sides and a bottom portion of the second N-type semiconductor layer of Simonnet in a plan view to have the thyristor, wherein a first PN junction is formed between the fourth P-type semiconductor layer and a part of a bottom portion of the second N-type semiconductor layer, a second PN junction is formed between the second P- type semiconductor layer and a first bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, and the first PN junction is located closer to a gate electrode side than the second PN junction in plan view, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 4, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet does not specifically disclose the thyristor, wherein the fourth P-type semiconductor layer is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer and a side portion of the second N-type semiconductor layer on a gate electrode side.
However, Sumuto teaches forming the ring-shaped P+ -type layer (8) (Sumuto, Fig. 2, pp. 1-2) on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that the P+ -type layer (8) is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer (4) and a side portion of the second N-type semiconductor layer (4) on a gate electrode side (e.g., on a side of gate 7).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto to have the thyristor, wherein the fourth P-type semiconductor layer is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer and a side portion of the second N-type semiconductor layer on a gate electrode side, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 8, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet does not specifically disclose that a ratio of an area of the fourth P-type semiconductor layer in contact with the second N-type semiconductor layer to an area of the second N-type semiconductor layer in plan view is 10% or more and 99% or less.
However, Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising a second P- type semiconductor layer (3), a cathode electrode (6) on the second N-type semiconductor layer (e.g., N+ type emitter layer 4) and a gate electrode (7) on the second P- type semiconductor layer (3), wherein a ring-shaped P+ -type layer (8) is formed on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that a first PN junction is formed between the ring-shaped P+ -type layer (e.g., 8, interpreted as the fourth P-type semiconductor layer, facing the gate 7) and a part of a bottom portion of the second N-type semiconductor layer (4), and a second PN junction is formed between the second P- type semiconductor layer (3) and a first bottom portion of the second N-type semiconductor layer (4) other than the part of the bottom portion, and the first PN junction is located closer to the gate electrode side (7) than the second PN junction, to control gate sensitivity and to improve voltage change rate (dv/dt).
Thus, Sumuto recognizes that forming a ring-shaped P+ -type layer on sides and a portion of the bottom of the second N-type semiconductor layer impacts performance of the thyristor. Thus, forming a ring-shaped P+ -type layer on sides and a portion of the bottom of the second N-type semiconductor layer is a result-effective variable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to vary, through routine optimization, forming a ring-shaped P+ -type layer on sides and a portion of the bottom of the second N-type semiconductor layer as Sumuto has identified the doping concentration as a result-effective variable. Further, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at specific ratio of an area of the fourth P-type semiconductor layer in contact with the second N-type semiconductor layer to an area of the second N-type semiconductor layer in plan view, 10% or more and 99% or less, in order to provide desired gate sensitivity and improved voltage change rate (dv/dt) as taught by Sumuto (pp. 1-2) (MPEP 2144.05).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, and optimizing the area of the ring-shaped P+ -type layer surrounding sides and a bottom portion of the second N-type semiconductor layer of Simonnet in a plan view to have the thyristor, wherein a ratio of an area of the fourth P-type semiconductor layer in contact with the second N-type semiconductor layer to an area of the second N-type semiconductor layer in plan view is 10% or more and 99% or less, in order to provide improved thyristor with controlled gate sensitivity and improved voltage change rate (dv/dt) (Sumuto, pp. 1-2).
With respect to claim 9, Simonnet discloses a thyristor manufacturing method (e.g., forming a thyristor 32) (Simonnet, Figs. 2A-2B, Col. 3, lines 38-67; Col. 4, lines 1-67; Col. 5, lines 1-13), comprising:
forming a first P-type semiconductor layer (86/84) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-3) below a first N-type semiconductor layer (60) (Simonnet, Fig. 2B, Col. 4, lines 38-41) and forming a second P-type semiconductor layer (82) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-3) on the first N-type semiconductor layer (60);
forming a third P-type semiconductor layer (88) (Simonnet, Fig. 2B, Col. 5, lines 4-6) on a surface side of the second P-type semiconductor layer (82);
forming a second N-type semiconductor layer (80) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-4) on the surface side of the second P-type semiconductor layer (82);
forming a gate electrode (90) (Simonnet, Fig. 2B, Col. 5, lines 4-6) on the third P-type semiconductor layer (88) and forming a cathode electrode (78) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-4) on the second N-type semiconductor layer (80),
wherein the second N-type semiconductor layer (80) is in direct contact with the second P-type semiconductor layer (82).
Further, Simonnet does not specifically disclose forming a fourth P-type semiconductor layer on a surface side of the second P-type semiconductor layer, and forming the second N-type semiconductor layer so as to partially overlap the fourth P-type semiconductor layer.
However, Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising forming a second P- type semiconductor layer (3), and forming a ring-shaped P+ -type layer (8) on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that the P+ -type layer (8) is formed on a surface side of the second P-type semiconductor layer (3), and forming the second N-type semiconductor layer (4) so as to partially overlap the P+ -type layer (8), to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor manufacturing method of Simonnet by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto to have the thyristor manufacturing method, comprising: forming a fourth P-type semiconductor layer on a surface side of the second P-type semiconductor layer, and forming the second N-type semiconductor layer so as to partially overlap the fourth P-type semiconductor layer, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Regarding claim 10, Simonnet in view of Sumuto discloses the thyristor manufacturing method according to claim 9. Further, Simonnet discloses the thyristor manufacturing method, wherein the third P-type semiconductor layer (e.g., 88) (Simonnet, Fig. 2B, Col. 5, lines 4-6) has an impurity concentration higher than that of the second P- type semiconductor layer (82), and the third P-type semiconductor layer (88) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-4) and the second N- type semiconductor layer (80) are separated from each other by the second P-type semiconductor layer (82), but does not specifically disclose that the fourth P-type semiconductor layer is formed below the cathode electrode and has an impurity concentration higher than that of the second P-type semiconductor layer, the third P-type semiconductor layer and the fourth P- type semiconductor layer are separated from each other by the second P-type semiconductor layer.
However, Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising a second P- type semiconductor layer (3), a cathode electrode (6) on the second N-type semiconductor layer (e.g., N+ type emitter layer 4) and a gate electrode (7) on the second P- type semiconductor layer (3), wherein a ring-shaped P+ -type layer (8) is formed on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that the P+ -type layer (8) in direct contact with each of the second P-type semiconductor layer (3) and the second N-type semiconductor layer (4), is disposed below the cathode electrode (6), and has an impurity concentration (P+) higher than that of the second P-type semiconductor layer (P-type layer 3), wherein the gate 7 and the P+ -type layer (8) are separated from each other by the second P-type semiconductor layer (3), to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor manufacturing method of Simonnet/Sumuto by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounding sides and a bottom portion of the second N-type semiconductor layer of Simonnet and separated from the third P-type semiconductor layer of Simonnet to have the thyristor manufacturing method, wherein the fourth P-type semiconductor layer is formed below the cathode electrode and has an impurity concentration higher than that of the second P-type semiconductor layer, the third P-type semiconductor layer and the fourth P- type semiconductor layer are separated from each other by the second P-type semiconductor layer, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, Abstract, pp. 1-2).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,148,810 to Simonnet in view of Sumuto (JP 55-95363 A) as applied to claim 1, and further in view of Tang et al. (CN 103219372, hereinafter Tang).
Regarding claim 5, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet discloses the thyristor, wherein a PN junction is formed between the second P- type semiconductor layer (82) (Simonnet, Fig. 2B, Col. 4, lines 63-67; Col. 5, lines 1-6) and a bottom portion of the second N-type semiconductor layer (80), but does not specifically disclose that (1) a first PN junction is formed between the fourth P- type semiconductor layer and a part of a bottom portion of the second N-type semiconductor layer, a second PN junction is formed between the second P- type semiconductor layer and a first bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, a third PN junction is formed between the second P- type semiconductor layer and a second bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, and in plan view, the first PN junction is located closer to a gate electrode side than the second PN junction, and the third PN junction is located closer to the gate electrode side than the first PN junction, (2) an impurity concentration of the part of the bottom portion of the second N-type semiconductor layer is higher than that of each of the first and second bottom portions.
Regarding (1), Sumuto teaches forming a thyristor (Sumuto, Fig. 2, pp. 1-2) comprising a second P- type semiconductor layer (3), a cathode electrode (6) on the second N-type semiconductor layer (e.g., N+ type emitter layer 4) and a gate electrode (7) on the second P- type semiconductor layer (3), wherein a ring-shaped P+ -type layer (8) is formed on sides and a portion of the bottom of the second N-type semiconductor layer (e.g., N+ type emitter layer 4), such that a first PN junction is formed between the ring-shaped P+ -type layer (e.g., 8, interpreted as the fourth P-type semiconductor layer, facing the gate 7) and a part of a bottom portion of the second N-type semiconductor layer (4), and a second PN junction is formed between the second P- type semiconductor layer (3) and a first bottom portion of the second N-type semiconductor layer (4) other than the part of the bottom portion, and the first PN junction is located closer to the gate electrode side (7) than the second PN junction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming a ring-shaped P+ -type layer as the fourth P-type semiconductor layer on sides and a bottom portion of the second N-type semiconductor layer as taught by Sumuto, wherein the ring-shaped P+ -type layer surrounds sides and a bottom portion of the second N-type semiconductor layer of Simonnet in a plan view and includes the first PN junction and the third PN junction located on sides of the second N-type semiconductor layer adjacent to a gate electrode side to have the thyristor, wherein a first PN junction is formed between the fourth P- type semiconductor layer and a part of a bottom portion of the second N-type semiconductor layer, a second PN junction is formed between the second P- type semiconductor layer and a first bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, a third PN junction is formed between the second P- type semiconductor layer and a second bottom portion of the second N-type semiconductor layer other than the part of the bottom portion, and in plan view, the first PN junction is located closer to a gate electrode side than the second PN junction, and the third PN junction is located closer to the gate electrode side than the first PN junction, in order to provide a thyristor with improved performance (e.g., controlled gate sensitivity and voltage change rate dv/dt) (Sumuto, pp. 1-2).
Regarding (2), Tang teaches forming a thyristor (Tang, Figs. 10-11, 13, 15, pp. 1-2, 8-9) comprising a cathode region (e.g., the N+ type emitter region 6, interpreted as the second N-type semiconductor layer) that is configured such that the N+ impurity is increased at the bottom-center portion of the N+ type emitter region (6) (Tang, Figs. 10-11, 13, 15, pp. 8-9) to increase the current density and to increase current conduction capability of the thyristor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming the second N-type semiconductor layer with increased N+ impurity at the bottom-center portion as taught by Tang to have the thyristor, wherein an impurity concentration of the part of the bottom portion of the second N-type semiconductor layer is higher than that of each of the first and second bottom portions, in order to increase current conduction capability of the thyristor, and to improve the on-current and opening speed (Tang, Abstract, pp. 1-2, 8-9).
Regarding claim 7, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet does not specifically disclose that an impurity concentration of the second N-type semiconductor layer is higher in a portion in contact with the fourth P-type semiconductor layer than in a portion not in contact with the fourth P-type semiconductor layer.
However, Tang teaches forming a thyristor (Tang, Figs. 10-11, 13, 15, pp. 1-2, 8-9) comprising a cathode region (e.g., the N+ type emitter region 6, interpreted as the second N-type semiconductor layer) that is configured such that the N+ impurity is greater (Tang, Fig. 11, p. 8) in the upper portion of the cathode region in contact with the P+type region (e.g., the P+ region 5 is formed on sides and a part of a bottom portion of the N+ type emitter region 6) and further decreases in a portion in contact with the P-type region (4) that is not in contact with the P+ type region (5), to increase current conduction capability of the thyristor.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming the second N-type semiconductor layer having increased N+ impurity in contact with the P+ type region as taught by Tang to have the thyristor, wherein an impurity concentration of the second N-type semiconductor layer is higher in a portion in contact with the fourth P-type semiconductor layer than in a portion not in contact with the fourth P-type semiconductor layer, in order to increase current conduction capability of the thyristor, and to improve the on-current and opening speed (Tang, Abstract, pp. 1-2, 8-9).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 10,148,810 to Simonnet in view of Sumuto (JP 55-95363 A) as applied to claim 1, and further in view of Shekar et al. (US Patent No. 5,319,222, hereinafter Shekar).
Regarding claim 6, Simonnet in view of Sumuto discloses the thyristor according to claim 1. Further, Simonnet does not specifically disclose that the fourth P-type semiconductor layer is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer and so as not to cover a side portion of the second N-type semiconductor layer on a gate electrode side.
However, Shekar teaches forming a thyristor (Shekar, Fig. 6, Col. 2, lines 49-66; Col. 3, lines 8-26; Col. 7, lines 61-68; Col. 8, lines 1-25) with improved performance characteristics, wherein the fourth P-type semiconductor layer (e.g., P+ type region 184’) is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer (N+ type region 190’) under the cathode electrode (196’) and so as not to cover a side portion of the second N-type semiconductor layer (190’) on the gate electrode side (e.g., a side facing the gate 208’ is not covered with the P+ type region 184’).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the thyristor of Simonnet/Sumuto by forming the fourth P-type semiconductor layer not covering a side of the second N-type semiconductor layer facing the gate electrode as taught by Shekar to have the thyristor, wherein the fourth P-type semiconductor layer is disposed so as to cover a part of a bottom portion of the second N-type semiconductor layer and so as not to cover a side portion of the second N-type semiconductor layer on a gate electrode side, in order to provide a thyristor with improved performance characteristics (Shekar, Fig. 6, Col. 2, lines 49-66; Col. 3, lines 8-26).
Response to Arguments
Applicant’s arguments with respect to claims 1-10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891