Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 19, 2025, is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over SUGIYAMA et al.(US 2019/0053380) in view of Park(US 2017/0347450) and further in view of Shizizu et al.(US 10,366,949).
Regarding claim 1, SUGIYAMA et al. discloses a metal supporting board(fig 1A, 110);a first metal thin film; an insulating layer(fig 1A, 122); a second metal thin film; and a conductive layer(fig 1A, 132) in order toward one side in a thickness direction ,the metal supporting board comprising a metal supporting layer(fig 1A, 111), and a surface metal layer(fig 1A, 112) disposed on one surface in the thickness direction of the metal supporting layer(fig 1A) and having a higher conductivity than the metal supporting layer(par 0063), the insulating layer having a through hole that penetrates the insulating layer in the thickness direction(fig 1A, 122), the conductive layer having a via portion that is disposed in the through hole and is electrically connected to the metal supporting board(FIG 1a, 133). SUGIYAMA et al. does not disclose a first metal thin film; and a second metal thin film. However Park discloses using a seed layer/metal thin film (fig 1, 140, 130) for conductors/circuits(fig 1, 160) on printed circuit boards so as to increase the bonding force between the substrate and the metal layer(para 0007). Additionally, Shizizu et al. discloses using a seed layer/metal thin film for each circuit on the circuit board(fig 2, 52T, 53R, 72T, 73R, 82T, 83R, 93, 92). It would have been obvious to one skilled at the time of the invention to use a seed layer/metal thin film for each circuit on the circuit board as shown by both Shizizu et al. and Park to use a seed layer/metal thin film for each circuit on the circuit board of SUGIYAMA et al. since this is commonly done for increasing the bonding force between the circuits and the insulating layers. And the first thin film would be the seed layer for the circuit fig 1A, 131 and the second thin film layer would be the seed layer for circuit fig 1A, 132.
Regarding claim 2, SUGIYAMA et al. discloses wherein the metal supporting layer comprises at least one kind selected from the group consisting of stainless steel, copper alloy, aluminum, nickel, and titanium(para 0054).
Regarding claim 3, SUGIYAMA et al. discloses wherein the surface metal layer comprises at least one kind selected from the group consisting of gold, silver, and copper(para 0054, copper).
Regarding claim 4, SUGIYAMA et al. discloses wherein the via portion(fig 1A, 133) is electrically connected to the metal supporting board(fig 1A, 111) through the first metal thin film and the second metal thin film(fig 1A, shows the Via is connected to the metal supporting board through both circuits fig 1A, 131, 132) with both have a seed layer/metal thin film attached to the base of each circuit.).
Allowable Subject Matter
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADITYA SHARMA whose telephone number is (571)270-7246. The examiner can normally be reached Monday - Friday 8:30 - 5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADITYA SHARMA/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847