Prosecution Insights
Last updated: April 19, 2026
Application No. 18/252,347

SEMICONDUCTOR STRUCTURE

Final Rejection §103
Filed
May 09, 2023
Examiner
SMITH, BRADLEY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Enkris Semiconductor Inc.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
2y 6m
To Grant
76%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allow Rate
695 granted / 873 resolved
+11.6% vs TC avg
Minimal -3% lift
Without
With
+-3.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
37 currently pending
Career history
910
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
42.6%
+2.6% vs TC avg
§102
25.5%
-14.5% vs TC avg
§112
24.8%
-15.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 873 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant's arguments filed 1/22/26 have been fully considered but they are not persuasive. The applicant alleges “on both the left and right sides of the space consisted by the gap and the recess claimed in the amended claim 1 are stacked island structures, while above and below are respectively the N-type semiconductor layer and the substrate”. The examiner submits that the upper and lower portions of the patterned substrate would be considered “stacked island structures” (see markup of fig. 11A below). MPEP 2131 discloses “[t]he elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). “ Therefore the applicant’s argument is not persuasive. PNG media_image1.png 352 563 media_image1.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-8, and 10-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2009/0114935) in view of Jain et al. (US 2017/0104129). Regarding claim 1, Huang et al. disclose a stacked structure (202, 902a), comprising stacked structure units (300a, 300b)(figs 3A, and 3B) disposed along a horizontal direction (fig. 2 , fig 9D), wherein each of the stacked structure units (300a, 300b) comprises stacked island structures (202, 902a), [0051] separated from each other along the horizontal direction; and an N-type semiconductor layer (906), a light-emitting layer (908) and a P-type semiconductor layer (60) sequentially laminated on the stacked structure (202, 902a) ( fig 2 and fig. 9E). Huang et al. fails to disclose a gap is present between the adjacent stacked island structures, and a recess concaved away from the stacked structure is further formed at a side of the N-type semiconductor layer in contact with the stacked structure, wherein the recess is formed corresponding to the gap. Jain et al. disclose a gap (44) is present between the adjacent stacked island structures (the upper and lower portions of the patterned substrate would be considered “stacked island structures”)(fig 11A) and a recess (44) concaved away from the stacked structure. The combination of Jain and Huang would form the a recess (44) concaved away from the stacked structure (fig 11A Jain et al.) at a side of the N-type semiconductor layer (906, Huang) in contact with the stacked structure (fig 9E, Huang), wherein the recess is formed corresponding to the gap(fig 11A Jain et al.). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (growing a layer over the patterned substrate), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (The n-type layer would be gown over the openings. Moreover, the overgrowth of the layer over gaps will have residual stress release since the overgrown layer easily deforms [0005, Jain et al.]) Regarding claim 2, Huang et al. disclose the stacked structure is a photonic crystal structure [0049, 0055]. Regarding claim 3, Huang et al. disclose the adjacent stacked structure units (202) that are adjacent to each other are separated from each other (fig. 9E). Regarding claim 4, Huang et al. disclose one of the stacked island structures (202, 902a) comprises a buffer layer (902, SiN) and a first semiconductor layer (902, GaN) sequentially laminated [0038, 0049]. Regarding claim 5, Huang et al. disclose one of the stacked island structures (202, 902a) comprises second semiconductor layers (GaN) and third semiconductor layers (AlN) laminated alternately; a material of the second semiconductor layers (GaN, [0038,0049]) is Alx1Iny1Ga1-x1-y1N, and a material of the third semiconductor layers (AlN, [0038, 0049]) is Alx2Iny2Ga1-x2-y2N, wherein X1, Y1, X2 and Y2 are valued from 0 to 1. Regarding claim 6, Huang et al. disclose the stacked structure units (300a)(fig. 3A) [0049] are smallest repeating units to form the stacked structure (202); and each of the stacked structure units (300a)(fig. 3A) comprises at least three stacked island structures separated from each other along the horizontal direction (fig. 3A). Regarding claim 7, Huang et al. disclose a shape of a section of one of the stacked island structures (300a) is a circle (fig. 3A, when viewed from above). Regarding claim 8, Huang et al. disclose the section of the one of the stacked island structures (200, 900a) is a circle (300a, 300b)(fig. 3A and fig 3B, when viewed from above), the section of the one of the stacked island structures (200, 900a, 300b) has a diameter of less than or equal to 50 mm [0039] (The examiner notes figure 3B shows the period 302, which is measured from the midpoint of two different 300b elements. Period 302 is described in [0039] as being 1-20 mm. Therefore, the diameter of the of the 300b would be at maximum 1-20 mm and less than 50 mm.) Regarding claim 10, Huang et al. disclose the and an N-type semiconductor layer (906), a light-emitting layer (908) and a P-type semiconductor layer (60) and the method (epitaxial process) does not patentably distinguish the structure from the prior art. MPEP 2113 discloses “The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)”. Regarding claim 11, Huang et al. disclose a substrate (200, 900) and a nucleation layer (bottom layer of stack 902a, AlN [0049], same material as nucleation layer disclosed in specification paragraph 0058); along a vertical direction, the nucleation layer is disposed between the substrate (900) and the stacked structure (902a layers above the first layer) and provided with grooves (spaces between 902a) to form a plurality of nucleation-layer-middle-islands separated from each other along the horizontal direction, wherein each stacked island structure (902a) corresponds to one nucleation-layer-middle-island. Regarding claim 12, Huang et al. disclose a sapphire substrate [0048]. Claim(s) 13-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2009/0114935) in view of Jain et al. (US 2017/0104129) as applied to claim 1 above in view of Sugiyama et al. (US 2012/0292649). Huang et al. and Jain et al. disclose the invention supra. Huang et al. and Jain et al. fail to disclose a reflection layer, wherein along the vertical direction, the reflection layer is disposed at a side of the P-type semiconductor layer away from the light-emitting layer; and a transfer layer, wherein along the vertical direction, the transfer layer is disposed at a side of the reflection layer away from the P-type semiconductor layer. Sugiyama et al. disclose a reflection layer (80), wherein along the vertical direction, the reflection layer (80) is disposed at a side of the P-type semiconductor layer (20) away from the light-emitting layer (30); and a transfer layer (40), wherein along the vertical direction, the transfer layer (40) is disposed at a side of the reflection layer (80) away from the P-type semiconductor layer (20) (fig. 1). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (forming a conductive reflection layer on the p-type layer), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (the conductive layer would electrically connect the p-type layer to other layers). Regarding claim 14 the combination of Huang and Sugiyama et al. disclose the structure above, the limitation “the reflection layer (70) and the transfer layer (80) are manufactured by a chip process” does not distinguish the structure. MPEP 2113 discloses “The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)”. Regarding claims 15 and 16, Sugiyama et al. disclose the reflection layer is silver (a metal layer) [0053]. Claim(s) 13, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang et al. (US 2009/0114935) in view of Jain et al. (US 2017/0104129)as applied to claim 1 above and further in view of Jeon et al. (US 2016/0126422). Huang et al. and Jain et al. disclose the invention supra. Huang et al. and Jain et al. fail to disclose a reflection layer, wherein along the vertical direction, the reflection layer is disposed at a side of the P-type semiconductor layer away from the light-emitting layer; and a transfer layer, wherein along the vertical direction, the transfer layer is disposed at a side of the reflection layer away from the P-type semiconductor layer. Jeon et al. disclose a reflection layer (91), wherein along the vertical direction, the reflection layer (91) is disposed at a side of the P-type semiconductor layer (50) away from the light-emitting layer (40); and a transfer layer (92), wherein along the vertical direction, the transfer layer (92) is disposed at a side of the reflection layer (91) away from the P-type semiconductor layer (50) (fig. 6). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (forming reflection layer on the p-type layer), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable (the reflection layer would direct light in a certain direction and make sure that light was not lost). Regarding claims 17 and 18, Jeon et al. disclosethe reflection layer (91) comprises a DBR layer laminated [0044] and the DBR layer is formed by alternately laminating first material layers made of titanium oxide and second material layers made of silicon oxide[0044]. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRADLEY SMITH/Primary Examiner, Art Unit 2817
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Prosecution Timeline

May 09, 2023
Application Filed
Oct 17, 2025
Non-Final Rejection — §103
Jan 22, 2026
Response Filed
Mar 13, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
80%
Grant Probability
76%
With Interview (-3.1%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 873 resolved cases by this examiner. Grant probability derived from career allow rate.

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