Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 02/26/2026 is acknowledged. The traversal is on the ground(s) that examination of all of the identified inventions and all of the pending claims would not result in a serious search and/or examination burden the Restriction Requirement does not explain why each identified invention lacks unity with each other group (i.e., why there is no single general inventive concept) specifically. This is not found persuasive because features specific to each species as discussed in restriction requirement would require different keyword searches. As discussed in the restriction there is no special technical feature because Takeguchi et. Al. (US 20240178079 A1) teaches the technical features of claim 1. Furthermore as discussed in the rejections below Ishii et. Al. (US 20200195916 A1) teaches the special technical features of the claims. Examiner further notes that although only claim 4 was identified as not reading on the elected Species claim 8 specifically requires a third semiconductor substrate provided with a third pad which is only read on by species II Fig. 4 having third chip 14 and third pad 51.
The requirement is still deemed proper and is therefore made FINAL.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SOLID-STATE IMAGING ELEMENT WITH DEDICATED TEST PAD, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-7 and 9-10 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Ishii et. Al. (US 20200195916 A1 hereinafter Ishii).
Regarding claim 1 and 9-10, Ishii teaches in Fig. 12 with associated text an electronic apparatus comprising a solid-state imaging element and method for manufacturing the same, comprising: a first semiconductor substrate 102 provided with a first pad 221 used for connection with an outside [0087], separately from a dedicated pad 130-1 used for inspection in a manufacturing process; and a second semiconductor substrate 101 provided with a second pad 130-1 used for inspection in a manufacturing process (Fig. 12, [0130]), wherein the first pad and the second pad are electrically connected to each other via a first electrode 321 provided in the first semiconductor substrate and a second electrode 322 provided in the second semiconductor substrate (Fig. 12, [0139]).
Regarding claim 3, Ishii teaches the first semiconductor substrate is provided with an opening (portion of opening 225 in top of 102 exposing 221) for connecting the first pad to the outside (Fig. 12, [0087]), the second semiconductor substrate is provided with a backfill portion obtained by backfilling 301 a portion opened (opening in 300) at a time of inspection using the second pad (Fig. 13B-13C, [0137]), and the opening and the backfill portion are disposed at positions where the opening and the backfill portion do not overlap each other in plan view (see annotated Fig. below).
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Regarding claim 5, Ishii teaches the second semiconductor substrate is provided with a semiconductor circuit configured to control input and output of a signal, and the semiconductor circuit is disposed at a position not overlapping the opening in plan view (see annotated Fig. above).
Regarding claim 6, Ishii teaches the semiconductor circuit is disposed at a position overlapping the backfill portion in plan view (see annotated Fig. above).
Regarding claim 7, Ishii teaches the first electrode and the second electrode are electrically and mechanically connected to each other by using bonding of a same material ([0126] and [0139]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ishii as applied to claim 1.
Regarding claim 2, Ishii teaches the solid-state imaging element according to claim 1, wherein the first semiconductor substrate and the second semiconductor substrate are layered in units of chips (Fig. 12)
Ishii does not specify in the present embodiment the layering is after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate and the second semiconductor substrate however Ishii teahes in Fig. 2A and 4A with associated text a similar layering is carried out after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate 102 (Fig. 2A, [0078]) and the second semiconductor substrate (Fig. 4A, [0099]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the layering of the embodiment of Figs. 12-14B after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate and the second semiconductor substrate as taught in the embodiments of Figs. 2A and 4A because according to Ishii In the case of bonding for forming a stacked structure in each chip, the inspection is conducted so as to exclude defective chips, thereby preventing a failure after the formation of the stacked structure. This can reduce the cost of forming the solid-state imaging device 100. In the case of bonding for each semiconductor substrate, wafers having quite a large number of defective chips are excluded, thereby preventing a failure after the formation of the stacked structure [0079].
Furthermore even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)
Because Ishii teaches a structure that is the same as are obvious from the claimed particularly “the first semiconductor substrate and the second semiconductor substrate are layered in units of chips”, the process limitations after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate and the second semiconductor substrate in claim 2, do not carry weight in a claim drawn to structure other than in how they affect the structure. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm.
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/AARON J GRAY/Examiner, Art Unit 2897
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