Prosecution Insights
Last updated: October 02, 2026
Application No. 18/252,583

SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC APPARATUS

Final Rejection §102§103
Filed
May 11, 2023
Priority
Nov 20, 2020 — JP 2020-193097 +1 more
Examiner
GRAY, AARON J
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Group Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
429 granted / 521 resolved
+14.3% vs TC avg
Strong +30% interview lift
Without
With
+29.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
32 currently pending
Career history
553
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
54.1%
+14.1% vs TC avg
§102
28.0%
-12.0% vs TC avg
§112
15.3%
-24.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 521 resolved cases

Office Action

§102 §103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 3, 5-7,9-10 and 12-15 is/are rejected under 35 U.S.C. 102(a)(1)/102(a)(2) as being anticipated by Ishii et. Al. (US 20200195916 A1 hereinafter Ishii). Regarding claim 1 and 9-10, Ishii teaches in Fig. 12 with associated text an electronic apparatus comprising a solid-state imaging element and method for manufacturing the same, comprising: a first semiconductor substrate 102 provided with a first pad 221 used for connection with an outside [0087], and a dedicated pad 130-2 used for inspection in a manufacturing process [Fig. 12, [0074]) wherein each of the first pad and the dedicated pad is provided within the first semiconductor substrate and the dedicated pad is provided separate from the first pad (the first pad and the dedicated pad are provided in separate location and separated from each other by the substrate Fig. 12); and a second semiconductor substrate 101 provided with a second pad 130-1 used for inspection in a manufacturing process (Fig. 12, [0130]), wherein the first pad and the second pad are electrically connected to each other via a first electrode 321 provided in the first semiconductor substrate and a second electrode 322 provided in the second semiconductor substrate (Fig. 12, [0139]). Regarding claims 3 and 12, Ishii teaches the first semiconductor substrate is provided with an opening (portion of opening 225 in top of 102 exposing 221) for connecting the first pad to the outside (Fig. 12, [0087]), the second semiconductor substrate is provided with a backfill portion obtained by backfilling 301 a portion opened (opening in 300) at a time of inspection using the second pad (Fig. 13B-13C, [0137]), and the opening and the backfill portion are disposed at positions where the opening and the backfill portion do not overlap each other in plan view (see annotated Fig. below). PNG media_image1.png 509 278 media_image1.png Greyscale Regarding claims 5 and 13, Ishii teaches the second semiconductor substrate is provided with a semiconductor circuit configured to control input and output of a signal, and the semiconductor circuit is disposed at a position not overlapping the opening in plan view (see annotated Fig. above). Regarding claims 6 and 14, Ishii teaches the semiconductor circuit is disposed at a position overlapping the backfill portion in plan view (see annotated Fig. above). Regarding claims 7 and 15, Ishii teaches the first electrode and the second electrode are electrically and mechanically connected to each other by using bonding of a same material ([0126] and [0139]). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 2 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii as applied to claim 1 and 10 respectively. Regarding claims 2 and 11, Ishii teaches the solid-state imaging element according to claims 1 and 10, wherein the first semiconductor substrate and the second semiconductor substrate are layered in units of chips (Fig. 12) Ishii does not specify in the present embodiment the layering is after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate and the second semiconductor substrate however Ishii teaches in Fig. 2A and 4A with associated text a similar layering is carried out after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate 102 (Fig. 2A, [0078]) and the second semiconductor substrate (Fig. 4A, [0099]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to carry out the layering of the embodiment of Figs. 12-14B after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate and the second semiconductor substrate as taught in the embodiments of Figs. 2A and 4A because according to Ishii In the case of bonding for forming a stacked structure in each chip, the inspection is conducted so as to exclude defective chips, thereby preventing a failure after the formation of the stacked structure. This can reduce the cost of forming the solid-state imaging device 100. In the case of bonding for each semiconductor substrate, wafers having quite a large number of defective chips are excluded, thereby preventing a failure after the formation of the stacked structure [0079]. Furthermore even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985) Because Ishii teaches a structure that is the same as are obvious from the claimed particularly “the first semiconductor substrate and the second semiconductor substrate are layered in units of chips”, the process limitations after inspection for guaranteeing known good die (KGD) is performed on each of the first semiconductor substrate and the second semiconductor substrate in claim 2, do not carry weight in a claim drawn to structure other than in how they affect the structure. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985), MPEP 2113. Claims 16 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii as applied to claim 1 and 10 respectively and further in view of Chen et. Al. (US 20200402903 A1 hereinafter Chen). Regarding claims 16 and 19, Ishii teaches the solid-state imaging element according to claims 1 and 10. Ishii does not specify the first pad overlaps with the second pad in a cross-sectional view. Chen teaches in Fig. 1 with associated text a device similar to that of Ishii wherein a first pad (pad between 26 sand 25 [0026]) overlaps with a second pad 20-1 [0026] in a cross-sectional view (Fig. 1, [0026]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a structure similar to that of Chen for the first pad of Ishii because according to Chen the second conductive pads 19-1 may electrically connect to the first conductive pads 18-1 and a top metal layer 20-1 of the capacitor die 12, and then to the conductive vias 25 and the interface bumps 26 through the electrical connection built by layers of conductive vias 21, 23 and metal layer(s) 22-1, 24 [0026] so that such a structure would be suitable for external connection in the device o Ishii. Claims 17-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ishii as applied to claim 1 and 10 respectively and further in view of Yang et. Al. (US 20190131277 A1 hereinafter Yang). Regarding claims 17 and 20, Ishii teaches the solid-state imaging element according to claims 1 and 10. Ishii does not specify the first pad is made of aluminum. Yang teaches in Fig. 1D with associated text a device similar to that of Ishii wherein a first pad (layer of 108 at the top) is made of aluminum (Fig. 1D, [0018]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use aluminum as taught by Yang first metal features 108 may be made of tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or a combination thereof so that it would have been obvious to one of ordinary skill in the art, in view of the teachings of Ishii and Yang, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to use aluminum of the first pad with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007), furthermore using aluminum for such a conductive feature was extremely well known in the art. Regarding claim 18, Ishii teaches the solid-state imaging element according to claims 1 and 10. Ishii does not specify the second pad is made of aluminum. Yang teaches in Fig. 1D with associated text a device similar to that of Ishii wherein a second pad (layer of 108 at the top) is made of aluminum (Fig. 1D, [0018]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use aluminum as taught by Yang first metal features 108 may be made of tungsten (W), copper (Cu), copper alloys, aluminum (Al), aluminum alloys, or a combination thereof so that it would have been obvious to one of ordinary skill in the art, in view of the teachings of Ishii and Yang, since all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods to use aluminum of the second pad with no change in their respective functions, and the combination would have yielded nothing more than predictable results to one of ordinary skill in the art before the effective filing date of the claimed invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S., 82 USPQ2d 1385 (2007), furthermore using aluminum for such a conductive feature was extremely well known in the art. Response to Arguments Applicant's arguments filed 06/04/2026 have been fully considered but they are not persuasive. Regarding the arguments on page 10 130-2 is now being relied upon for the dedicated pad 130-2 is in the substrate 102 and the first pad and the dedicated pad are provided in separate locations and separated from each other by the substrate Fig. 12 so that they are provided separately as discussed in the rejection above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON J GRAY whose telephone number is (571)270-7629. The examiner can normally be reached Monday-Friday 9am-4pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Toledo Fernando can be reached on 5712721867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AARON J GRAY/Examiner, Art Unit 2897
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Prosecution Timeline

May 11, 2023
Application Filed
Mar 16, 2026
Non-Final Rejection mailed — §102, §103
Jun 04, 2026
Response Filed
Aug 11, 2026
Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+29.8%)
2y 6m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 521 resolved cases by this examiner. Grant probability derived from career allowance rate.

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