Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RCE, received 3/16/2026, has been entered.
Claims 1-7 and 15-16 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 5-7, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US Pub. No. 2020/0227390 A1), hereafter referred to as Chiu, in view of Ishibashi et al. (US Pub. No. 2019/0159332 A1), hereafter referred to as Ishibashi.
As to claim 1, Chiu discloses an integrated electronic component (see annotated fig 3C, below, [0022]) comprising:
a rewiring layer (layer 30; See annotated fig 3C below), the rewiring layer comprising:
a layer (fig 3C, layer 30 but doesn’t explicitly teach that it is an insulator);
a first electrode pad (bottom pad portion of 33) disposed on a lower surface of the layer (bottom of 30);
a second electrode pad (upper pad portion of 33) disposed on an upper surface of the insulator layer (upper of 30); and
an interlayer connection conductor (33) formed in the layer (30) so as to connect the first electrode pad and the second electrode pad to each other (upper and lower pad portions of 33);
a first chip (22) under the rewiring layer (30), the first chip facing upwardly toward the lower surface of the insulation layer on which the first electrode pad is disposed;
a molded resin (24; [0037]) directly sealing at least a portion of all sides of the first chip (22); and
a second chip (21) above the rewiring layer (30), the second chip facing downwardly toward the upper surface of the insulation layer on which the second electrode pad is disposed;
wherein the first electrode pad and the second electrode pad are disposed so as to face each other with the interlayer connection conductor extending linearly from the first electrode pad to the second electrode pad (linear connection between upper and lower portions of 33);
wherein the first electrode pad is connected to a fourth electrode pad (pad on 22 connected to pad portion of 33), the fourth electrode pad being disposed on a surface of the first chip (22); and
wherein the second electrode pad is connected to a fifth electrode pad (220 connected to upper pad portion of 33), the fifth electrode pad being disposed on a lower surface of the second chip (21).
Chiu does not explicitly disclose that the rewiring layer includes an insulator layer.
Nonetheless, Ishibashi discloses wherein a rewiring layer includes an insulator layer (fig 1, 5a; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the core layer of rewiring layer 30 from an insulator layer as taught by Ishibashi since this will provide electrical separation from the conductive elements thus preventing short circuit operations.
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As to claim 5, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses a sealing member sealing (26) the first chip (22); and
a connection conductor (250) passing through the sealing member (26),
wherein the rewiring layer (30) further includes:
a wiring (portion of 33) formed on any one of the lower surface (bottom), the upper surface (upper), and an inner layer (inner) of the layer (30), the wiring connected to one of the first electrode pad (lower portion of 33) and the second electrode pad (pad portion of 33); and
a third electrode pad (adjacent pad 33) disposed on the lower surface (lower) of the layer (30), the third electrode pad (pad 33) being connected to the connection conductor (wiring portion of 33), and
wherein at least a part of the wiring (part of 33) is connected to the third electrode pad (adjacent pad 33).
As to claim 6, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses wherein the first electrode pad and the second electrode pad are connected via the interlayer connection conductor at the shortest distance (fig 3C, direct vertical connection between top and bottom surface of 30 is connected with 33 between upper chip and lower chip).
As to claim 7, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses wherein the first electrode pad and the second electrode pad are connected together via the interlayer connection conductor at the shortest distance therebetween (fig 3C, direct vertical connection between top and bottom surface of 30 is connected with 33 between upper chip and lower chip).
As to claim 15, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses wherein the first chip (22) has a top surface on which the fourth electrode is disposed and an opposing bottom surface that is opposite the top surface (see top and bottom surfaces of 22), wherein an entirety of the bottom surface of the first chip is directly sealed closed by the molded resin (24).
As to claim 16, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu in view of Ishibashi further disclose wherein a wiring disposed within the layer extends to and connects with the interlayer connection conductor at a location between and spaced apart from the first electrode pad and the second electrode pad (Chiu’s fig 3C, layer 30 including the fan-out wiring without showing the actual fanning out wiring, nonetheless, Ishibashi shows a fanning out wiring in figure 5, wiring 17a). It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the fanning out wiring detailed in Ishibashi in the fan-out circuit layer of Chiu since this will improve electrical interconnectivity of the device.
Allowable Subject Matter
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest all of the limitations of claim 2 including the limitations external connection conductors are positioned under the third electrode pad, the external connection conductors passing through the molded resin from an upper surface to a lower surface thereof; claims 3-4 are allowable because of their dependence from claim 2.
Response to Arguments
Applicant's arguments filed 3/16/2026 have been fully considered but they are not persuasive.
Applicant argued that elements 300A and 300B of Chiu are not “electrode pads,” as required by claim 1.
Examiner disagrees because Chiu does not include any elements 300A or 300B. Applicant might mean 30A and 30B of Chiu are not “electrode pads,” however, 30A and 30B of Chiu are defined as the first side and second side of circuit element 30. Examiner agrees that none of 30A nor 30B can be considered to be an electrode pad because they are only defined as a top and bottom surface.
Applicant argued that Chiu discloses that circuit layers 300, i.e., elements 300A and 300B in Figure 3C are fan-out redistribution layers. “Applicant respectfully submits that those skilled in the art understand that circuit layers/fan-out redistribution layers have different structures and perform different functions than simple electrode pads.”
Examiner disagrees because Chiu only discloses a single circuit layer 300, as opposite to the plurality of “circuit layers 300” presented by the Applicant. Furthermore, the Applicant has provided no reasoning for why it is believed that a simple electrode pad structure is different from the conductor electrode pad structure shown in fig 3C. Instead, the Examiner has presented that the structure of a simple electrode pad (i.e. a structure of a conductive element in a pad shape that is used to connect electrical conductors) is shown in the figure and described as a circuit layer/fan-out redistribution layers.
Applicant argued that it would not have been obvious to replace the fan-out layers of Chiu.
Examiner disagrees because there is no need to replace the fan-out layers of Chiu.
Applicant argued that “if the components in Chiu were replaced with simple electrode pads – which are neither semiconductor elements nor passive elements – the structural integrity and the functional purpose of Chiu’s high-density integration would be undermined.
Examiner disagrees because the fan-out layers of Chiu are clearly not semiconductor elements nor passive elements, so it is unclear how the Applicant draws the conclusion that the structural integrity and functional purpose would be undermined.
Applicant argued that component 21 is not sealed by encapsulation layer 26 but sealed by coupling layer 28.
This argument is moot in view of new ground of rejection.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2021/0349260 A1 and US 2016/0021753 A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 5/21/2026
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