Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment, received 10/21/2025, has been entered.
Claims 1-14 are presented for examination.
Specification
The amendment filed 10/21/2025 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows: The addition of “method for production” was not supported by the original disclosure because the Applicant’s original disclosure did not include a method for production.
Applicant is required to cancel the new matter in the reply to this Office Action.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claims 8-14 recite “a method for producing an integrated electronic component comprising steps”, this limitation was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention, because the specification did not provide teaching of the method of producing or the steps as now recited in claims 8-14.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claims are indefinite because each claim either recites or is dependent from a claim that recites “a first chip under the rewiring layer while facing upwardly a surface of the rewiring layer on which the first electrode pad is formed” or “a first chip on the rewiring layer while facing upwardly a surface of the rewiring layer on which the first electrode pad is formed.” These limitations render the claims indefinite because one of skill in the art would not understand what is meant by these words when read in view of the Applicant’s disclosure.
Claim 5 recites the limitation "the electrode pad" in the third to last line. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu et al. (US Pub. No. 2020/0227390 A1), hereafter referred to as Chiu, in view of Ishibashi et al. (US Pub. No. 2019/0159332 A1), hereafter referred to as Ishibashi.
As to claim 1, Chiu discloses an integrated electronic component (fig 3C, [0022]) comprising:
a rewiring layer (30), the rewiring layer comprising:
a layer (fig 3C, layer 30 but doesn’t explicitly teach that it is an insulator);
a first electrode pad (bottom pad portion of 33) disposed on a lower surface of the layer (bottom of 30);
a second electrode pad (upper pad portion of 33) on an upper surface of the insulator layer (upper of 30); and
an interlayer connection conductor (33) formed in the layer (30) so as to connect the first electrode pad and the second electrode pad to each other (upper and lower pad portions of 33);
a first chip (21) under the rewiring layer (30) while facing upwardly a surface of the rewiring layer on which the first electrode pad is formed;
a molded resin (26; [0040]) so as to seal the first chip (21); and
a second chip (22) on the rewiring layer (30) while facing downwardly a surface of the rewiring layer on which the second electrode pad is formed;
wherein the first electrode pad and the second electrode pad are disposed so as to face each other with the interlayer connection conductor extending linearly from the first electrode pad to the second electrode pad (linear connection between upper and lower portions of 33);
wherein the first electrode pad is connected to a fourth electrode pad (pad on 21 connected to pad portion of 33), the fourth electrode pad being disposed on a surface of the first chip (21); and
wherein the second electrode pad is connected to a fifth electrode pad (220 connected to upper pad portion of 33), the fifth electrode pad being disposed on a lower surface of the second chip (22).
Chiu does not explicitly disclose that the rewiring layer includes an insulator layer.
Nonetheless, Ishibashi discloses wherein a rewiring layer includes an insulator layer (fig 1, 5a; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the core layer of rewiring layer 30 from an insulator layer as taught by Ishibashi since this will provide electrical separation from the conductive elements thus preventing short circuit operations.
As to claim 2, Chiu in view of Ishibashi disclose the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses wherein the rewiring layer (30) further includes:
a wiring (wiring portion of 33) formed on any one of the lower surface (bottom), the upper surface (top), or an inner layer (inner) of the layer (30), the wiring being connected to one of the first electrode pad (bottom portion of 33) or the fourth electrode pad (upper portion of 33); and
a third electrode pad (lower portion of 33 adjacent to first lower portion of 33) disposed on the lower surface of the layer (30),
wherein the first chip (21) is positioned under the rewiring layer (30) while facing upward a surface of the rewiring layer (30) on which the first electrode pad (lower portion of 33) and the third electrode pad are formed (lower portion of 33 connected to 250); and
external connection conductors (250 including lower via 33) are positioned under the third electrode pad (lower pad portion of 33), the external connection conductors passing through the molded resin (26) from an upper surface to a lower surface thereof (upper and lower of resin 26), and
wherein a part of the wiring is connected to the third pad (wiring of connector 33).
As to claim 3, Chiu in view of Ishibashi the integrated electronic component according to claim 2 (paragraphs above).
He does not disclose wherein the first electrode pad comprises a ground electrode pad for ground and a signal electrode pad of signals, wherein the second electrode pad comprises a ground electrode pad for ground and a signal electrode pad for signals wherein the wiring includes:
a first ground wiring for ground that is formed on the lower first surface of the insulator layer and is connected to the third electrode pad,
a second ground wiring for ground that is formed on the second surface of the insulator layer and is connected to the fourth electrode pad,
a first signal wiring for signals that is disposed between the third electrode pad and the fourth electrode pad, and
a second signal wiring for signals that is disposed between the first ground wiring and the second ground wiring.
Nonetheless, Ishibashi discloses wherein a wiring (fig 17, [0084]) includes:
a first ground wiring for ground (fig 17, [0084]) that is formed on the lower first surface of an insulator layer (6C, [0216]) and is connected to a third electrode pad (12),
a second ground wiring for ground (fig 17, [0084]) that is formed on the second surface (bottom) of the insulator layer (6C, [0216]) and is connected to a fourth electrode pad (9a),
a first signal wiring for signals (fig 17, [0084]) that is disposed between the third electrode pad (12) and the fourth electrode pad (9a), and
a second signal wiring for signals (fig 17, [0084]) that is disposed between the first ground wiring and the second ground wiring (fig 17, [0084]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the wirings of Chiu to be formed of the power/ground and signal interconnections as taught by Ishibashi since this provides for small size and small loss of input/output signals with shortened wiring between stacked chips.
As to claim 4, Chiu in view of Ishibashi the integrated electronic component according to claim 2 (paragraphs above),
Chiu does not disclose wherein the first electrode pad comprises a power-supply electrode pad for power supply, wherein the second electrode pad comprises a power-supply electrode pad for power supply;
wherein the wiring includes:
a first power-supply wiring for power supply that is formed on the first surface of the insulator layer and is connected to the third electrode pad,
a second power-supply wiring for power supply that is formed on the second surface of the insulator layer and is connected to the fourth electrode pad,
a first signal wiring for signals that is disposed between the third electrode pad and the fourth electrode pad, and
a second signal wiring for signals that is disposed between the first power-supply wiring and the second power-supply wiring.
Nonetheless, Ishibashi discloses wherein a wiring (fig 17, [0084]) includes:
a first power-supply wiring for power supply (fig 17, [0084]) that is formed on the first surface of the insulator layer (6C, [0216]) and is connected to the third electrode pad (12),
a second power-supply wiring for power supply (fig 17, [0084]) that is formed on the second surface of the insulator layer (6C, [0216]) and is connected to the fourth electrode pad (9a),
a first signal wiring for signals (fig 17, [0084]) that is disposed between the third electrode pad (12) and the fourth electrode pad (9a), and
a second signal wiring for signals (fig 17, [0084]) that is disposed between the first power-supply wiring and the second power-supply wiring (6C, [0216]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the wirings of He to be formed of the power/ground and signal interconnections as taught by Ishibashi since this provides for small size and small loss of input/output signals with shortened wiring between stacked chips.
As to claim 5, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses a sealing member sealing (26) the first chip (21); and
a connection conductor (250) passing through the sealing member (26),
wherein the rewiring layer (30) further includes:
a wiring (portion of 33) formed on any one of the lower surface (bottom), the upper surface (upper), and an inner layer (inner) of the layer (30), the wiring connected to one of the first electrode pad (lower portion of 33) and the second electrode pad (pad portion of 33); and
a third electrode pad (adjacent pad 33) disposed on the lower surface (lower) of the layer (30), the electrode pad (pad 33) connected to the connection conductor (wiring portion of 33), and
wherein at least a part of the wiring (part of 33) is connected to the third electrode pad (adjacent pad 33).
As to claim 6, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses wherein the first electrode pad and the second electrode pad are connected via the interlayer connection conductor at the shortest distance (fig 3C, direct vertical connection between top and bottom surface of 30 is connected with 33 between upper chip and lower chip).
As to claim 7, Chiu in view of Ishibashi the integrated electronic component according to claim 1 (paragraphs above),
Chiu further discloses wherein the first electrode pad and the second electrode pad are connected together via the interlayer connection conductor at the shortest distance therebetween (fig 3C, direct vertical connection between top and bottom surface of 30 is connected with 33 between upper chip and lower chip).
As to claim 8, Chiu discloses a method for producing an integrated electronic component (figs 3A-C, [0022]) comprising the steps of:
a first step of preparing a rewiring layer (30), the rewiring layer comprising: a layer (30), a first electrode pad (lower pad region of 33) disposed on a lower surface of the layer (30), a second electrode pad (upper pad region of 33) disposed on an upper surface of the layer (3), and an interlayer connection conductor (33) formed in the layer (30) so as to connect the first electrode pad (lower pad) and the second electrode pad (upper pad) to each other; a second step of disposing a first chip (21) on the rewiring layer (30) while facing upwardly a surface of the rewiring layer on which the first electrode pad (lower portion of 33) is formed; a third step of forming a molded resin (26; [0040]) so as to seal the first chip (21); and a fourth step of disposing a second chip (22) on the rewiring layer (30) while facing downwardly a surface of the rewiring layer (30) on which the second electrode pad (upper portion of 33) is formed (see detail shown in figs 2A-C” wherein chip 21 is attached using conductive bumps 210, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to bond facing upwardly using the conductive bumps 210 in fig 3A-C since this provides design flexibility with simplified manufacturability), wherein the first electrode pad and the second electrode pad are disposed so as to face each other with the interlayer connection conductor extending linearly from the first electrode pad to the second electrode pad (interconnect conductor 33 connecting upper and lower sides); wherein the first electrode pad is connected to a fourth electrode pad (pad on chip 21 connected to 33), the fourth electrode pad being disposed on an upper surface of the first chip (pad on chip 21), and wherein the second electrode pad is connected to a fifth electrode pad (220 connected to 33), the fifth electrode pad (220) being disposed on a lower surface of the second chip (22).
Chiu does not explicitly disclose that the rewiring layer includes an insulator layer.
Nonetheless, Ishibashi discloses wherein a rewiring layer includes an insulator layer (fig 1, 5a; [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the core layer of rewiring layer 30 from an insulator layer as taught by Ishibashi since this will provide electrical separation from the conductive elements thus preventing short circuit operations.
As to claim 9, Chiu in view of Ishibashi the method for producing an integrated electronic component according to claim 8 (paragraphs above),
Chiu further discloses wherein the rewiring layer (30) further includes: a wiring (wiring portion of 33) formed on any one of the lower surface, the upper surface, or an inner layer of the layer (inner surface of layer 30), the wiring being connected to one of the first electrode pad or the second electrode pad (33); and a third electrode pad disposed on the lower surface of the insulator layer (adjacent pad portion of 33), wherein the second step comprises the steps of: mounting the first chip (21) on the rewiring layer (30) while facing upwardly a surface of the rewiring layer (30) on which the first electrode pad and the third electrode pad are formed (pad portions of 33); and forming external connection conductors (250) on the third electrode pad (adjacent portion of 33), the external connection conductors passing through the molded resin (26) from an upper surface to a lower surface thereof (top/bottom surfaces), and wherein a part of the wiring is connected to the third electrode pad (wiring portion of 33).
As to claim 10, Chiu in view of Ishibashi the method for producing an integrated electronic component according to claim 9 (paragraphs above),
Chiu does not disclose wherein the first electrode pad comprises a ground electrode pad for ground and a signal electrode pad for signals, wherein the second electrode pad comprises a ground electrode pad for ground and a signal electrode pad for signals, wherein the wiring includes: a first ground wiring for ground that is formed on the lower surface of the insulator layer and is connected to the ground electrode of the first electrode pad, a second ground wiring for ground that is formed on the upper surface of the insulator layer and is connected to the ground electrode of the second electrode pad, a first signal wiring for signals that is disposed between the ground electrode pad of the first electrode pad and the ground electrode pad of the second electrode pad, and a second signal wiring for signals that is disposed between the first ground wiring and the second ground wiring.
Nonetheless, Ishibashi discloses wherein a wiring (fig 17, [0084]) includes:
a first ground wiring for ground (fig 17, [0084]) that is formed on the lower first surface of an insulator layer (6C, [0216]) and is connected to a third electrode pad (12),
a second ground wiring for ground (fig 17, [0084]) that is formed on the second surface (bottom) of the insulator layer (6C, [0216]) and is connected to a fourth electrode pad (9a),
a first signal wiring for signals (fig 17, [0084]) that is disposed between the third electrode pad (12) and the fourth electrode pad (9a), and
a second signal wiring for signals (fig 17, [0084]) that is disposed between the first ground wiring and the second ground wiring (fig 17, [0084]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the wirings of Chiu to be formed of the power/ground and signal interconnections as taught by Ishibashi since this provides for small size and small loss of input/output signals with shortened wiring between stacked chips.
As to claim 11, Chiu in view of Ishibashi the method for producing an integrated electronic component according to claim 9 (paragraphs above),
Chiu does not disclose wherein the first electrode pad comprises a power-supply electrode pad for power supply, wherein the second electrode pad comprises a power-supply electrode pad for power supply, wherein the wiring includes: a first power-supply wiring for power supply that is formed on the lower surface of the insulator layer and is connected to the power-supply electrode pad of the first electrode pad, a second power-supply wiring for power supply that is formed on the upper surface of the insulator layer and is connected to the power-supply electrode pad of the second electrode pad, a first signal wiring for signals that is disposed between the power-supply electrode pad of the first electrode pad and the power-supply electrode pad of the second electrode pad, and a second signal wiring for signals that is disposed between the first power-supply wiring and the second power-supply wiring.
Nonetheless, Ishibashi discloses wherein a wiring (fig 17, [0084]) includes:
a first power-supply wiring for power supply (fig 17, [0084]) that is formed on the first surface of the insulator layer (6C, [0216]) and is connected to the third electrode pad (12),
a second power-supply wiring for power supply (fig 17, [0084]) that is formed on the second surface of the insulator layer (6C, [0216]) and is connected to the fourth electrode pad (9a),
a first signal wiring for signals (fig 17, [0084]) that is disposed between the third electrode pad (12) and the fourth electrode pad (9a), and
a second signal wiring for signals (fig 17, [0084]) that is disposed between the first power-supply wiring and the second power-supply wiring (6C, [0216]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the wirings of He to be formed of the power/ground and signal interconnections as taught by Ishibashi since this provides for small size and small loss of input/output signals with shortened wiring between stacked chips.
As to claim 12, Chiu in view of Ishibashi the method for producing an integrated electronic component according to claim 8 (paragraphs above),
Chiu further discloses the integrated electronic component comprising: a sealing member (26) sealing the first chip (21); and a connection conductor (250) passing through the sealing member (26), wherein the rewiring layer (30) further includes: a wiring (wiring portion of 33) formed on any one of the lower surface, the upper surface, and an inner layer of the layer (30), the wiring connected to one of the first electrode pad and the second electrode pad (33); and a third electrode pad disposed on the lower surface of the insulator layer (adjacent 33), the electrode pad connected to the connection conductor (250), and wherein at least a part of the wiring is connected to the third electrode pad (wiring portion of 33).
As to claim 13, Chiu in view of Ishibashi the method for producing an integrated electronic component according to claim 8 (paragraphs above),
Chiu further discloses wherein the first electrode pad and the second electrode pad are connected via the interlayer connection conductor at the shortest distance (fig 3C, direct vertical connection between top and bottom surface of 30 is connected with 33 between upper chip and lower chip).
As to claim 14, Chiu in view of Ishibashi the method for producing an integrated electronic component according to claim 8 (paragraphs above),
Chiu further discloses wherein the first electrode pad and the second electrode pad are connected together via the interlayer connection conductor at the shortest distance therebetween (fig 3C, direct vertical connection between top and bottom surface of 30 is connected with 33 between upper chip and lower chip).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 2021/0349260 A1 and US 2016/0021753 A1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 11/18/2025
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