DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 9-15, and 17-19 are rejected under 35 U.S.C. 102 as being anticipated by Loghmany et al. ( US 2022/0344457 A1; hereinafter Loghmany )
Regarding claim 9, Loghmany teaches a method of fabricating a wafer ( Fig. 6 #600 ) containing a plurality of high-electron-mobility transistors (HEMTs) ( [0039] the method #600 describes a method to fabricate enhancement-mode HEMTs and depletion-mode HEMTs in parallel on the same wafer), the method comprising: providing semiconductor layers ( [0041] a series of trenches and fins is formed in the semiconductor layer ) capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMTs ( [0019] The HEMT #100 further includes semiconductor layers #140 capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMT #100), wherein the semiconductor layers comprise a first layer of aluminum gallium nitride (AIGaN) ( [0022] the first semiconductor material includes aluminum gallium nitride (ALGaN) and a second layer of gallium nitride (GaN) ( [0022] the second semiconductor material may include gallium nitride (GaN)), whereby the concentration of Al and thickness of AIGaN give rise to a characteristic threshold voltage ( [0016] Other techniques involve the reduction of the size of fins, but so far such fin features have only been fabricated at sizes as low as about 50 nanometers. At this size, such fin features result in HEMTs with positive threshold voltages nearly equal to about 0 volts) ; for a first one of said HEMTs: forming a series of first trenches ( Fig. 1 #152 ) and first fins ( Fig. 1 #154 ) in the semiconductor layers ( Fig. 1 #140 ) over a first active area ( Fig. 1 #150 ) of the semiconductor layers ( Fig. 1 #140 ) on which a first gate contact terminal ( Fig. 1 #130 ) of the first one of said HEMTs is to be set down, wherein the width of the first fins ( [0023] The active area #150 includes a series of fins #154 having widths #153 equal to or less than about 30 nanometers ) is chosen to shift the characteristic threshold voltage to a new threshold voltage ( as discussed above ); setting down the first gate contact terminal ( Fig. 1 #130 ) across the first fins ( Fig. 1 #154 ); and setting down a first source contact terminal ( Fig. 1 #110 ) and a first drain contact terminal ( Fig. 1 #120 ) on either side of the first gate contact terminal ( Fig. 1 #130 ) outside of the first active area ( Fig. 1 #150); and for a further one of said HEMTs: forming a series of further trenches ( [0041] a series of trenches ) and further fins ( [0041] and fins ) in the semiconductor layers ( [0041] formed in the semiconductor layer ) over a further active area ( [0041] in an active area of the semiconductor layer ) of the semiconductor layers on which a further gate contact terminal ( [0041] on which a gate contact terminal ) of the HEMT is to be set down ( [0041] HEMT is to be set down ), wherein the width of the further fins is less than the width of the first fins ( [0041] the fins having widths equal to or less than about 30 nm across ) to shift the characteristic threshold voltage below the new threshold voltage of the first one of said HEMTs ( as discussed above ) ; setting down a further gate contact terminal ( [0041] the gate contact terminal is set down ) across the further series of fins ( [0041] across the fins ); and setting down a further source contact terminal and a further drain contact terminal on either side of the further gate contact terminal outside of the further active area ( [0041] Source contact terminal and drain contact terminals are set down on either side of the gate contact terminal outside of the area ).
Regarding claim 10, Loghmany teaches the method of claim 9 ( as discussed above), wherein forming the series of trenches ( Fig. 1 #152 ) and fins ( Fig. 1 #154 ) comprises: covering the semiconductor layers with an electrosensitive resist layer ( [0036] the semiconductor layers are covered with an electrosensitive resist layer ); patterning the fins into the electrosensitive resist layer by electron beam lithography to form a mask ( [0037] the series of fins are patterned using the electrosensitive resist layer by electron beam lithography, thereby forming a mask from the electrosensitive resist layer ); and dry etching the trenches into the semiconductor layers through the mask ( [0038] the series of trenches is dry etched into the semiconductor layer through the mask).
Regarding claim 11, Loghmany teaches the method of claim 10 ( as discussed above), wherein dry etching the series of trenches into the semiconductor layers comprises inductively coupled plasma - reactive ion etching(ICP-RIE) ( [0038] The trenches may be dry etched with chlorine-based dry etching and by inductively coupled plasma-reactive ion etching (ICP-RIE)).
Regarding claim 12, Loghmany teaches the method of claim 10 ( as discussed above), wherein the electrosensitive resist layer comprises hydrogen silsesquioxane (HSQ) ( [0036] The electrosensitive resist layer may include hydrogen silsesquioxane (HSQ)).
Regarding claim 13, Loghmany teaches the method of claim 9 (as discussed above), wherein the gate contact terminals ( Fig. 2A and 2B #130 ) are set down perpendicular to the fins ( [ 0024] The trenches #152 and fins #154 run perpendicular to the direction of the gate contact terminal #130).
Regarding claim 14, Loghmany teaches the method of claim 9 (as discussed above), wherein the trenches ( Fig. 4B trenches #452 ) extend through the semiconductor layers ( Fig. 4B semiconductor layer #440 ) past a depth at which the two-dimensional electron sheet is to be formed ( Fig. 4B trenches extend past the two-dimensional electron sheet region #445).
Regarding claim 15, Loghmany teaches the method of claim 9 ( as discussed above), wherein the width of the fins ( [0017] fins at sizes equal to or less than about 30 nanometers) is chosen to shift the characteristic threshold voltage to a voltage that is sufficient for creating a depletion mode HEMT ( [0042] a depletion-mode HEMT is fabricated into the semiconductor layers ).
Regarding claim 17, Loghmany teaches a device comprising: semiconductor layers comprising a first layer of aluminum gallium nitride (AIGaN) ( [0022] the first semiconductor material includes aluminum gallium nitride (ALGaN) and a second layer of gallium nitride (GaN) ) ( [0022] the second semiconductor material may include gallium nitride (GaN)), said layers being capable of sustaining a two-dimensional electron sheet to enable electrical current to flow ( [0019] The HEMT #100 further includes semiconductor layers #140 capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMT #100 ), the semiconductor layers comprising a plurality of active areas on which gate contact terminals are to be set down ( [0042] a depletion- mode HEMT is fabricated into the semiconductor layers ( which contains an active layer)), the active areas comprising a series of trenches and fins ( [0041] a series of trenches and fins ), the fins having different widths over each active area ( [0041] the fins having widths equal to or less than about 30 nm across ); a plurality of drain contact terminals adjacent respective ones of the active areas ( [0042 Fabrication of the depletion-mode HEMT involves at least setting down a gate contact terminal, and a source contact terminal and a drain contact terminal on either side of the gate contact terminal ); a plurality of source contact terminals adjacent respective ones of the active areas ( as discussed above) ; and a plurality of gate contact terminals set down across the fins of respective ones of the active areas ( [0041] The gate contact terminal is set down across the fins ), such that the device comprises a plurality of AIGaN/GaN high-electron-mobility transistors (HEMTs) having different threshold voltages ( [0039] the method #600 describes a method to fabricate enhancement-mode HEMTs and depletion-mode HEMTs in parallel on the same wafer ).
Regarding claim 18, Loghmany teaches the device of claim 17 ( as discussed above), wherein the gate contact terminals ( Fig. 2A and 2B #130 ) are set down perpendicular to the fins ( [ 0024] The trenches #152 and fins #154 run perpendicular to the direction of the gate contact terminal #130).
Regarding claim 19, Loghmany teaches the device of claim 17 ( as discussed above), wherein the trenches ( Fig. 4B trenches #452 ) extend through the semiconductor layers ( Fig. 4B semiconductor layer #440 ) past a depth at which the two-dimensional electron sheet is to be formed ( Fig. 4B trenches extend past the two-dimensional electron sheet region #445).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5 are rejected under U.S.C. 103 as being unpatentable over Yamada; US 9071167 B2; 04/2014 in view of Kang et al.; US 2016/0315088 A1; 11/2015
Claim 1: Yamada discloses a method for fabricating a AIGaN/GaN high-electron-mobility transistor (HEMT), the method comprising: providing semiconductor layers capable of sustaining a two-dimensional electron sheet to enable electrical current to flow through the HEMT ( as shown in Fig. 5) , wherein the semiconductor layers comprise a first layer of aluminum gallium nitride (AIGaN) (Fig. 5 #4) and a second layer of gallium nitride (GaN) ( Fig. 5 #2), whereby the concentration of Al and thickness of AIGaN give rise to a characteristic threshold voltage ( Col. 10 Lines 29 – 35 the threshold value of the gate voltage can be controlled to become a desired positive value by the gate control layer which has been formed so as to have a predetermined polarization by controlling the composition and the thickness of the mixed crystal ); ; wherein the width of the fins is chosen to shift the characteristic threshold voltage to a new threshold voltage ( Col. 10 Lines 29 – 35 the threshold value of the gate voltage can be controlled to become a desired positive value by the gate control layer which has been formed so as to have a predetermined polarization by controlling the composition and the thickness of the mixed crystal ), and wherein the new threshold voltage increases with reduction in the width of the fins ( as discussed above ).
Yamada does not appear to disclose forming a series of trenches and fins in the semiconductor layers in an active area of the semiconductor layers on which gate contact terminals are to be set down; and setting down gate contact terminals across the fins at the active area.
However, Kang teaches forming a series of trenches ( Fig. 16 #705 ) and fins ( Fig. 16 #732 ) in the semiconductor layers in an active area ( Fig. 16 #704) of the semiconductor layers on which gate contact terminals are to be set down ( Fig. 16 #700G ); and setting down gate contact terminals across the fins at the active area ( as shown in Fig. 16 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kang with Yamada to implement forming a series of trenches and fins in the semiconductor layers in an active area of the semiconductor layers on which gate contact terminals are to be set down; and setting down gate contact terminals across the fins at the active area because this creates high-performance 3D transistors.
Claim 5: Yamada and Kang disclose the method of claim 1 ( as discussed above).
Yamada teaches the gate contact terminals ( Fig. 6a gate electrode connection layer #8 ) are set down perpendicular to the fins ( as shown in Fig. 6a ).
Claim 2 is rejected under U.S.C. 103 as being unpatentable over Yamada; US 9071167 B2; 04/2014 in view of Pao et al.; US 2020/0176447 A1; 11/2019
Claim 2: Yamada discloses the method of claim 1 (as discussed above).
Yamada does not appear to disclose forming the series of trenches and fins comprises: covering the semiconductor layers with an electrosensitive resist layer; patterning the fins into the electrosensitive resist layer by electron beam lithography to form a mask; and dry etching the trenches into the semiconductor layers through the mask.
However, Pao teaches forming the series of trenches ( [0019] In some implementations, isolation feature #122 includes a multi-layer structure that fills trenches ) and fins ( Fig. 2A fins #120A, #120B, #120C, and #120D) comprises: covering the semiconductor layers with an electrosensitive resist layer ( [0018] The lithography process can include forming a resist layer on a mask layer disposed over substrate #110 ); patterning the fins into the electrosensitive resist layer by electron beam lithography to form a mask ( as discussed above ); and dry etching the trenches into the semiconductor layers through the mask ( [0014] etching back the p-type work function material to the second thickness in the second transistor region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Pao with Yamada to implement forming the series of trenches and fins comprises: covering the semiconductor layers with an electrosensitive resist layer; patterning the fins into the electrosensitive resist layer by electron beam lithography to form a mask; and dry etching the trenches into the semiconductor layers through the mask because the electrosensitive material is sensitive to electron beam exposure allowing for high-resolution patterning.
Claim 3 is rejected under U.S.C. 103 as being unpatentable over Yamada; US 9071167 B2; 04/2014 in view of Pao et al.; US 2020/0176447 A1; 11/2019
as it relates to claim 2 and further in view of Ahn et al.; US 2017/0236909 A1; 08/2016
Claim 3: Yamada and Pao disclose the method of claim 2 ( as discussed above).
Neither Yamada nor Pao appear to disclose dry etching the series of trenches into the semiconductor layers comprises inductively coupled plasma - reactive ion etching (ICP- RIE).
However, Ahn teaches dry etching the series of trenches ( Fig. 5. #10A) into the semiconductor layers ( Fig. 5 #10 ) comprises inductively coupled plasma - reactive ion etching (ICP- RIE) ( [0056] The etch process may be performed using a dry etch method or a wet etch method, such as Reactive Ion Etching (RIE), Magnetically Enhanced Reactive Ion Etching (MERIE), or ICP (Inductive Coupled Plasma)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ahn with Pao and Yamada to implement dry etching the series of trenches into the semiconductor layers comprises inductively coupled plasma - reactive ion etching (ICP- RIE) because this technique offers unparalled control for creating deep, high-aspect ratio features.
Claim 4 is rejected under U.S.C. 103 as being unpatentable over Yamada; US 9071167 B2; 04/2014 in view of Pao et al.; US 2020/0176447 A1; 11/2019
as it relates to claim 2 and further in view of Then et al.; US 2020/0219878 A1; 01/2019
Claim 4: Yamada and Pao disclose the method of claim 2 ( as discussed above).
Neither Yamada nor Pao appear to disclose the electrosensitive resist layer comprises hydrogen silsesquioxane (HSQ).
However, Then teaches the electrosensitive resist layer ( [0043] the gate dielectric material #120 and the gate electrode material #122 may be surrounded by a gate spacer, not shown in Fig. 1) comprises hydrogen silsesquioxane (HSQ) ( [0043] A gate spacer may be made of a low-k dielectric material. Examples of low-k materials that may be used as the dielectric gate spacer may include hydrogen silsesquioxane (HSQ)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Then with Pao and Yamada to implement the electrosensitive resist layer comprises hydrogen silsesquioxane (HSQ) because this material is critical for fabricating nanoscale features in electron-beam lithography.
Claims 6 and 7 are rejected under U.S.C. 103 as being unpatentable over Yamada; US 9071167 B2; 04/2014 in view of Loghmany et al.; US 2022/0344457 A1; 09/2020
Claim 6: Yamada discloses the method of claim 1 ( as discussed above)
Yamada does not appear to disclose the trenches extend through the semiconductor layers past a depth at which the two-dimensional electron sheet is to be formed.
However, Loghmany teaches the trenches ( Fig. 4B trenches #452 ) extend through the semiconductor layers ( Fig. 4B semiconductor layer #440 ) past a depth at which the two-dimensional electron sheet is to be formed ( Fig. 4B trenches extend past the two-dimensional electron sheet region #445).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Loghmany with Yamada to implement the trenches extend through the semiconductor layers past a depth at which the two-dimensional electron sheet is to be formed because this improves breakdown voltage by reducing electric field crowding.
Claim 7: Yamada discloses the method of claim 1 ( as discussed above).
Yamada does not appear to disclose the width of the fins is chosen to shift the characteristic threshold voltage to a voltage that is sufficient for creating a depletion mode HEMT.
However, Loghmany teaches wherein the width of the fins ( [0017] fins at sizes equal to or less than about 30 nanometers) is chosen to shift the characteristic threshold voltage to a voltage that is sufficient for creating a depletion mode HEMT ( [0042] a depletion-mode HEMT is fabricated into the semiconductor layers ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Loghmany with Yamada to implement the width of the fins is chosen to shift the characteristic threshold voltage to a voltage that is sufficient for creating a depletion mode HEMT because in “normally-on” transistors the width of the fins tunes the negative Vth to a specific, required value for the circuit.
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Yamada; US 9071167 B2; 04/2014 in view of Radosavljevic et al.; US 12,125,888 B2; 09/2017
Claim 8: Yamada discloses the method of claim 1 ( as discussed above).
Yamada does not appear to disclose the width of each of the fins is greater than 30 nm and up to 500 nm across.
However, Radosavljevic teaches the width of each of the fins is greater than 30 nm and up to 500 nm across ( Col. 6 lines 54 – 57 each fin #102B has a width, WF between 100 nm – 500 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Radosavljevic with Yamada to implement the width of each of the fins is greater than 30 nm and up to 500 nm across because this balances high-power performance, thermal management, and manufacturability.
Claim 16 is rejected under U.S.C. 103 as being unpatentable over Loghmany et al.; US 2022/0344457 A1; 09/2020 in view of Radosavljevic et al.; US 12,125,888 B2; 09/2017
Claim 16: Loghmany discloses the method of claim 9 ( as discussed above).
Loghmany does not appear to disclose the width of each of the fins is greater than 30 nm and up to 500 nm across.
However, Radosavljevic teaches the width of each of the fins is greater than 30 nm and up to 500 nm across ( Col. 6 lines 54 – 57 each fin #102B has a width, WF between 100 nm – 500 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Radosavljevic with Loghmany to implement the width of each of the fins is greater than 30 nm and up to 500 nm across because this balances high-power performance, thermal management, and manufacturability.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over Loghmany et al.; US 2022/0344457 A1; 09/2020 in view of Babic et al.; US 8,674,405 B1; 02/2012
Claim 20: Loghmany discloses the device of claim 17 (as discussed above)
Loghmany does not appear to disclose at least one isolation trench between each respective one of the HEMTs.
However, Babic teaches at least one isolation trench between each respective one of the HEMTs ( Col. 3 lines 7- 10 Additionally, individual HEMTs may be isolated from adjacent devices on the same wafer or chip using isolation trenches #12 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Babic with Loghmany to implement at least one isolation trench between each respective one of the HEMTs because this can prevent parasitic leakage currents and electrical cross-talk, ensuring that each device functions independently.
Response to Amendment/Arguments
Applicant’s arguments, see pages 7-8 of remarks, filed 12/31/2025, with respect to the rejection of claim 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kang.
Applicant's arguments, see page 9, filed 12/31/2025, with respect to the effective filing date of Loghmany have been fully considered but they are not persuasive. Loghmany has a provisional application 62/903231 filed on Sept. 20, 2019 which reads on the claim rejections. The provisional application fully supports the publication of Loghmany (2022/0344457) as utilized in the rejection above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817