DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election of species A, Figs. 1-14, claims 1-4 and 8-17, in the reply filed on 10/3/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 5-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/3/25.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kitamoto, US Publication No. 2012/0327609 A1 (from the IDS).
Kitamoto anticipates:
1. A semiconductor device comprising (see figs. 103):
a substrate (80) having an obverse surface (e.g. top surface) facing in a thickness direction;
a first wiring layer (70, 84) disposed on the obverse surface;
a second wiring layer (72, 90) disposed on the obverse surface and spaced apart from the first wiring layer in a first direction orthogonal to the thickness direction;
a first semiconductor element (50) having a first obverse electrode (N) and a first reverse electrode (P) located opposite to each other in the thickness direction, the first reverse electrode (p) being bonded to the first wiring layer (70, 84);
a second semiconductor element (54) having a second obverse electrode (P) and a second reverse electrode (N) located opposite to each other in the thickness direction, the second reverse electrode (N) being bonded to the second wiring layer (72, 90); and
a conductive member (78) spaced apart from the substrate in the thickness direction and bonded to the first obverse electrode (N) and the second obverse electrode (P), wherein
polarities of the first obverse electrode (N) and the second obverse electrode (P) are different from each other,
the substrate includes an exposed portion (e.g. exposed portion along line C2 shown in fig. 3) located between the first wiring layer (70, 84) and the second wiring layer (72, 90), and
the conductive member (78) overlaps with the exposed portion, as viewed in the thickness direction. See Kitamoto at para. [0001] – [0109], figs. 1-17.
2. The semiconductor device according to claim 1, further comprising:
a first gate terminal (74) spaced apart from the first wiring layer (70, 84); and
a second gate terminal (76) spaced apart from the second wiring layer (72, 90), wherein
the first semiconductor element (50) has a first gate electrode (68 right) electrically connected to the first gate terminal, and
the second semiconductor element (54) has a second gate electrode (68 left) electrically connected to the second gate terminal (76), fig. 3.
Claim(s) 1-4, 8, 13 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshimoto, JP 2011036016 A (see attached English machine translation).
Yoshimoto anticipates:
1. A semiconductor device comprising (see figs. 1 and 10-15):
a substrate (10) having an obverse surface (e.g. top surface) facing in a thickness direction (e.g. z-axis);
a first wiring layer (40) disposed on the obverse surface;
a second wiring layer (50) disposed on the obverse surface and spaced apart from the first wiring layer in a first direction (e.g. vertical, y-axis) orthogonal to the thickness direction;
a first semiconductor element (130) having a first obverse electrode (132) and a first reverse electrode (131) located opposite to each other in the thickness direction, the first reverse electrode (131) being bonded to the first wiring layer (40);
a second semiconductor element (140) having a second obverse electrode (141) and a second reverse electrode (142) located opposite to each other in the thickness direction, the second reverse electrode (142) being bonded to the second wiring layer (50); and
a conductive member (75) spaced apart from the substrate in the thickness direction and bonded to the first obverse electrode (132) and the second obverse electrode (141), wherein
polarities of the first obverse electrode and the second obverse electrode are different from each other (e.g. see “P” and “N” in figs. 10 and 14),
the substrate (50) includes an exposed portion located between the first wiring layer (40) and the second wiring layer (50), and
the conductive member (75) overlaps with the exposed portion, as viewed in the thickness direction. See Yoshimoto at machine translation pages 1-28, figs. 1-17.
2. The semiconductor device according to claim 1, further comprising:
a first gate terminal (52) spaced apart from the first wiring layer (40); and
a second gate terminal (e.g. horizontal 53) spaced apart from the second wiring layer (50), wherein
the first semiconductor element (130) has a first gate electrode (134) electrically connected to the first gate terminal (52), and
the second semiconductor element (140) has a second gate electrode (144) electrically connected to the second gate terminal (e.g. horizontal 53), figs. 10-13.
3. The semiconductor device according to claim 2, further comprising (see figs. 10-15):
a first detection terminal (e.g. P node on input side in fig. 1) spaced apart from the first wiring layer (40) and electrically connected to the first obverse electrode (132) (e.g. See page 3 “In each upper arm side switching element (130), the collector (131) is electrically connected to the positive node (P) on the input side, and the emitter (132) is electrically connected to the corresponding output terminal (U, V, W)…The positive node (P) on the input side is constituted by a connection terminal and is connected to the positive connection terminal of the converter circuit (11).”), and
a second detection terminal (e.g. N node on input side of fig. 2) spaced apart from the second wiring layer (50) and electrically connected to the second reverse electrode (142) (e.g. See page 3 “ In each lower arm side switching element (140), the collector (141) is electrically connected to the corresponding output terminal (U, V, W), and the emitter (142) is connected to the negative node (N) on the input side…The negative side node (N) on the input side is constituted by a connection terminal and is connected to the negative side connection terminal of the converter circuit (11).”).
4. The semiconductor device according to claim 3, further comprising a gate electrode lead-out layer (e.g. vertical 153) spaced apart from the second wiring layer (50) and electrically connected to the second gate terminal (e.g. horizontal 153), wherein
the first gate electrode (134) is located on a same side as the first obverse electrode (132) in the thickness direction, and
the second gate electrode (144) is located on a same side as the second reverse electrode (142) in the thickness direction and bonded to the gate electrode lead-out layer (e.g. 143 vertical) (e.g. See page 14, “The metal wiring board (53) is joined to the gate (144) of the lower arm side switching element (140) by ball solder.”), figs. 10-15.
8. The semiconductor device according to claim 3, further comprising a pair of diodes (120, 110) bonded to the first wiring layer (40) and the second wiring layer (50), respectively, wherein the pair of diodes are bonded to the conductive member (75), figs. 10-15.
13. The semiconductor device according to claim 3, wherein the first gate terminal (52) is located on an opposite side of the second wiring layer (50) with respect to the first wiring layer (40) in the first direction (e.g. vertical, y-axis), and
the second gate terminal (e.g. horizontal 53) is located on an opposite side of the first wiring layer (40) with respect to the second wiring layer (50) in the first direction, fig. 10.
14. The semiconductor device according to claim 13, wherein the first detection terminal (e.g. P node on input side in fig. 1 is electrically conned to 130 at page 3) is located closer to the first gate terminal (134) than to the second gate terminal (144), and
the second detection terminal (e.g. N node on input side of fig. 2 is electrically connected to 140 at page 3) is located closer to the second gate terminal (144) than to the first gate terminal (134), figs. 1 and 10.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9, 11, 12, 15 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimoto, as applied to claim 1 above, in view of Arai et al., US Publication No. 2020/0135702 A1.
Regarding claim 9:
Yoshimoto teaches all the limitations of claim 1 above, but does not expressly teach further comprising a capacitor bonded to the first wiring layer and the second wiring layer.
In an analogous art, Arai teaches, in fig. 1, a power conversion device that converts DC power to AC power, similar to Yoshimoto. Arai further teaches the power conversion device comprises a capacitor (4), para. [0039].
It would have been obvious to a person of ordinary skill in the art to modify Yoshimoto with Arai to form “a capacitor bonded to the first wiring layer and the second wiring layer” because Arai teaches a capacitor provides for “smoothing”. See Arai at para. [0039].
Regarding claim 11:
Yoshimoto further teaches:
11. The semiconductor device according to claim 3, further comprising (see figs. 1 and 1015_:
a first input terminal (e.g. See page 3, “The positive node (P) on the input side is constituted by a connection terminal and is connected to the positive connection terminal of the converter circuit (11).”) electrically connected to the first wiring layer (40);
a second input terminal (e.g. See page 3, “The negative side node (N) on the input side is constituted by a connection terminal and is connected to the negative side connection terminal of the converter circuit (11).”) electrically connected to the second wiring layer (50); and
an output terminal (55, u, v, w) spaced apart from the substrate in a sense of the thickness direction which the obverse surface faces and electrically connected to the conductive member (75), wherein…
Yoshimoto does not expressly teach:
the first input terminal and the second input terminal are located on a first side of the substrate in a second direction orthogonal to the thickness direction and the first direction, and
the output terminal is located on a second side of the substrate in the second direction.
In an analogous art, Arai teaches:
(see fig. 12) the input terminal (21) are located on a first side (e.g. pointing upward on the page) of the substrate in a second direction orthogonal to the thickness direction and the first direction, and
the output terminal (22) is located on a second side (e.g. pointing downward on the page) of the substrate in the second direction. See Arai at para. [0105], also see fig. 1.
Arai further teaches the input terminal (21 in fig. 2) can comprise a first input terminal (21 left) and a second input terminal (21 right), similar to Yoshimoto.
12. The semiconductor device according to claim 11, wherein the output terminal (55) is bonded to the conductive member (75), figs. 11-13.
Regarding claim 15:
Arai further teaches (see figs. 3-4) a sealing resin (11) covering the elements of the power conversion device including a wiring layer (15), a first semiconductor element (12), the second semiconductor element (13) and a conductive member (19).
wherein the sealing resin (11) includes a part held between an exposed portion of the wiring layer (15) and the conductive member (19) in the thickness direction, para. [0046].
It would have been obvious to a person of ordinary skill in the art to modify Yoshimoto with Arai to form “further comprising a sealing resin covering the first wiring layer, the second wiring layer, the first semiconductor element, the second semiconductor element and the conductive member, wherein the sealing resin includes a part held between the exposed portion and the conductive member in the thickness direction” because a sealing resin can protect elements of the power conversion device from the surrounding environment.
Regarding claim 16:
It would have been obvious to a person of ordinary skill in the art to modify Yoshimoto with Arai to form “wherein the substrate has a reverse surface facing away from the obverse surface in the thickness direction, and the reverse surface is exposed from the sealing resin” because Arai teaches when a reverse face is exposed by the sealing this helps with heat dissipation. See Arai at para. [0053] – [0056].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Yoshimoto with the teachings of Arai because (i) A sealing resin can protect elements of the power conversion device from the surrounding environment; (ii) Forming the input terminal and output terminal on opposite sides can more effectively restrict current imbalance (e.g. Arai at para. [0105]); and (iii) When a reverse face is exposed by the sealing this helps with heat dissipation (e.g. Arai at para. [0053] – [0056]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimoto, as applied to claim 1 above, in view of Kitamoto, US Publication No. 2012/0327609 A1 (from the IDS).
Regarding claim 17:
Yoshimoto teaches all the limitations of claim 1 above, but does not expressly teach a heat sink bonded to the reverse surface.
In an analogous art, Kitamoto teaches a heat sink (82) bonded to the reverse surface (of 80), fig. 3.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Yoshimoto with the teachings of Kitamoto because the heat sink helps to cool the inverter. See Kitamoto at para. [0047].
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
9 December 2025