DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment & Claims’ Status
The Amendment filed on 12/15/2025 has been entered. Claims 16-25, 27, and 29-33 are currently pending and being examined. Claims 16-17, 27, 29, and 33 have been amended. Claims 26, 28, and 34 have been cancelled by the Applicant. No claims have been newly added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 16-22, 24-25, 27, 29, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Kawai (JP 2013243275 A, of record) in view of Beyer et al (US 5,313,094 A, hereafter Beyer).
Re Claim 16, Kawai discloses a method for producing a transistor with high electron mobility (FIGS. 11-12, with reference to FIG. 3; [0080]-[0083]), comprising:
a) growing an epitaxial layer (51, 14; [0052], [0080]-[0085]), which comprises a semiconductor material ([0080]), onto a front side of a flat substrate (52; [0082]), wherein the flat substrate (52) is
i) removable from the epitaxial layer (51, 14) by chemical etching ([0083]) and/or dry etching; and/or
ii) removable from the epitaxial layer by application of laser radiation having a certain wavelength;
b) applying at least one lateral and/or vertical transistor structure (18, 23, 24, 25; [0043]) to a front side of the epitaxial layer (top side of 51, 14 in FIG. 11; [0083]);
c) applying a temporary wafer (28; FIG. 3; [0067]) to the front side of the epitaxial layer (top side of 51, 14 in FIG. 11; [0083]);
d) removing the flat substrate (52; [0083]) from the bottom side of the epitaxial layer (51, 14; [0083]);
e) applying a thermally conducting layer (11, 12; [0080]) to the bottom side of the epitaxial layer (51, 14; [0080]); and
f) completely removing the temporary wafer (28; [0071]);
wherein the flat substrate (52) is completely removed from the bottom side of the epitaxial layer (51, 14; [0083]), and the thermally conducting layer (11, 12) is applied to the bottom side of the epitaxial layer (51, 14; [0080]) so that the thermally conducting layer (11, 12) contacts at least 80% of the bottom side of the epitaxial layer (51, 14; [0080]);
wherein the epitaxial layer (51, 14) comprises a semiconductor material (14; [0052]) selected from the group consisting of GaN, AIN ([0052]), AlxGa1-xN, InGaN, InAIGaN, AlScN, Ga2O3 and combinations thereof, wherein x is a number between 0 and 1,
wherein the thermally conducting layer (11, 12) on the bottom side of the epitaxial layer (51) comprises a material (12) that is
electrically insulating ([0045]); or
electrically conductive, wherein the electrically conductive material has, in the direction of the epitaxial layer, a height in the range of 50 nm to 5um.
Kawai does not explicitly disclose wherein the electrically insulating material (12) is selected from the group consisting of TaC, diamond, and a combination thereof.
However, Beyer teaches a device comprising wherein the electrically insulating material (22; column 2, lines 42-67) is selected from the group consisting of TaC, diamond (column 2, lines 61-67), and a combination thereof.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Kawai with the limitations taught by Beyer to substitute diamond as a functionally equivalent thermally conductive material due to its high electrical resistivity and thermal conduction capabilities as taught by Beyer (column 2, lines 42-67).
Re Claim 17, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches wherein the epitaxial layer (51, 14)
i) is grown on in the direction of the flat substrate (52) up to a height in the range of 200 nm to 50 um ([0085]: ~3 um for thickness of 51, [0047]: ~200 nm for thickness of 14); and/or
ii) has an extension of 25.4 mm to 300 mm in a direction parallel to the flat substrate.
Re Claim 18, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches wherein the flat substrate (52)
i) is suitable for growing epitaxially a layer comprising a material selected from the group consisting of GaN, AIN ([0008], Si(111) is at least suitable for growing AlN), AlxGa1-xN, InGaN, InAIGaN, AIScN, Ga2O3 and combinations thereof, each of said material is optionally doped, with x being a number between 0 and 1; and/or
ii) comprises a material selected from the group consisting of silicon carbide, AIN, sapphire, and combinations and mixtures thereof.
Re Claim 19, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches wherein the flat substrate (52) has a height in the range of 100 um to 1.5 mm in the direction of the epitaxial layer (51, 14; [0034]).
In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists (see MPEP 2144.05.I). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 16 with the limitations taught by Kawai to choose a height of 100 um for the flat substrate (Kawai: 52) to be in the specified range to provide appropriate thickness for epitaxial growth as taught by Kawai ([0034]).
Re Claim 20, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches applying at least one electrical front contact (17; [0043]) to an upper side of the epitaxial layer (51, 14; [0043]).
Re Claim 21, Kawai and Beyer teach the method according to Claim 20, while Kawai further teaches wherein the application of the at least one electrical front contact (17) is carried out
i) after the application of at least one lateral and/or vertical structure, which is selected from the group consisting of transistor, Schottky diode structure, p-n diode structure, PIN diode structure, and combinations thereof, to the epitaxial layer, or after the removal of the temporary wafer; and/or
ii) by utilizing a material that has an electrical conductivity in the range of 10^-6 omega-m to 10^-8 omega-m; and/or
iii) by utilizing a material that has a thermal conductivity in the range of 10 to 2300 W/(mK); and/or
iv) by utilizing a material that comprises a metal; and/or
v) in such a way that the at least one electrical front-side contact has a height in the range of 50nm to 10 pm in the direction of the epitaxial layer; and/or
vi) by way of deposition ([0052]) or bonding.
Re Claim 22, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches wherein the at least one lateral and/or vertical transistor structure (18, 23, 24, 25)
i) is applied in the form of a layer ([0043]); and
ii) comprises a semiconductor (18; [0043]); and/or
iii) is processed by a step selected from the group consisting of demetallization, wet-chemical etching, dry-chemical etching, insulator coating, ion implantation, diffusion, and combinations thereof.
Re Claim 24, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches wherein the complete removal of the flat substrate (52) from the bottom side of the epitaxial layer (51, 14) is effected by
i) chemical etching ([0083]), dry etching, and combinations thereof; and/or
ii) applying laser radiation having a certain wavelength.
Re Claim 25, Kawai and Beyer teach the method according to Claim 16, while Kawai further teaches wherein the thermally conducting layer (11, 12) on the bottom side of the epitaxial layer
i) comprises a material that has a specific thermal conductivity in the range of 10 to 2300 W/(mK); and/or
ii) has been or is applied by way of deposition or bonding ([0084]).
Re Claim 27, Kawai and Beyer teach the method according to Claim 16, while Beyer further teaches wherein the electrically insulating material
has a specific electrical resistance of at least 10^10 ohm-m; and/or
is polycrystalline (column 2, lines 58-59); and/or
has a height in the range of 20 um to 1.5 mm in the direction of the epitaxial layer.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 16 with the limitations taught by Beyer to substitute polycrystalline diamond as a functionally equivalent thermally conductive material due to its high electrical resistivity and thermal conduction capabilities as taught by Beyer (column 2, lines 42-67).
Re Claim 29, Kawai and Beyer teach the method according to Claim 16, while it is not necessary for them to disclose any further described limitations of a thermally conducting material that is electrically conductive, since the alternative configuration of the thermally conducting material being electrically insulating is taught by Kawai and Beyer (see rejection of Claim 16, particularly pertaining to lines 23-28 of Claim 16 and the wording of “or” in line 26).
Re Claim 33, Kawai discloses a transistor with high electron mobility (FIG. 10; [0080]-[0083]), comprising:
a) an epitaxial layer (51, 14; [0080]), which comprises a semiconductor material ([0080]); and
b) at least one lateral and/or vertical transistor structure (18, 23, 24, 25; [0043]) on an upper side of the epitaxial layer (51, 14 in FIG. 11; [0083]);
c) a thermally conducting layer (11, 12; [0080]) on a bottom side of the epitaxial layer (51, 14; [0080]),
wherein the thermally conducting layer (11, 12), on the bottom side of the epitaxial layer (51, 14; [0080]), contacts at least 80% of the bottom side of the epitaxial layer (51, 14; [0080]),
wherein the transistor is produced by the method of Claim 16 (see rejection of Claim 16 and incorporation of Beyer).
Claims 23 and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Kawai and Beyer as applied to Claim 16 further in view of Nie et al (US 2016/0013045 A1, of record, hereafter Nie).
Re Claim 23, Kawai and Beyer teach the method according to Claim 16, but they do not explicitly disclose wherein the temporary wafer (Kawai: 28) is applied to the front side of the epitaxial layer (Kawai: 51) by gluing.
However, Nie teaches a method (FIG. 4; [0037]-[0039]) comprising wherein the temporary wafer (701; [0038]) is applied to the front side of the epitaxial layer (201; [0033]) by gluing ([0038]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 16 with the limitations of Nie to apply the temporary wafer (Kawai: 28) using glue to such that the carrier wafer can be easily removed while providing resistance to chemical attack during subsequent processing as taught by Nie ([0038]).
Re Claim 30, Kawai and Beyer teach the method according to Claim 16, but they do not explicitly disclose applying at least one electrical back-side contact to a bottom side of the epitaxial layer (Kawai: 51).
However, Nie teaches a method (FIG. 6; [0042]) comprising applying at least one electrical back-side contact (801; [0042]) to a bottom side of the epitaxial layer (201; [0042]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 16 with the limitations of Nie to utilize an electrical back-side contact (Nie: 801) to provide for electrical contact to the epitaxial layer (Kawai: 51) as taught by Nie ([0042]).
Re Claim 31, Kawai, Beyer, and Nie teach the method according to Claim 30, while Nie further teaches wherein the electrical back-side contact (801)
i) is applied to the bottom side of the epitaxial layer after the flat substrate has been removed, optionally after a local region of the thermally conducting layer has been removed; and/or
ii) comprises a material that has a specific electrical resistance of no more than 2-104 ohm-m; and/or
iii) comprises a material that has a specific thermal conductivity in the range of 150 to 380 W/(mK); and/or
iv) comprises a semiconductor material and/or metal ([0044]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 30 with the limitations of Nie to utilize an semiconductor/metal electrical back-side contact (Nie: 801) to provide for electrical contact to the epitaxial layer (Kawai: 51) as taught by Nie ([0042]).
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Kawai and Beyer as applied to Claim 16 further in view of Zhang et al (CN 107393858 A, of record, hereafter Zhang).
Re Claim 32, Kawai and Beyer teach the method according to Claim 16, but they do not explicitly disclose wherein the complete removal of the temporary wafer (Kawai: 28) from the upper side of the epitaxial layer (Kawai: 51) is effected by a method selected from the group consisting of laser lift-off method, wet-chemical etching method, dry-chemical etching method, thermal method, thermally activated smart-cut method, and combinations thereof, optionally combined with an ion implantation method.
However, Zhang teaches a method (FIG. 6; pg. 4, paras. 8-11) comprising wherein the complete removal of the temporary wafer (9; pg. 4, para. 11) from the upper side of the epitaxial layer (2; pg. 3, para. 17) is effected by a method selected from the group consisting of laser lift-off method, wet-chemical etching method, dry-chemical etching method (pg. 3, para. 16), thermal method, thermally activated smart-cut method, and combinations thereof, optionally combined with an ion implantation method.
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method as discussed for Claim 16 with the limitations of Zhang to use a dry etching method to remove the temporary wafer (Kawai: 28) to ensure its complete removal as taught by Zhang (pg. 3, para. 16).
Response to Arguments
Applicant’s arguments, see Remarks pg. 4, paras. 3-7, filed 12/15/2025, with respect to the rejection of Claim 1 under 35 U.S.C. 102(a)(1) in light of the new amended limitations have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kawai and Beyer under 35 U.S.C. 103. Applicant’s aforementioned arguments with respect to Claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments, see Remarks pg. 2, para. 4 to pg. 4, para. 2, filed 12/15/2025, with respect to the rejection of Claim 1 have been fully considered but are not persuasive because Kawai discloses an epitaxial layer containing at least two portions (51, 14; [0052] for 14 being epitaxial, [0085] for 51 being epitaxial), with the portion 14 comprising AlN ([0052]). This epitaxial layer (51, 14) as a whole is explicitly grown onto the flat substrate (52; [0085]), wherein the flat substrate (52) is completely removed ([0083]). The claim limitations make no mention of the epitaxial layer comprising only of (or more precisely, consisting of) a semiconductor material selected from the group consisting of GaN, AlN, Al.sub.xGa.sub.1-xN, InGaN, InAlGaN, AlScN, Ga.sub.2O.sub.3 and combinations thereof.
Also, to date, no specific arguments against the rejections of Claims 18-24 and 30-32, which ultimately depend from Claim 16, have been presented beyond they are allowable due to their dependence from Claim 16. Therefore, the examiner offers no response at this time.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892