DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 6, 8, 11 and 13-15, is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kawashima et al. (US 2020/0365498, hereinafter “Kawashima”).
Regarding claim 1, Kawashima teaches in Figs. 9-12 (Figs. 9 and 12 shown below) and related text a semiconductor device comprising:
a support member (219, Figs. 11-12 and ¶[0017]) having an obverse surface facing in a thickness direction (Fig. 11);
a semiconductor element (12, Fig. 11 and ¶[0046]) mounted on the obverse surface; and
a bonding layer (15, Fig. 11 and ¶[0050]) that bonds the obverse surface (230, Fig. 11 and ¶[0064]) and the semiconductor element,
wherein the support member includes a base member (218, Fig. 11 and ¶[0064]) or copper, ¶[0057], and a metal layer (220, Fig. 11 and ¶¶[0049] and [0057] or nickel plating on copper, ¶[0057]) mounted on the base member (218, Fig. 11 and ¶[0064]) and providing the obverse surface,
the support member includes a first region (e.g. 230, Fig. 11) in contact with the bonding layer (15, Fig. 11), and a second region (e.g. region outside of 230, Figs. 11-12) adjacent to the first region as viewed in the thickness direction,
the bonding layer contains a metal composition in a solid phase (e.g. solder, ¶[0050], and the second region is more repellent to a liquid phase of the metal composition than the first region (¶¶[0065]-[0067]).
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Regarding claim 2 (1), Kawashima teaches wherein a surface roughness of the second region (e.g. X outside of 230, Fig. 12) is greater than a surface roughness of the first region (e.g. 230 where semiconductor element is mounted, Fig. 11 and ¶[0065]).
Regarding claim 3 (2), Kawashima teaches wherein the second region is formed with a plurality of grooves (¶[0052]) extending in a direction crossing the thickness direction and aligned in parallel to each other (Fig. 12 and ¶[0052]).
Regarding claim 4 (3), Kawashima teaches wherein the metal layer (220, Figs. 11-12 or nickel plating layer, Figs. 11-12) has a first portion included in the first region (Figs. 11-12), and a second portion included in the second region (e.g. region outside of where semiconductor element is mounted, Figs. 11-12).
Regarding claim 6 (1), Kawashima teaches wherein the second region surrounds the first region as viewed in the thickness direction (Figs. 11-12).
Regarding claim 8 (1), Kawashima teaches wherein a composition of the base member includes copper (¶¶[0049] and [0057]).
Regarding claim 11 (1), Kawashima further teaches
a terminal (26, Fig. 9 and ¶[0051]) located away from the support member and electrically connected to the semiconductor element (12, Fig. 9 and ¶[0051]),
wherein at least a portion of the second region (e.g. region outside of 230, Figs. 9 and 12) is positioned between the semiconductor element (12, Fig. 9) and the terminal (26, Fig. 9), as viewed in the thickness direction (Figs. 9-12).
Regarding claim 13 (11), Kawashima further teaches a sealing resin (14, Figs. 9-10 and ¶[0046]) covering the semiconductor element (12, Figs. 9-10) and a portion of each of the support member and the terminal (Figs. 9-12), wherein the sealing resin is in contact with the second region (Fig. 10).
Regarding claim 14 (13), Kawashima further teaches a conductive member bonded to the semiconductor element and the terminal (i.e. Kawashima teaches that, while not shown, terminal 26 is electrically connected to a signal pad of the semiconductor element 12 which would necessarily require a conductive member being bonded to both the semiconductor element and the terminal, Fig. 9 and ¶[0051]).
Regarding claim 15 (13), Kawashima teaches wherein the support member (219, Figs. 9-12) has a reverse surface (i.e. surface of 210 facing away from 12, Figs. 10-11) facing away from the obverse surface in the thickness direction, and
the reverse surface is exposed from the sealing resin (14, Fig. 10).
Claim(s) 1-4, 6 and 8-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kobayashi et al. (US 2016/0207148, hereinafter “Kobayashi”).
Regarding claim 1, Kobayashi teaches in Figs. 9-11 (Fig. 10 shown below) and related text a semiconductor device comprising:
a support member (2, Fig. 10 and ¶[0040]) having an obverse surface facing in a thickness direction (Fig. 10);
a semiconductor element (3, Fig. 10 and ¶[0039]) mounted on the obverse surface; and
a bonding layer (5, Fig. 11 and ¶[0044]) that bonds the obverse surface (Fig. 10) and the semiconductor element (3, Fig. 10),
wherein the support member includes a base member (21, Fig. 10 and ¶[0040]), and a metal layer (22, Fig. 10 and ¶[0040]) mounted on the base member (21, Fig. 10) and providing the obverse surface,
the support member includes a first region in contact with the bonding layer (Fig. 10), and a second region (e.g. region outside of the bonding layer 5, Fig. 10) adjacent to the first region as viewed in the thickness direction,
the bonding layer contains a metal composition in a solid phase (e.g. solder, ¶[0044], and the second region is more repellent to a liquid phase of the metal composition than the first region (¶[0064]).
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Regarding claim 2 (1), Kobayashi teaches wherein a surface roughness of the second region (e.g. 22c, Fig. 10 and ¶[0064]) is greater than a surface roughness of the first region (e.g. region under bonding layer 5, Fig. 10 and ¶¶[0061]-[0064]).
Regarding claim 3 (2), Kobayashi teaches wherein the second region is formed with a plurality of grooves (Figs. 9-11 and ¶¶[0061]-[0064]) extending in a direction crossing the thickness direction and aligned in parallel to each other (Fig. 1, 7-12 and ¶[0052]).
Regarding claim 4 (3), Kobayashi teaches wherein the metal layer (22, Fig. 10) has a first portion included in the first region (e.g. under bonding layer 5, Fig. 10), and a second portion included in the second region (e.g. region outside of the bonding layer 5, Fig. 10).
Regarding claim 6 (1), Kobayashi teaches wherein the second region surrounds the first region as viewed in the thickness direction (Figs. 9-10).
Regarding claim 8 (1), Kobayashi teaches wherein a composition of the base member includes copper (¶[0040]).
Regarding claim 9 (1), Kobayashi teaches wherein a composition of the metal layer includes silver (¶[0040]).
Regarding claim 10 (1), Kobayashi teaches wherein the metal composition contains tin (¶[0064]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7, 9 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kawashima as applied to claim 1 and 11 above and further in view of Haga et al. (US 2017/0301612, hereinafter “Haga”).
Regarding claim 7 (1), teaching of Kawashima was discussed above in the rejection of claim 1. Kawashima, however, does not explicitly teach that the semiconductor element includes a first element and a second element that are spaced apart from each other, and that at least a portion of the second region is positioned between the first element and the second element, as viewed in the thickness direction. Including a first and second elements as part of the semiconductor element would, nonetheless, have been obvious to one of ordinary skill in the art, as evidenced by Haga (Fig. 1) in order to form a semiconductor device with desired characteristics and would amount to nothing more than using plurality of the same elements in one semiconductor device. It is noted that the semiconductor device disclosed by Kawashima includes first and second elements, as disclosed by Haga, at least a portion of the second region of each of the elements would be positioned between the first element and the second element, as viewed in the thickness direction.
Regarding claim 9 (1), teaching of Kawashima was discussed above in the rejection of claim 1 and includes wherein the metal layer includes nickel (¶[0057]). Kawashima, however, does not explicitly teach that the metal layer is silver. Haga, in a similar field of endeavor teaches that silver can be used instead of nickel. Thus, because these two materials were art-recognized equivalents before the effective filing date of the claimed invention, one of ordinary skill in the art would have found it obvious to substitute silver for nickel when forming metal layer disclosed by Kawashima.
Regarding claim 12 (11), teaching of Kawashima was discussed above in the rejection of claim 1 and includes wherein the base member (218, Fig. 10) is made out of copper (¶[0064]). While Kawashima does not explicitly teach that a composition of the terminal is the same as of the base member, forming the base member and the terminal, such as those disclosed by Kawashima from the same material would have been obvious to one of ordinary skill in the art as evidenced by Haga. Specifically, Haga teaches in Fig. 1 and related text that base member (e.g. 2, Fig. 1) and terminals (e.g. 3, Fig. 1) can be made from the same material (¶¶[0032] and [0035]), such as copper in order to simplifying manufacturing process of the semiconductor device (¶[0035]).
Thus, since the prior art teaches all of the claim elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the terminal from a material having the same composition as that of the base member in order to simplifying manufacturing process of the semiconductor device.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi as applied to claim 4 above, and further in view of Kosaka et al. (US 2023/0056682, hereinafter “Kosaka”).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Regarding claim 5 (4), teaching of Kobayashi was discussed above in the rejection of claim 4. Kobayashi, however, does not explicitly teach that the base member is exposed from the second portion of the metal layer in the second region.
Kosaka, in a similar field of endeavor, teaches in Fig. 8 and related text, that grooves similar to those disclosed by Kobayashi, can be formed in a second portion (i.e. portion where recesses 18 are formed, Fig. 8 and ¶[0044]) of a second region (e.g. region outside of the region in which the semiconductor element 3 is bonded, Fig. 8) of the metal layer (12, Fig. 8) so that the base member (11, Fig. 8 and ¶[0042]) is exposed form the second portion (Fig. 8) in order to suppress the bonding defects in the semiconductor device (¶[0100]).
Thus, since the prior art teaches all of the claimed elements, using such elements would lead to predictable results, and as such, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the grooves disclosed by Kobayashi so that the that the base member is exposed from the second portion of the metal layer in the second region in order to suppress the bonding defects in the semiconductor device.
Claim(s) 16-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et al. (US 2016/0207148, hereinafter “Kobayashi”) in view of Muto et al. (US 2006/0177967, hereinafter “Muto”).
Regarding claim 16, Kobayashi teaches in Figs. 9-12 (Fig. 10 shown above) and related text a method of manufacturing a semiconductor device comprising the steps of:
forming a metal layer (22, Fig. 10 and ¶¶[0040] and [0047]) on a base member (21, Fig. 10 and ¶[0040]) having an obverse surface facing in a thickness direction, such that the metal layer covers the obverse surface (Fig. 10),
arranging a bonding layer (5, Fig. 10 and ¶[0044]) on a first region of the metal layer (e.g. region under bonding layer 5, Fig. 10), the bonding material containing a metal composition (e.g. solder, ¶[0044]);
arranging a semiconductor element (3, Fig. 10 and ¶[0044]) on the bonding material; and
bonding the semiconductor element to the metal layer by the bonding material (¶[0044]),
wherein the method further comprises a step of irradiating a second region of the meal layer (i.e. region outside the region under bonding material 5, Fig. 10) with a laser (¶¶[0046]-[0052]), between the step of forming the metal layer and the step of arranging the semiconductor element (¶¶[0039], [0043] and [0052]), the second region being adjacent to the first region (Fig. 10).
While Kobayashi does not explicitly teach that the semiconductor element is bonded to the metal layer by melting and solidifying the bonding material, melting and solidifying the bonding material such as that disclosed by Kobayashi in order to bond semiconductor element to the metal layer is well-known in the art as evidenced by Muto. Specifically, Muto, in a similar field of endeavor teaches in Fig. 14 and related text that a semiconductor element (2, Fig. 14 and ¶[0109]), similar to that disclosed by Kobayashi, can be bonded to a metal layer (e.g. 21, Fig. 14 and ¶[0109]) by performing a reflow process that includes arranging the semiconductor element (2, Fig. 14) on the bonding material (11, Fig. 14) and melting and solidifying the bonding material in order to bond the semiconductor element to the metal layer (¶[0110]).
Thus, since the prior art teaches all of the claimed method steps, using such steps would lead to predictable results, and as such it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to melt and solidify the bonding material disclosed by Kobayashi in order to bond the semiconductor element to the metal layer.
Regarding claim 17 (16), the combined teaching of Kobayashi and Muto discloses wherein a plurality of grooves (e.g. 22b, Figs. 9-10) are formed in the second region in the step of irradiating the second region with a laser (Kobayashi, ¶¶[0046]-[0052]), the plurality of grooves extend in a direction crossing the thickness direction and being aligned in parallel to each other (Figs. 1, 7-8 and 12).
Regarding claim 18 (16), the combined teaching of Kobayashi and Muto discloses wherein a plurality of slits (e.g. 22b, Figs. 9-10) are formed in the second region in the step of irradiating the second region with a laser (Kobayashi, ¶¶[0046]-[0052]), the plurality of grooves extend in a direction crossing the thickness direction and being aligned in parallel to each other (Figs. 1, 7-8 and 12).
Conclusion
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/A.B.C/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893