Prosecution Insights
Last updated: October 04, 2026
Application No. 18/253,611

POWER SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
May 19, 2023
Priority
Feb 03, 2021 — JP 2021-015673 +1 more
Examiner
HUTSON, NICHOLAS LELAND
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Power Semiconductor Device, Ltd.
OA Round
3 (Non-Final)
68%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
75%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
21 granted / 31 resolved
At TC average
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
14 currently pending
Career history
58
Total Applications
across all art units

Statute-Specific Performance

§103
55.3%
+15.3% vs TC avg
§102
35.9%
-4.1% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 31 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7 April 2026 has been entered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3, and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu et al (US Patent 6201696B1) in view of Hori et al (US Publication 20160254255). Regarding claim 1, Shimizu teaches a power semiconductor device which includes an insulating substrate (Fig. 9, 2, column 18 lines 1-10, AlN or DBC), a semiconductor element provided on a front surface of the insulating substrate (Fig. 9, 22), and a gel-like first insulating material that seals the semiconductor element (Fig. 9, 91 – mislabeled as ‘9’ in Fig. 9, column 20 lines 55-60), the device comprising a plate-shaped terminal for electrically connecting the semiconductor element and external equipment (Fig. 9, 71), wherein a [[entire]] portion of the plate-shaped terminal surrounded by the first insulating material is covered with a second insulating material having a higher hardness than the first insulating material (Fig. 9, portion of 71 covered by 16 and surrounded by 91, resin harder than silicone gel, column 21 lines 2-5, column 2 line 7), wherein the gel-like first insulating material is in contact with a part of the semiconductor element and a part of the insulating substrate (Fig. 9, 91 in contact with part of 22 and 2). Shimizu does not specifically teach wherein a bonded portion between the semiconductor element and an electrode of the insulating substrate is covered with the second insulating material and the entire portion of the plate shaped terminal surrounded by the first insulating material is covered with a second insulating material. Hori teaches wherein a bonded portion between the semiconductor element and an electrode of the insulating substrate is entirely covered with the second insulating material (Fig. 1, bonded portion of 9a between 5 and 3 entirely covered with 13) It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Shimizu to include a bonded portion between the semiconductor element and an electrode of the insulating substrate is covered with the second insulating material (so fully covering the electrode) as taught by Hori in order to improve the reliability and operability of the device. Regarding claim 2, Shimizu as modified teaches the limitations of claim 1 upon which claim 2 depends. Shimizu does not specifically teach wherein one end of the plate-shaped terminal is bonded to an electrode of the front surface of the insulating substrate. Hori teaches wherein one end of the plate-shaped terminal is bonded to an electrode of the front surface of the insulating substrate (Fig. 1, 9a bonded to top/front surface of 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Shimizu to include the terminal bonded to an electrode of the front surface of the insulating substrate as taught by Hori in order to improve the mechanical robustness of the device. Regarding claim 3, Shimizu as modified teaches the limitations of claim 1 upon which claim 3 depends. Shimizu teaches further comprising a case that houses the insulating substrate, the semiconductor element, and the first insulating material (Fig. 9, case 6 housing 2, 22, and 91), wherein the plate-shaped terminal is provided in the case (Fig. 9, 71 in 8), and is electrically connected via a metal wire to an electrode of the front surface of the insulating substrate or an electrode of the semiconductor element (Fig. 9, wire 31 electrically connecting 71 to 22). Regarding claim 5, Shimizu as modified teaches the limitations of claim 1 upon which claim 5 depends. Shimizu teaches wherein the semiconductor element and the electrode of the insulating substrate are bonded by a sintered metal (Fig. 9, conductive film 1, column 18 lines 1-10). Furthermore, the present claim is drawn to a device, thus the method of sintering does not patentably distinguish the claimed invention from that of the invention of Simizu. It should be noted that a "product by process claim" is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in " product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above caselaw makes clear. See also MPEP 2113 [R-1]. Regarding claim 6, Shimizu as modified teaches the limitations of claim 1 upon which claim 6 depends. Shimizu teaches wherein the second insulating material is at least one of a polyamideimide resin, an epoxy resin, a fluororesin, an acrylic resin, and a silicone resin (Fig. 9, 16, column 21 lines 2-5, resin). Regarding claim 7, Shimizu as modified teaches the limitations of claim 1 upon which claim 7 depends. Shimizu teaches wherein the second insulating material is a resin, and is in contact with the first insulating material (Fig. 9, 16, column 21 lines 2-5, resin, in contact with 91). Regarding claim 8, Shimizu as modified teaches the limitations of claim 7 upon which claim 8 depends. Shimizu teaches wherein the second insulating material is at least one of a polyamideimide resin, an epoxy resin, a fluororesin, an acrylic resin, and a silicone resin (Fig. 9, 16, column 21 lines 2-5, resin). Response to Arguments Applicant's arguments filed 7 April 2026 have been fully considered but they are not persuasive. Also, there is also a new ground of rejection presented for claims 1-3 and 5-8 that only uses Hori as a secondary reference and a new reference to Shimizu is used as the primary reference. Applicant argues that Hori does not teach “a bonded portion between the semiconductor element and an electrode of the insulating substrate is covered with the second insulating material, and wherein the gel-like first insulating material is in contact with a part of the semiconductor element and a part of the insulating substrate”. Hori Fig. 1 teaches a bonded portion between the semiconductor element 5 and electrode 9a (the potion bonding 9a to substrate 3) is covered with the second insulating material 13, and a gel-like first insulating material 15 in contact with a part of the semiconductor element 5 and a part of the insulating substrate 3. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818 /JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

May 19, 2023
Application Filed
Jul 24, 2025
Non-Final Rejection mailed — §103
Oct 24, 2025
Response Filed
Jan 07, 2026
Final Rejection mailed — §103
Apr 07, 2026
Request for Continued Examination
Apr 13, 2026
Response after Non-Final Action
Sep 24, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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MICROELECTRONIC MECHANICAL FUSE AND ANTI-FUSE APPARATUS AND METHOD
3y 2m to grant Granted Sep 15, 2026
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METHOD FOR PRODUCING A MICROELECTRONIC DEVICE
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Patent 12713918
THERMAL TEST CHIP WITH STACKABLE METAL BASED HEATER AND SENSOR
3y 11m to grant Granted Aug 18, 2026
Patent 12707993
PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
3y 6m to grant Granted Aug 11, 2026
Patent 12701981
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
4y 5m to grant Granted Aug 04, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
68%
Grant Probability
75%
With Interview (+7.7%)
3y 4m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 31 resolved cases by this examiner. Grant probability derived from career allowance rate.

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