Prosecution Insights
Last updated: April 19, 2026
Application No. 18/253,611

POWER SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
May 19, 2023
Examiner
HUTSON, NICHOLAS LELAND
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hitachi Power Semiconductor Device, Ltd.
OA Round
2 (Final)
64%
Grant Probability
Moderate
3-4
OA Rounds
3y 1m
To Grant
68%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allow Rate
9 granted / 14 resolved
-3.7% vs TC avg
Minimal +4% lift
Without
With
+4.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 1m
Avg Prosecution
37 currently pending
Career history
51
Total Applications
across all art units

Statute-Specific Performance

§103
53.3%
+13.3% vs TC avg
§102
37.0%
-3.0% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 14 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Hori et al (US Publication 20160254255) in view of Hironaka et al (US Publication 20230268239). Regarding claim 1, Hori teaches A power semiconductor device which includes an insulating substrate (Fig. 2, 3, paragraph 29), a semiconductor element provided on a front surface of the insulating substrate (Fig. 2, 5 on 3, paragraph 29), the device comprising a plate-shaped terminal for electrically connecting the semiconductor element and external equipment (Fig. 2, 9ac/9a and 9bc/9b flat plate-like terminals); and additionally wherein an entire portion of the plate-shaped terminal surrounded by a first insulating material (not a gel though) is covered with a second insulating material (Fig. 2, the part of terminals 9a and 9b representing a ‘portion’ of the plate shaped terminal surrounded by 15 and covered by 13 “an epoxy resin, PPS, PBT, or the like” para 40). Hori does not specifically teach a gel-like first insulating material that seals the semiconductor element, such that the surrounding first insulating material is covered with a second insulating material having a higher hardness than the first insulating material. Hironaka teaches and a gel-like first insulating material that seals the semiconductor element (Fig. 1, 14, para 35 “silicone gel”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application for Hori to include a gel-like insulating material that seals the semiconductor element instead of the surrounding insulation there presently (figure 2, element 15) as taught by Hironaka in order to prevent partial discharge due to voids occurring when the main terminal is heated thus improving device reliability and operability. Therefore, Hori as modified teaches wherein an entire portion of the plate-shaped terminal surrounded by the first (gel) insulating material is covered with a second insulating material having a higher hardness than the first insulating material (Fig. 2, the part of terminals 9a and 9b representing a ‘portion’ of the plate shaped terminal surrounded by 15 silicone gel as taught by Hironaka and covered by 13 “an epoxy resin, PPS, PBT, or the like” Hori para 40, which is known to be harder than a gel). Regarding claim 2, Hori as modified teaches the limitations of claim 1 upon which claim 2 depends. Hori teaches wherein one end of the plate-shaped terminal is bonded to an electrode of the front surface of the insulating substrate (Fig. 2, 9a and 9b bonded to 33a and 33b). Regarding claim 3, Hori as modified teaches the limitations of claim 1 upon which claim 3 depends. Hori teaches further comprising a case (Fig. 2, housing 2) that houses the insulating substrate (Fig. 2, 3), the semiconductor element (Fig. 2, 5), and the first insulating material (Fig. 2, 13), wherein the plate-shaped terminal is provided in the case (Fig. 2, 14), and is electrically connected via a metal wire to an electrode of the front surface of the insulating substrate or an electrode of the semiconductor element (Fig. 2, 10). Regarding claim 4, Hori as modified teaches the limitations of claim 1 upon which claim 4 depends. Hori teaches wherein a bonded portion between the semiconductor element and an electrode of the insulating substrate is covered with the second insulating material (Fig. 2, intersection of elements 9a, 33a, and 13). Regarding claim 5, Hori as modified teaches the limitations of claim 4 upon which claim 5 depends. Hori teaches wherein the semiconductor element and the electrode of the insulating substrate are bonded by a sintered metal (Fig. 2, 9a and 9b on 33a and 33b, para 26 and 31). Regarding claim 6, Hori as modified teaches the limitations of claim 1 upon which claim 6 depends. Hori teaches wherein the second insulating material is at least one of a polyamideimide resin, an epoxy resin, a fluororesin, an acrylic resin, and a silicone resin (para 40 "epoxy resin, PPS, PBT, or the like", a thermosetting resin is a type of polyamideimide resin). Regarding claim 7, Hori as modified teaches the limitations of claim 1 upon which claim 7 depends. Hori teaches wherein the second insulating material is a resin, and is in contact with the first insulating material (para 40 "epoxy resin, PPS, PBT, or the like" second resin in contact with 15). Regarding claim 8, Hori as modified teaches the limitations of claim 7 upon which claim 8 depends. Hori teaches wherein the second insulating material is at least one of a polyamideimide resin, an epoxy resin, a fluororesin, an acrylic resin, and a silicone resin (para 40 "epoxy resin, PPS, PBT, or the like", a thermosetting resin is a type of polyamideimide resin). Response to Arguments Applicant's arguments filed 24 October 2025 have been fully considered but they are not persuasive. Applicant argues it would not have been obvious to modify Hori in the manner described in the 103 rejection of claim 1 stating that Hori prefers having a thermosetting resin such as an epoxy resin which would avoid excessive deformation (Hori, para 33 and 37) and that the modification of providing a silicone gel would change the principle of operation. This argument is respectfully traversed, as simply being able to ‘better’ operate in high temperatures (a specific external condition) does not change the principle of operation. Silicon gels and epoxy resins are well known in the art of semiconductors to be common insulation protection. Silicon is known to provide a better resistance to temperature fluctuations or moisture, so if a user was going to need the device in these conditions, silicone gel would be the better choice, thus making it obvious under certain conditions depending on what a user would prefer. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS HUTSON whose telephone number is (571)270-1750. The examiner can normally be reached Mon-Fri 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571 272 2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NICHOLAS LELAND HUTSON/ Examiner, Art Unit 2818 /JEFF W NATALINI/ Supervisory Patent Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

May 19, 2023
Application Filed
Jul 22, 2025
Non-Final Rejection — §103
Oct 24, 2025
Response Filed
Jan 05, 2026
Final Rejection — §103
Apr 07, 2026
Request for Continued Examination
Apr 13, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12520553
Forming Seams with Desirable Dimensions in Isolation Regions
2y 5m to grant Granted Jan 06, 2026
Patent 12512379
LOW-PROFILE SEALED SURFACE-MOUNT PACKAGE
2y 5m to grant Granted Dec 30, 2025
Patent 12422210
TECHNIQUES AND DEVICE STRUCTURES BASED UPON DIRECTIONAL DIELECTRIC DEPOSITION AND BOTTOM-UP FILL
2y 5m to grant Granted Sep 23, 2025
Patent 12419082
Field Effect Transistor Device
2y 5m to grant Granted Sep 16, 2025
Patent 12400929
Semiconductor Device and Method of Forming Graphene-Coated Core Embedded Within TIM
2y 5m to grant Granted Aug 26, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
64%
Grant Probability
68%
With Interview (+4.2%)
3y 1m
Median Time to Grant
Moderate
PTA Risk
Based on 14 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month