DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-8, 10-13, 15-19 and 21-26 have been considered but are moot of new rejection and interpretation of prior art.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8, 10-13, 15, 17-19 and 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq) (US 8,563,403 B1) in view of Zhu (US 2011/0227158 A1).
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In regards to claim 1, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses an apparatus comprising: a first wafer slice (items 102 plus 106 plus 108) comprising a first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) at a top of the first wafer slice (items 102 plus 106 plus 108), a first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320), a first bottom bonding layer (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320), and a first through-via (item 112), wherein: the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) includes a first front-end-of-line (FEOL) portion (item 104) and a first back-end-of-line (BEOL) portion (items 106, 108) that is over the first FEOL portion (item 104) and includes at least one first connecting layer (item 110); the first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320) is underneath the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) and includes at least one of a first barrier layer (items 304, 312 or 320) and a first thermally conductive layer (items 304, 312 or 320); the first bottom bonding layer (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320), which is formed of silicon oxide (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320), is underneath the first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320) and at a bottom of the first wafer slice (items 102 plus 106 plus 108); and the first through-via (item 112) vertically extends through the first bottom bonding layer (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320) and the first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320), and extends into the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6), wherein the at least one first connecting layer (item 110) is configured to electrically connect the first FEOL portion (item 104) and the first through-via (item 112); and a second wafer slice (items 404 plus 406 plus 408 plus 420) vertically stacked underneath the first wafer slice (items 102 plus 106 plus 108) and comprising a top bonding layer (item 420) at a top of the second wafer slice (items 404 plus 406 plus 408 plus 420) and configured to bond to the first wafer slice (items 102 plus 106 plus 108), a second device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) underneath the top bonding layer (item 420), and a top via (item 508), wherein: the second device region includes a second FEOL portion (item 404) and a second BEOL portion (items 406, 408) that is over the second FEOL portion (item 404) and includes at least one second connecting layer (item 410); the top via (item 508) vertically extends through the top bonding layer (item 420) and into the second BEOL portion (items 406, 408) of the second device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6); and the top bonding layer (item 420) in the second wafer slice (items 404 plus 406 plus 408), which is formed of silicon oxide, is directly bonded with the first bottom bonding layer (item 320), such that the top via (item 508) is in contact with the first through-via (item 112), and the second FEOL portion (item 404) is electrically connected to the first FEOL portion (item 104) through the at least one second connecting layer (item 410), the top via (item 404), the first through-via (item 112), and the at least one first connecting layer (item 110), but does not specifically disclose wherein the first barrier layer is formed of silicon nitride and the first thermally conductive layer is formed of aluminum nitride…the top via vertically extends through the top bonding layer and into the second BEOL portion of the second device region without extending into the second FEOL portion of the second device region.
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Zhu (Fig. 1a, 1a upside down and associated text) discloses wherein the first barrier layer (item 6) is formed of silicon nitride (paragraphs 19, 20) and the first thermally conductive layer is formed of aluminum nitride the top via (item 52) vertically extends through the top bonding layer (item 52) and into the second BEOL portion (item 56) of the second device region (items 54, 56) without extending into the second FEOL portion (item 54) of the second device region (items 54, 56).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Zhu for the purpose of an electrical connection and preventing diffusion (paragraph 20).
It would have been obvious to modify the invention to include a first barrier layer being formed of silicon nitride or a first thermally conductive layer is formed of aluminum nitride, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1 a and associated text) does not specifically disclose a second enhancement region…wherein the second enhancement region is underneath the second device region and includes at least one of a second barrier layer formed of silicon nitride and a second thermally conductive layer formed of aluminum nitride.
It would have been obvious to modify the invention to include disclose a second enhancement region…wherein the second enhancement region is underneath the second device region and includes at least one of a second barrier layer formed of silicon nitride and a second thermally conductive layer formed of aluminum nitride, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193 USPQ 8).
It would have been obvious to modify the invention to include a second barrier layer is formed of silicon nitride and second thermally conductive layer is formed of aluminum nitride, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 2, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein between the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) and the second device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6), any layer that comprises silicon is formed only of one or more silicon composites.
In regards to claim 3, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein: the first BEOL portion (items 106, 108) comprises first dielectric layers (items 106, 108), and a plurality of first connecting layers (item 110) that includes the at least one first connecting layer (item 110), wherein the plurality of first connecting layers (item 110) is partially covered by the first dielectric layers (items 106, 108) and is configured to electrically connect the first FEOL portion (item 104) to components outside the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6); the first FEOL portion (item 104) comprises a first contact layer underneath the first BEOL portion (items 106, 108), a first active layer underneath the first contact layer, and first isolation sections underneath the first contact layer and surrounding the first active layer (Respective active and insulating layers are not discussed in detail but implicit with IC technologies mentioned in col4. 4 lines 42-61, processor ICs in bulk semiconductor of SOI); the second BEOL portion (items 406, 408) comprises second dielectric layers (items 406, 408), and a plurality of second connecting layers (item 410) that includes the at least one second connecting layer (item 410), wherein the plurality of second connecting layers (item 410) is partially covered by the second dielectric layers (items 406, 408) and is configured to electrically connect the second FEOL portion (item 404) to components outside the second device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6); and the second FEOL portion (item 404) comprises a second contact layer underneath the second BEOL portion (items 406, 408), a second active layer underneath the second contact layer, and second isolation sections underneath the second contact layer and surrounding the second active layer (Respective active and insulating layers are not discussed in detail but implicit with IC technologies mentioned in col4. 4 lines 42-61, processor ICs in bulk semiconductor of SOI).
In regards to claim 4, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses a bump structure (item 516), which is formed over the first wafer slice (item 104, 106, 108), and electrically coupled to the first FEOL portion (item 104) through the plurality of first connecting layers (item 110) in the first BEOL portion (item 104), but does not specifically disclose a plurality of bumps.
It would have been obvious to modify the invention to include a plurality of bumps, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193
USPQ 8).
In regards to claim 5, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein the first through-via (item 112) of the first wafer slice (items 104, 106, 108) does not extend toward or into a particular portion of the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) where the first active layer is located, and the top via (item 508) of the second wafer slice (items 404, 406, 408, 402) does not extend toward or into a particular portion of the second device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) where the second active layer is located.
In regards to claim 6, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein the first isolation sections extend vertically beyond a bottom surface of the first active layer to define a first opening within the first isolation sections and underneath the first active layer (Figs. 4 to 5 and col. 4, lines 42 - 61 the removal of a semiconductor base layer (102) in order to expose a semiconductor substrate (epi-layer 104) which may be embodied as bulk substrate (i.e. implicitly with shallow trench regions which extend beyond the active region) or as SOI (i.e. implicitly with a passivation layer, known in the art as buried oxide layer, BOX) which would lead to a coplanar arrangement of isolation regions and active regions).
In regards to claim 7, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein a bottom surface of each first isolation section and the bottom surface of the first active layer are coplanar, such that the first FEOL portion (item 104) of the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) has a flat bottom surface (Figs. 4 to 5 and col. 4, lines 42 - 61 the removal of a semiconductor base layer (102) in order to expose a semiconductor substrate (epi-layer 104) which may be embodied as bulk substrate (i.e. implicitly with shallow trench regions which extend beyond the active region) or as SOI (i.e. implicitly with a passivation layer, known in the art as buried oxide layer, BOX) which would lead to a coplanar arrangement of isolation regions and active regions).
In regards to claim 8, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein the first wafer slice (items 104, 106, 108) further includes a first passivation layer (items 304, 312 or 320) vertically between the first device region (not shown, but mentioned, col. 3, line 65 through col. 4, line 6) and the first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320), wherein: the first passivation layer (items 304, 312 or 320) continuously covers the first active layer and at least covers bottom surfaces of the first isolation sections; and the first passivation layer (items 304, 312 or 320) is formed of silicon oxide.
In regards to claim 10, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein: the first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320) includes the first barrier layer (items 304, 312 or 320) underneath the first passivation layer (items 304, 312 or 320) and the first thermally conductive layer (items 304, 312 or 320) underneath the first barrier layer (items 304, 312 or 320) and over the first bottom bonding layer (item 320), but does not specifically disclose the first barrier layer (items 304, 312 or 320) has with a thickness between 0.2 μm and 10 μm; and the first thermally conductive layer (items 304, 312 or 320) has a thickness between 0.1 μm and 20 μm. Examiner notes that the Applicant’s invention does not require both, but at least one of a barrier layer and a thermally conductive layer (see Applicant’s claim 1).
Zhu (Fig. 1a and associated text) discloses respective layer, e.g. a silicon nitride layer (6). D2 teaches a maximum thickness of only 100 nm in order to avoid too large capacitance. Since the application is silent about an unexpected advantage of a greater thickness, the claimed feature lacks an inventive step over Zhu (with greater thicknesses constituting a predictable disadvantage).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a first barrier layer with a thickness between 0.2 μm and 10 μm; and a first thermally conductive layer having thickness between 0.1 μm and 20 μm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 11, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein the second isolation sections extend vertically beyond a bottom surface of the second active layer to define a second opening within the second isolation sections and underneath the second active layer (Figs. 4 to 5 and col. 4, lines 42 - 61 the removal of a semiconductor base layer (102) in order to expose a semiconductor substrate (epi-layer 104) which may be embodied as bulk substrate (i.e. implicitly with shallow trench regions which extend beyond the active region) or as SOI (i.e. implicitly with a passivation layer, known in the art as buried oxide layer, BOX) which would lead to a coplanar arrangement of isolation regions and active regions). The above line of reasoning for claims 6-8 applies mutatis mutandis for the second wafer slice (which corresponds to item 400, col. 6, line 66 through col. 7, line 31).
In regards to claim 12, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein a bottom surface of each second isolation section and the bottom surface of the second active layer are coplanar, such that the second FEOL portion of the second device region has a flat bottom surface (Figs. 4 to 5 and col. 4, lines 42 - 61 the removal of a semiconductor base layer (102) in order to expose a semiconductor substrate (epi-layer 104) which may be embodied as bulk substrate (i.e. implicitly with shallow trench regions which extend beyond the active region) or as SOI (i.e. implicitly with a passivation layer, known in the art as buried oxide layer, BOX) which would lead to a coplanar arrangement of isolation regions and active regions). The above line of reasoning for claims 6-8 applies mutatis mutandis for the second wafer slice (which corresponds to item 400, col. 6, line 66 through col. 7, line 31).
In regards to claim 13, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein the second wafer slice further includes a second passivation layer vertically between the second FEOL portion of the second device region and the second enhancement region, wherein: the second passivation layer continuously covers the second active layer and at least covers bottom surfaces of the second isolation sections; and the second passivation layer is formed of silicon oxide (Figs. 4 to 5 and col. 4, lines 42 - 61 the removal of a semiconductor base layer (102) in order to expose a semiconductor substrate (epi-layer 104) which may be embodied as bulk substrate (i.e. implicitly with shallow trench regions which extend beyond the active region) or as SOI (i.e. implicitly with a passivation layer, known in the art as buried oxide layer, BOX) which would lead to a coplanar arrangement of isolation regions and active regions). The above line of reasoning for claims 6-8 applies mutatis mutandis for the second wafer slice (which corresponds to item 400, col. 6, line 66 through col. 7, line 31)
In regards to claim 15, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) discloses wherein: the second enhancement region includes the second barrier layer underneath the second passivation layer and the second thermally conductive layer underneath the second barrier layer; the second barrier layer has a thickness between 0.2 μm and 10 μm; and the second thermally conductive layer has a thickness between 0.1 μm and 20 μm (See rejection of claim 10 above).
It would have been obvious to modify the invention to include a second enhancement region includes the second barrier layer underneath the second passivation layer and the second thermally conductive layer underneath the second barrier layer; the second barrier layer having a thickness between 0.2 μm and 10 μm; and the second thermally conductive layer having a thickness between 0.1 μm and 20 μm, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193
USPQ 8).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a second barrier layer with a thickness between 0.2 μm and 10 μm; and a second thermally conductive layer having thickness between 0.1 μm and 20 μm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 17, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) discloses wherein the first FEOL portion (item 12, Zhu) provides a switch field-effect transistor (FET) (item 14, Zhu), and the second FEOL portion (item 54, 56, Zhu) provides another switch FET (item 55, Zhu).
Examiner notes the claims 18-25 below relate to a third stacked wafer slice. A person of ordinary skill in the art appreciates that further stacked slices are obvious in the field of 3D IC stacks. Therefore the previous arguments above for the first and/or second wafer slices apply mutatis mutandis.
It would have been obvious to modify the invention to include a third wafer slice, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193
USPQ 8).
In regards to claim 18, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claim 1] discloses further comprising a third wafer slice vertically stacked underneath the second wafer slice and comprising a third top bonding layer at a top of the third wafer slice and configured to bond to the second wafer slice, a third device region underneath the third top bonding layer, and a third top via, wherein: the second wafer slice further comprises a second bottom bonding layer underneath the second enhancement region, and a second through-via that vertically extends through the second bottom bonding layer and the second enhancement region and into the second device region; the at least one second connecting layer is configured to electrically connect the second FEOL portion and the second through-via; the third device region includes a third FEOL portion and a third BEOL portion that is over the third FEOL portion and includes at least one third connecting layer; the third top via vertically extends through the third top bonding layer and into the third BEOL portion of the third device region without extending into the third FEOL portion of the third device region, wherein the at least one third connecting layer is configured to electrically connect the third FEOL portion and the third top via; the second bottom bonding layer and the third top bonding layer are formed of silicon oxide and directly (bonded) boned with each other, such that the third top via is in contact with the second through-via, such that the second FEOL portion is electrically connected to the third FEOL portion through the at least one third connecting layer, the third top via, the second through-via, and the at least one second connecting layer.
In regards to claim 19, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claim 2] discloses wherein between the first device region and the second device region and between the second device region and the third device region, any layer that comprises silicon is formed only of one or more silicon composites.
In regards to claim 21, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claims 8 and 10] discloses wherein: the second wafer slice further includes a second passivation layer vertically between the second device region and the second enhancement region; wherein: the second through-via extends through the second bottom bonding layer, the second enhancement region, the second passivation layer and into the second device region; and the second passivation layer is formed of silicon oxide
In regards to claim 22, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claims 8 and 10] discloses wherein: the first enhancement region includes the first barrier layer underneath the first device region and the first thermally conductive layer underneath the first barrier layer and over the first bottom bonding layer; the first barrier layer has a thickness between 0.2 μm and 10 μm; the first thermally conductive layer has a thickness between 0.1 μm and 20 μm; the second enhancement region includes the second barrier layer underneath the second passivation layer and the second thermally conductive layer underneath the second barrier layer and over the second bottom bonding layer; the second barrier layer has a thickness between 0.2 μm and 10 μm; and the second thermally conductive layer has a thickness between 0.1 μm and 20 μm.
In regards to claim 23, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claim 13] discloses wherein the third wafer slice further includes a third passivation layer underneath the third FEOL portion of the third device region, wherein the third passivation layer is formed of silicon oxide.
In regards to claim 24, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claim 14] discloses wherein the third wafer slice further includes a third enhancement region underneath the third passivation layer, wherein the third enhancement region includes at least one of a third barrier layer and a third thermally conductive layer.
In regards to claim 25, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) as modified by Zhu (Fig. 1a and associated text) [See rejection of claims 8, 10, 15] discloses wherein: the third enhancement region includes the third barrier layer underneath the third passivation layer and the third thermally conductive layer underneath the third barrier layer; the third barrier layer is formed of silicon nitride with a thickness between 0.2 μm and 10 μm; and the third thermally conductive layer is formed of aluminum nitride with a thickness between 0.1 μm and 20 μm.
Claim(s) 16 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq) (US 8,563,403 B1) in view of Zhu (US 2011/0227158 A1) applied to the claims above, and further in view of Costa et al. (Costa) (US 2016/0100489 A1).
In regards to claim 16, Farooq as modified by Zhu does not specifically disclose wherein the mold compound has a thermal conductivity greater than 1 W/m.Math.K and a dielectric constant less than 8.
In regards to claim 26, Farooq as modified by Zhu does not specifically disclose wherein the mold compound has a thermal conductivity greater than 1 W/m.Math.K and a dielectric constant less than 8.
In regard to claims 16 and 26, Costa (paragraphs 26, 35, Figs 1, 1A and associated text) discloses a mold compound (item 20); wherein the mold compound has a thermal conductivity greater than 1 W/m.Math.K (paragraphs 26, 35, Fig. 1A) and a dielectric constant less than 8 (~3.8 for CoolPoly D5506).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Costa for the purpose of heat dissipation, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Farooq et al. (Farooq) (US 8,563,403 B1) in view of Zhu (US 2011/0227158 A1) as applied to the claims above, and further in view of Dai et al. (Dai) (CN 106098609 A).
In regards to claims 22, Farooq (Figs. 1, 4, 5, 8, 14-16, 16 upside down and associated text) discloses wherein: the first enhancement region (items 304, 312, 320, 304 plus 312 or 304 plus 312 plus 320) includes the first barrier layer (items 304, 312 or 320) underneath the first passivation layer (items 304, 312 or 320) and the first thermally conductive layer (items 304, 312 or 320) underneath the first barrier layer (items 304, 312 or 320) and over the first bottom bonding layer (item 320), but does not specifically disclose the second passivation layer is formed of silicon oxide; the second enhancement region includes the second barrier layer underneath the second passivation layer and the second thermally conductive layer underneath the second barrier layer and over the second bottom bonding layer.
It would have been obvious to modify the invention to include a second passivation layer is formed of silicon oxide; the second enhancement region includes the second barrier layer underneath the second passivation layer and the second thermally conductive layer underneath the second barrier layer and over the second bottom bonding layer, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art (St. Regis Paper Co. v. Bemis Co., 193
USPQ 8).
Farooq does not specifically disclose the first/second barrier layer (items 304, 312 or 320) has with a thickness between 0.2 μm and 10 μm; and the first/second thermally conductive layer (items 304, 312 or 320) has a thickness between 0.1 μm and 20 μm. Examiner notes that the Applicant’s invention does not require both, but at least one of a barrier layer and a thermally conductive layer (see Applicant’s claim 1).
Zhu (Fig. 1a and associated text) discloses respective layer, e.g. a silicon nitride layer (6). D2 teaches a maximum thickness of only 100 nm in order to avoid too large capacitance. Since the application is silent about an unexpected advantage of a greater thickness, the claimed feature lacks an inventive step over Zhu (with greater thicknesses constituting a predictable disadvantage).
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a first barrier layer with a thickness between 0.2 μm and 10 μm; and a first thermally conductive layer having thickness between 0.1 μm and 20 μm, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
Dai discloses in the context of high performance SOI device (like Farooq and Zhu) to provide an aluminum nitride, AlN, layer of a thickness of 0,5 μm (see e.g. par. [0055]) buried in the insulating silicon oxide, SiO, layer. Dai teaches to do so in order to improve the thermal conductivity of the insulating layer, because the thermal conductivity of AlN is 200 times that of SiO (see par. [0007]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Dai for the purpose of improving thermal conductivity of the insulating layer (paragraph 7).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 May 16, 2026
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