DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP Publication No. 3-161823 (Xia), cited by Applicant.
Xia discloses (Figs. 3A, 3B, 4-6, 8)
Claim 1. (Original) A semiconductor device comprising:
a conductor 2 / 3 including an obverse surface (top) including a first edge (near label 210), a reverse surface (bottom) spaced apart from the obverse surface (top) in a thickness direction and including a second edge (near labels 24 and 35), and an intermediate surface 211 connected to the first edge (near label 210) and the second edge (near labels 24 and 35);
a semiconductor element 4 supported on the obverse surface (top) and electrically connected to the conductor 2 / 3; and
a sealing resin 6 that covers the obverse surface (top), the semiconductor element 4, and at least a portion of the intermediate surface 211, wherein
the reverse surface (bottom) of the conductor 2 /3 is exposed from the sealing resin 6,
the first edge (near label 210) is located outward from the second edge (near labels 24 and 35) as viewed in the thickness direction,
in a cross section orthogonal to the first edge (near label 210), the intermediate surface 211 includes a first point (annotated with the right dot below) located between the first edge (near label 210) and the second edge (near labels 24 and 35) and a second point (annotated with the left dot below) located between the first edge (near label 210) and the first point (annotated with the right dot below), and
a first distance from the obverse surface (top) to the first point (annotated with the right dot below) in the thickness direction is smaller than a second distance from the obverse surface (top) to the second point (annotated with the left dot below) in the thickness direction.
PNG
media_image1.png
416
586
media_image1.png
Greyscale
Xia discloses
Claim 2. (Original) The semiconductor device according to claim 1, wherein the intermediate surface 211 includes a recess (groove) that is recessed toward one side in the thickness direction, and the recess (groove) is located between the first edge (near label 210) and the first point (annotated with the right dot below) as viewed in the thickness direction.
Xia discloses
Claim 3. (Currently Amended) The semiconductor device according to claim 1, wherein the intermediate surface 211 includes a projection (point) that projects in the thickness direction, and the projection (point) is located between the first point (annotated with the right dot below) and the second edge (near labels 24 and 35) as viewed in the thickness direction.
Xia discloses
Claim 4. (Currently Amended) The semiconductor device according to claim 1, wherein the intermediate surface 211 includes an end extending from the first edge (near label 210) in the thickness direction and an overhang, the end including a third edge (near label 21) opposite from the first edge (near label 210) in the thickness direction, the overhang extending from the third edge (near label 21) to the first point (annotated with the right dot below).
Xia discloses
Claim 5. (Original) The semiconductor device according to claim 4, wherein the dimension of the end in the thickness direction is equal to or greater than the second distance.
Xia discloses
Claim 6. (Currently Amended) The semiconductor device according to claim 4, wherein the dimension of the end in the thickness direction is smaller than a distance from the obverse surface (top) to the reverse surface (bottom) in the thickness direction.
Xia discloses
Claim 7. (Original) The semiconductor device according to claim 5, wherein the dimension of the end in the thickness direction is equal to a distance from the obverse surface (top) to the reverse surface (bottom) in the thickness direction.
Xia discloses
Claim 10. (Currently Amended) The semiconductor device according to claim 1, wherein the conductor 2 / 3 includes a die pad 2 and a terminal 3 spaced apart from the die pad 2, and
the die pad 2 includes a first obverse surface (top) that forms a portion of the obverse surface (top) of the conductor 2 / 3, whereas the terminal 3 includes a second obverse surface (top) that forms another portion of the obverse surface (top) of the conductor 2 / 3,
the semiconductor element 4 is supported on the first obverse surface (top) of the die pad 2, and
the terminal 3 is electrically connected to the semiconductor element 4.
Xia discloses
Claim 11. (Original) The semiconductor device according to claim 10, further comprising a wire 5 bonded to the semiconductor element 4 and the second obverse surface (top) of the terminal 3, and the wire 5 is covered with the sealing resin 6.
Xia discloses
Claim 12. (Currently Amended) The semiconductor device according to claim 10, wherein the terminal 3 includes a first reverse surface (bottom) forming a portion of the reverse surface (bottom) of the conductor 2 / 3, and a side surface connected to the second obverse surface (top) and the first reverse surface (bottom), the side surface being exposed from the sealing resin 6.
Xia discloses
Claim 13. (Original) The semiconductor device according to claim 12, wherein the terminal 3 includes an intermediate surface 321 connected to the second obverse surface (top) and the first reverse surface (bottom) and at least partially covered with the sealing resin 6, the intermediate surface 311 being connected to the side surface.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xia as applied to claim 7 above, and further in view of JP Publication No. 2015-38917 (Oishi), cited by Applicant.
Xia fails to disclose
Claim 8. (Original) The semiconductor device according to claim 7, wherein a portion of the overhang is exposed from the sealing resin.
Oishi teaches (Fig. 2, 7)
A semiconductor device comprising:
wherein a portion of the overhang is exposed from the sealing resin 30.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to expose the overhang in Xia. The motivation would be to provide a contact region for the selected area based on routine engineering design considerations as shown in Oishi. See MPEP 2144.04.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xia as applied to claim 4 above, and further in view of JP Publication No. 2016-105432 (Takahashi), cited by Applicant.
Xia fails to disclose
Claim 9. (Currently Amended) The semiconductor device according to claim 4, wherein the end has a surface roughness greater than a surface roughness of the overhang.
Takahashi teaches (Fig. 1)
A semiconductor device comprising:
wherein the end has a surface roughness greater than a surface roughness of the overhang.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to roughen a portion of the end in Xia. The motivation would be to prevent the sealing resin from peeling from one portion and does affect the adhesion of the semiconductor as discussed in Takahashi ([0008], translation).
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xia as applied to claim 1 above, and further in view of JP Publication No. 2008-258411 (Kasuya), cited by Applicant.
Xia fails to disclose
Claim 14. (Currently Amended) The semiconductor device according to claim 1, further comprising a coating layer that covers the reverse surface of the conductor, wherein the coating layer contains a metallic element.
Kasuya teaches (Figs. 1, 2)
A semiconductor device comprising:
a coating layer 12 that covers the reverse surface 9A of the conductor 4, wherein the coating layer 12 contains a metallic element ([0023] of the translation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a coating in Xia. The motivation would be to improve mounting strength as discussed in Kasuya ([0011], translation).
Kasuya teaches
Claim 15. (Original) The semiconductor device according to claim 14, wherein the conductor 4 includes a side surface 9B connected to the obverse surface (top) and the reverse surface 9A and exposed from the sealing resin 5, the side surface 9B being covered with the coating layer 12.
Kasuya teaches ([0023])
Claim 16. (Currently Amended) The semiconductor device according to claim 14, wherein the metallic element includes at least one of nickel and palladium.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Nos. 6,208,023 (Nakayama), 6,927,483 (Lee), U.S. Patent Application Publication Nos. 2006/0071351 (Lange), 2008/0286901 (Khor), 2009/0230526 (Chen), 2010/0258934 (Chang Chien), 2011/0233753 (Camacho) 2016/0293531 (Lu), 2021/0118818 (Cadag), 2022/0157742 (Lee) teaches a conductor at least partially covered with a sealing resin.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
Prosecution Insights