DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see Remarks, filed 1/15/26, with respect to the rejection(s) of claim(s) 1-7, 10-13 under 35 USC 102 have been fully considered and are persuasive in light of the amendments. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sirinorakul.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-19 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1, the following terminology is unclear:
does “a same position as the reverse surface in the thickness direction” mean coplanar in thickness direction or aligned vertically?
does “the first point being spaced apart from the second edge as viewed in the thickness direction” refer to horizontal spacing, projected spacing, Euclidean distance?
These phrases coupled with “the first edge is located outward from the second edge” makes determining the locations of the first edge, the first point, the second edge, the second point, and the newly recited “first / second curved section” and “an apex” (which are not described in the specification) potentially ambiguous.
The other claims are rejected as being dependent on claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 10-13, 17-19 is/are, to the extent taught and understood, rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent No.
Sirinorakul discloses (at least Fig. 10)
1. (Currently Amended) A semiconductor device comprising:
A semiconductor device comprising:
a conductor LEAD/DAP including an obverse surface (top) including a first edge, a reverse (bottom) surface spaced apart from the obverse surface in a thickness direction and including a second edge, and an intermediate surface connected to the first edge and the second edge (see annotations below);
a semiconductor element DIE supported on the obverse surface and electrically connected to the conductor LEAD/DAP; and
a sealing resin ENCAPSULATION that covers the obverse surface, the semiconductor element DIE, and at least a portion of the intermediate surface,
wherein
the reverse surface of the conductor LEAD/DAP is exposed from the sealing resin ENCAPSULATION,
the second edge (see annotations) being located at a same position as the reverse surface in the thickness direction,
the first edge (see annotations) is located outward from the second edge as viewed in the thickness direction,
in a cross section orthogonal to the first edge, the intermediate surface includes a first point located between the first edge and the second edge and a second point located between the first edge and the first point, the first point being spaced apart from the second edge as viewed in the thickness direction (see annotations),
a first distance from the obverse surface to the first point in the thickness direction is smaller than a second distance from the obverse surface to the second point in the thickness direction,
[AltContent: ][AltContent: textbox (second curved section)][AltContent: ][AltContent: textbox (first edge)]the intermediate surface includes a first curved section that is convex toward the obverse surface, and in the cross section, the first point is located at an apex of the first curved section in the thickness direction.
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[AltContent: textbox (first curved section )][AltContent: textbox (second point)][AltContent: textbox (first point)][AltContent: textbox (intermediate surface)][AltContent: textbox (second edge)]
Sirinorakul discloses
2. (Currently Amended) The semiconductor device according to claim 1, wherein
the intermediate surface includes a recess (groove) that is recessed toward one side in the thickness direction,
the recess (groove) is located between the first edge and the first point as viewed in the thickness direction, and
the recess has an apex located offset toward the obverse surface with respect to the second point in the thickness direction (see annotations).
Sirinorakul discloses
3. (Currently Amended) The semiconductor device according to claim 1, wherein the intermediate surface includes a projection (asperities) that projects in the thickness direction, and the projection (asperities) is located between the first point and the second edge as viewed in the thickness direction (see annotations).
Sirinorakul discloses
4. (Currently Amended) The semiconductor device according to claim 1, wherein the intermediate surface includes an end extending from the first edge in the thickness direction and an overhang, the end including a third edge opposite from the first edge in the thickness direction, the overhang extending from the third edge to the first point (see annotations).
Sirinorakul discloses
5. (Original) The semiconductor device according to claim 4, wherein the dimension of the end in the thickness direction is equal to or greater than the second distance (see annotations).
Sirinorakul discloses
6. (Currently Amended) The semiconductor device according to claim 4, wherein the dimension of the end in the thickness direction is smaller than a distance from the obverse surface (top) to the reverse surface (bottom) in the thickness direction (see annotations).
Sirinorakul discloses
7. (Currently Amended) The semiconductor device according to claim 5, wherein the dimension of the end in the thickness direction is equal to a distance from the obverse surface (top) to the reverse surface (bottom) in the thickness direction.
Sirinorakul discloses
10. (Currently Amended) The semiconductor device according to claim 1, wherein the conductor LEAD/DAP includes a die pad DAP and a terminal LEAD spaced apart from the die pad DAP, and
the die pad DAP includes a first obverse surface (top) that forms a portion of the obverse surface (top) of the conductor LEAD/DAP, whereas the terminal LEAD includes a second obverse surface (top) that forms another portion of the obverse surface (top) of the conductor LEAD/DAP,
the semiconductor element DIE is supported on the first obverse surface (top) of the die pad DAP, and
the terminal LEAD is electrically connected to the semiconductor element DIE.
Sirinorakul discloses
11. (Currently Amended) The semiconductor device according to claim 10, further comprising a wire BOND bonded to the semiconductor element DIE and the second obverse surface (top) of the terminal LEAD, and the wire BOND is covered with the sealing resin ENCAPSULATION.
Sirinorakul discloses
12. (Currently Amended) The semiconductor device according to claim 10, wherein the terminal LEAD includes a first reverse surface (bottom) forming a portion of the reverse surface (bottom) of the conductor LEAD/DAP, and a side surface connected to the second obverse surface (top) and the first reverse surface (bottom), the side surface being exposed from the sealing resin ENCAPSULATION.
Sirinorakul discloses
13. (Currently Amended) The semiconductor device according to claim 12, wherein the terminal LEAD includes an intermediate surface connected to the second obverse surface (top) and the first reverse surface (bottom) and at least partially covered with the sealing resin ENCAPSULATION, the intermediate surface being connected to the side surface.
Sirinorakul discloses
17. (New) The semiconductor device according to claim 1, wherein the intermediate surface further includes a second curved section extending from the second edge toward the first curved section, and the second curved section does not overlap with the reverse surface (bottom) as viewed in the thickness direction (seen annotations).
Sirinorakul discloses
18. (New) The semiconductor device according to claim 1, wherein the intermediate surface includes an end extending from the first edge in the thickness direction, and the end includes a third edge opposite from the first edge in the thickness direction, the first edge overlapping with the third edge as viewed in the thickness direction (see annotations).
Sirinorakul discloses
19. (New) The semiconductor device according to claim 1, wherein a distance between the reverse surface (bottom) and the first point in the thickness direction is greater than the first distance (see annotations).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sirinorakul as applied to claim 7 above, and further in view of JP Publication No. 2015-38917 (Oishi), cited by Applicant.
Sirinorakul fails to disclose
8. (Currently Amended) The semiconductor device according to claim 7, wherein a portion of the overhang is exposed from the sealing resin.
Oishi teaches (Fig. 2, 7)
A semiconductor device comprising:
wherein a portion of the overhang is exposed from the sealing resin 30.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to expose the overhang in Sirinorakul. The motivation would be to provide a contact region for the selected area based on routine engineering design considerations as shown in Oishi. See MPEP 2144.04.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sirinorakul as applied to claim 4 above, and further in view of JP Publication No. 2016-105432 (Takahashi), cited by Applicant.
Sirinorakul fails to disclose
9. (Currently Amended) The semiconductor device according to claim 4, wherein the end has a surface roughness greater than a surface roughness of the overhang.
Takahashi teaches (Fig. 1)
A semiconductor device comprising:
wherein the end has a surface roughness greater than a surface roughness of the overhang.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to roughen a portion of the end in Sirinorakul. The motivation would be to prevent the sealing resin from peeling from one portion and does affect the adhesion of the semiconductor as discussed in Takahashi ([0008], translation).
Claim(s) 14-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sirinorakul as applied to claim 1 above, and further in view of JP Publication No. 2008-258411 (Kasuya), cited by Applicant.
Sirinorakul fails to specifically disclose
14. (Currently Amended) The semiconductor device according to claim 1, further comprising a coating layer that covers the reverse surface of the conductor, wherein the coating layer contains a metallic element.
Kasuya teaches (Figs. 1, 2)
A semiconductor device comprising:
a coating layer 12 that covers the reverse surface 9A of the conductor 4, wherein the coating layer 12 contains a metallic element ([0023] of the translation).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a coating in Sirinorakul. The motivation would be to improve mounting strength as discussed in Kasuya ([0011], translation).
Kasuya teaches
15. (Currently Amended) The semiconductor device according to claim 14, wherein the conductor 4 includes a side surface 9B connected to the obverse surface (top) and the reverse surface 9A and exposed from the sealing resin 5, the side surface 9B being covered with the coating layer 12.
Kasuya teaches ([0023])
16. (Currently Amended) The semiconductor device according to claim 14, wherein the metallic element includes at least one of nickel and palladium.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. Patent Application Publication Nos. 2009/0034225 (Shoji), 2010/0276800 (Yanase), JP Publication No. 6656961 (堂前 克之)teach a curved conductor at least partially covered with a sealing resin.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TERESA M. ARROYO/ Primary Examiner, Art Unit 2893
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