DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on September 02nd, 2026, has been entered.
Upon entrance of the Amendment, claims 1-3, 6, 8, 9, 11, 12, 17, 19, and 20 were amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 7, 18, and 20 are rejected under 35 U.S.C. 102A(a)(2) as being anticipated by Park (U.S. Patent No. 10,848,657).
Regarding claim 1, Park discloses a semiconductor module, comprising:
a substrate (Fig. 16, print circuit board substrate 2021);
a first semiconductor element on the substrate (Fig. 16, first semiconductor element including image sensor element 2024 and print circuit board CERAMIC PCB), wherein the first semiconductor element includes:
a wiring electrically connected to the substrate (Fig. 16, wirings in the print circuit board CERAMIC PCB electrically connected to the substrate 2021); and
a pixel region of an imaging element on an upper surface of the first semiconductor element, wherein the upper surface is opposite to a surface facing the substrate (Fig. 16, image sensor 2024 having imaging element on its upper surface, opposite to a surface facing the substrate 2021);
a second semiconductor element on the upper surface of the first semiconductor element, and at a position different from the pixel region on the upper surface of the first semiconductor element (Fig. 16, circuit element 2022); and
a cover part that covers the first semiconductor element and the second semiconductor element from the upper surface with respect to at least a part of a region excluding the pixel region (Fig. 16, element 2027, the claim does not specify direction of the claimed “covers”).
Regarding claim 2, Park discloses the cover part is a frame having an opening corresponding to the pixel region, and the cover part is attached to the substrate to cover the first semiconductor element and the second semiconductor element from the upper surface (Fig. 16).
Regarding claim 4, Park discloses the frame has a hollow structure with respect to a region including the second semiconductor element and the wiring (Fig. 16).
Regarding claim 7, Park discloses the frame is in contact with the upper surface of the second semiconductor element (Fig. 16, note that the claim does not require a direct contact).
Regarding claim 18, Park discloses each of the first and second semiconductor elements is a semiconductor chip and forms a chip-on-chip structure (Fig. 16).
Regarding claim 20, Park discloses a method for manufacturing a semiconductor module, the method comprising
forming a second semiconductor element (Fig. 16, circuit element 2022) on an upper surface of a first semiconductor element (first semiconductor element including image sensor element 2024 and print circuit board CERAMIC PCB), and at a position different from a pixel region of an imaging element on the upper surface of the first semiconductor element (Fig. 16), wherein the first semiconductor element includes including the pixel region (Fig. 16, the pixel region on top surface image sensor 2024);
mounting the first semiconductor element on a substrate (Fig. 16, the first semiconductor element is mounted on the print circuit board substrate 2021);
forming a wiring electrically connected to the substrate (ig. 16, wirings in the print circuit board CERAMIC PCB electrically connected to the substrate 2021); and
forming a cover part that covers the first semiconductor element and the second semiconductor element from the upper surface with respect to at least a part of a region excluding the pixel region (Fig. 16, element 2017).
Allowable Subject Matter
Claims 3, 5-6, 8-17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 3, the prior art fails to anticipate or render obvious the claimed limitations including “the frame is formed by includes one of resin or metal” in combination with the limitations recited in claims 1-2.
Regarding to claim 5, the prior art fails to anticipate or render obvious the claimed limitations including “a filling portion filled in a sealed manner in a region including the second semiconductor element and the wiring” in combination with the limitations recited in claims 1-2 and 4.
Regarding to claim 8, the prior art fails to anticipate or render obvious the claimed limitations including “the inner wall has a wrinkle pattern” in combination with the limitations recited in claims 1-2 and the rest of limitations recited in claim 8.
Regarding to claim 9, the prior art fails to anticipate or render obvious the claimed limitations including “the frame has a tapered structure in which an inner wall of the frame that faces the pixel region is inclined toward the pixel region” in combinations with the limitation recited in claims 1-2.
Regarding to claim 10, the prior art fails to anticipate or render obvious the claimed limitations including “a sealing glass bonded to an upper surface of the frame via a sealing material” in combination with the limitations recited in claims 1-2.
Regarding to claim 12, the prior art fails to anticipate or render obvious the claimed limitations including “the cover part is a sealing resin that seals a portion of the semiconductor module other than an opening corresponding to the pixel region” in combination with the limitations recited in claim 1.
Regarding to claim 15, the prior art fails to anticipate or render obvious the claimed limitations including “the cover part is a molding resin that covers a back surface and a side surface of the second semiconductor element” in combination with the limitations recited in claim 1.
Regarding to claim 19, the prior art fails to anticipate or render obvious the claimed limitations including “the first semiconductor element and the second semiconductor element form a chip-on-wafer structure” in combination with the limitations recited in claim 1 and the rest of limitations recited in claim 19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VU A VU/Primary Examiner, Art Unit 2897
